1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD$"); 36 37/* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69#ifdef HAVE_KERNEL_OPTION_HEADERS 70#include "opt_device_polling.h" 71#endif 72 73#include <sys/param.h> 74#include <sys/endian.h> 75#include <sys/systm.h> 76#include <sys/sockio.h> 77#include <sys/mbuf.h> 78#include <sys/malloc.h> 79#include <sys/kernel.h> 80#include <sys/module.h> 81#include <sys/socket.h> 82#include <sys/sysctl.h> 83#include <sys/taskqueue.h> 84 85#include <net/if.h> 86#include <net/if_arp.h> 87#include <net/ethernet.h> 88#include <net/if_dl.h> 89#include <net/if_media.h> 90 91#include <net/bpf.h> 92 93#include <net/if_types.h> 94#include <net/if_vlan_var.h> 95 96#include <netinet/in_systm.h> 97#include <netinet/in.h> 98#include <netinet/ip.h> 99#include <netinet/tcp.h> 100 101#include <machine/bus.h> 102#include <machine/resource.h> 103#include <sys/bus.h> 104#include <sys/rman.h> 105 106#include <dev/mii/mii.h> 107#include <dev/mii/miivar.h> 108#include "miidevs.h" 109#include <dev/mii/brgphyreg.h> 110 111#ifdef __sparc64__ 112#include <dev/ofw/ofw_bus.h> 113#include <dev/ofw/openfirm.h> 114#include <machine/ofw_machdep.h> 115#include <machine/ver.h> 116#endif 117 118#include <dev/pci/pcireg.h> 119#include <dev/pci/pcivar.h> 120 121#include <dev/bge/if_bgereg.h> 122 123#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 124#define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126MODULE_DEPEND(bge, pci, 1, 1, 1); 127MODULE_DEPEND(bge, ether, 1, 1, 1); 128MODULE_DEPEND(bge, miibus, 1, 1, 1); 129 130/* "device miibus" required. See GENERIC if you get errors here. */ 131#include "miibus_if.h" 132 133/* 134 * Various supported device vendors/types and their names. Note: the 135 * spec seems to indicate that the hardware still has Alteon's vendor 136 * ID burned into it, though it will always be overriden by the vendor 137 * ID in the EEPROM. Just to be safe, we cover all possibilities. 138 */ 139static const struct bge_type { 140 uint16_t bge_vid; 141 uint16_t bge_did; 142} const bge_devs[] = { 143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 145 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 149 150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 151 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 227 228 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 229 230 { TC_VENDORID, TC_DEVICEID_3C996 }, 231 232 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 233 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 234 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 235 236 { 0, 0 } 237}; 238 239static const struct bge_vendor { 240 uint16_t v_id; 241 const char *v_name; 242} const bge_vendors[] = { 243 { ALTEON_VENDORID, "Alteon" }, 244 { ALTIMA_VENDORID, "Altima" }, 245 { APPLE_VENDORID, "Apple" }, 246 { BCOM_VENDORID, "Broadcom" }, 247 { SK_VENDORID, "SysKonnect" }, 248 { TC_VENDORID, "3Com" }, 249 { FJTSU_VENDORID, "Fujitsu" }, 250 251 { 0, NULL } 252}; 253 254static const struct bge_revision { 255 uint32_t br_chipid; 256 const char *br_name; 257} const bge_revisions[] = { 258 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 259 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 260 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 261 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 262 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 263 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 264 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 265 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 266 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 267 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 268 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 269 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 270 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 271 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 272 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 273 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 274 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 275 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 276 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 277 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 278 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 279 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 280 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 281 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 282 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 283 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 284 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 285 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 286 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 287 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 288 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 289 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 290 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 291 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 292 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 293 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 294 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 295 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 296 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 297 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 298 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 299 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 300 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 301 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 302 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 303 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 304 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 305 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 306 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 307 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 308 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 309 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 310 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 311 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 312 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 313 /* 5754 and 5787 share the same ASIC ID */ 314 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 315 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 316 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 317 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 318 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 319 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 320 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 321 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 322 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 323 324 { 0, NULL } 325}; 326 327/* 328 * Some defaults for major revisions, so that newer steppings 329 * that we don't know about have a shot at working. 330 */ 331static const struct bge_revision const bge_majorrevs[] = { 332 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 333 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 334 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 335 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 336 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 337 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 338 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 339 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 340 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 341 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 342 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 343 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 344 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 345 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 346 /* 5754 and 5787 share the same ASIC ID */ 347 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 348 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 349 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 350 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 351 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 352 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 353 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 354 355 { 0, NULL } 356}; 357 358#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 359#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 360#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 361#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 362#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 363#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 364#define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 365 366const struct bge_revision * bge_lookup_rev(uint32_t); 367const struct bge_vendor * bge_lookup_vendor(uint16_t); 368 369typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 370 371static int bge_probe(device_t); 372static int bge_attach(device_t); 373static int bge_detach(device_t); 374static int bge_suspend(device_t); 375static int bge_resume(device_t); 376static void bge_release_resources(struct bge_softc *); 377static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 378static int bge_dma_alloc(struct bge_softc *); 379static void bge_dma_free(struct bge_softc *); 380static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 381 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 382 383static void bge_devinfo(struct bge_softc *); 384static int bge_mbox_reorder(struct bge_softc *); 385 386static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 387static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 388static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 389static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 390static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 391 392static void bge_txeof(struct bge_softc *, uint16_t); 393static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 394static int bge_rxeof(struct bge_softc *, uint16_t, int); 395 396static void bge_asf_driver_up (struct bge_softc *); 397static void bge_tick(void *); 398static void bge_stats_clear_regs(struct bge_softc *); 399static void bge_stats_update(struct bge_softc *); 400static void bge_stats_update_regs(struct bge_softc *); 401static struct mbuf *bge_check_short_dma(struct mbuf *); 402static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 403 uint16_t *, uint16_t *); 404static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 405 406static void bge_intr(void *); 407static int bge_msi_intr(void *); 408static void bge_intr_task(void *, int); 409static void bge_start_locked(struct ifnet *); 410static void bge_start(struct ifnet *); 411static int bge_ioctl(struct ifnet *, u_long, caddr_t); 412static void bge_init_locked(struct bge_softc *); 413static void bge_init(void *); 414static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 415static void bge_stop(struct bge_softc *); 416static void bge_watchdog(struct bge_softc *); 417static int bge_shutdown(device_t); 418static int bge_ifmedia_upd_locked(struct ifnet *); 419static int bge_ifmedia_upd(struct ifnet *); 420static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 421 422static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 423static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 424 425static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 426static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 427 428static void bge_setpromisc(struct bge_softc *); 429static void bge_setmulti(struct bge_softc *); 430static void bge_setvlan(struct bge_softc *); 431 432static __inline void bge_rxreuse_std(struct bge_softc *, int); 433static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 434static int bge_newbuf_std(struct bge_softc *, int); 435static int bge_newbuf_jumbo(struct bge_softc *, int); 436static int bge_init_rx_ring_std(struct bge_softc *); 437static void bge_free_rx_ring_std(struct bge_softc *); 438static int bge_init_rx_ring_jumbo(struct bge_softc *); 439static void bge_free_rx_ring_jumbo(struct bge_softc *); 440static void bge_free_tx_ring(struct bge_softc *); 441static int bge_init_tx_ring(struct bge_softc *); 442 443static int bge_chipinit(struct bge_softc *); 444static int bge_blockinit(struct bge_softc *); 445static uint32_t bge_dma_swap_options(struct bge_softc *); 446 447static int bge_has_eaddr(struct bge_softc *); 448static uint32_t bge_readmem_ind(struct bge_softc *, int); 449static void bge_writemem_ind(struct bge_softc *, int, int); 450#ifndef __HAIKU__ 451static void bge_writembx(struct bge_softc *, int, int); 452#endif 453#ifdef notdef 454static uint32_t bge_readreg_ind(struct bge_softc *, int); 455#endif 456static void bge_writemem_direct(struct bge_softc *, int, int); 457static void bge_writereg_ind(struct bge_softc *, int, int); 458 459static int bge_miibus_readreg(device_t, int, int); 460static int bge_miibus_writereg(device_t, int, int, int); 461static void bge_miibus_statchg(device_t); 462#ifdef DEVICE_POLLING 463static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 464#endif 465 466#define BGE_RESET_START 1 467#define BGE_RESET_STOP 2 468static void bge_sig_post_reset(struct bge_softc *, int); 469static void bge_sig_legacy(struct bge_softc *, int); 470static void bge_sig_pre_reset(struct bge_softc *, int); 471static void bge_stop_fw(struct bge_softc *); 472static int bge_reset(struct bge_softc *); 473static void bge_link_upd(struct bge_softc *); 474 475/* 476 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 477 * leak information to untrusted users. It is also known to cause alignment 478 * traps on certain architectures. 479 */ 480#ifdef BGE_REGISTER_DEBUG 481static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 482static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 483static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 484#endif 485static void bge_add_sysctls(struct bge_softc *); 486static void bge_add_sysctl_stats_regs(struct bge_softc *, 487 struct sysctl_ctx_list *, struct sysctl_oid_list *); 488static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 489 struct sysctl_oid_list *); 490static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 491 492static device_method_t bge_methods[] = { 493 /* Device interface */ 494 DEVMETHOD(device_probe, bge_probe), 495 DEVMETHOD(device_attach, bge_attach), 496 DEVMETHOD(device_detach, bge_detach), 497 DEVMETHOD(device_shutdown, bge_shutdown), 498 DEVMETHOD(device_suspend, bge_suspend), 499 DEVMETHOD(device_resume, bge_resume), 500 501 /* MII interface */ 502 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 503 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 504 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 505 506 DEVMETHOD_END 507}; 508 509static driver_t bge_driver = { 510 "bge", 511 bge_methods, 512 sizeof(struct bge_softc) 513}; 514 515static devclass_t bge_devclass; 516 517DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 518DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 519 520static int bge_allow_asf = 1; 521 522TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 523 524SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 525SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 526 "Allow ASF mode if available"); 527 528#define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 529#define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 530#define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 531#define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 532#define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 533 534static int 535bge_has_eaddr(struct bge_softc *sc) 536{ 537#ifdef __sparc64__ 538 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 539 device_t dev; 540 uint32_t subvendor; 541 542 dev = sc->bge_dev; 543 544 /* 545 * The on-board BGEs found in sun4u machines aren't fitted with 546 * an EEPROM which means that we have to obtain the MAC address 547 * via OFW and that some tests will always fail. We distinguish 548 * such BGEs by the subvendor ID, which also has to be obtained 549 * from OFW instead of the PCI configuration space as the latter 550 * indicates Broadcom as the subvendor of the netboot interface. 551 * For early Blade 1500 and 2500 we even have to check the OFW 552 * device path as the subvendor ID always defaults to Broadcom 553 * there. 554 */ 555 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 556 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 557 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 558 return (0); 559 memset(buf, 0, sizeof(buf)); 560 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 561 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 562 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 563 return (0); 564 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 565 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 566 return (0); 567 } 568#endif 569 return (1); 570} 571 572static uint32_t 573bge_readmem_ind(struct bge_softc *sc, int off) 574{ 575 device_t dev; 576 uint32_t val; 577 578 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 579 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 580 return (0); 581 582 dev = sc->bge_dev; 583 584 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 585 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 586 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 587 return (val); 588} 589 590static void 591bge_writemem_ind(struct bge_softc *sc, int off, int val) 592{ 593 device_t dev; 594 595 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 596 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 597 return; 598 599 dev = sc->bge_dev; 600 601 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 602 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 603 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 604} 605 606#ifdef notdef 607static uint32_t 608bge_readreg_ind(struct bge_softc *sc, int off) 609{ 610 device_t dev; 611 612 dev = sc->bge_dev; 613 614 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 615 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 616} 617#endif 618 619static void 620bge_writereg_ind(struct bge_softc *sc, int off, int val) 621{ 622 device_t dev; 623 624 dev = sc->bge_dev; 625 626 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 627 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 628} 629 630static void 631bge_writemem_direct(struct bge_softc *sc, int off, int val) 632{ 633 CSR_WRITE_4(sc, off, val); 634} 635 636#ifndef __HAIKU__ 637static void 638#else 639void 640#endif 641bge_writembx(struct bge_softc *sc, int off, int val) 642{ 643 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 644 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 645 646 CSR_WRITE_4(sc, off, val); 647 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0) 648 CSR_READ_4(sc, off); 649} 650 651/* 652 * Map a single buffer address. 653 */ 654 655static void 656bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 657{ 658 struct bge_dmamap_arg *ctx; 659 660 if (error) 661 return; 662 663 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 664 665 ctx = arg; 666 ctx->bge_busaddr = segs->ds_addr; 667} 668 669static uint8_t 670bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 671{ 672 uint32_t access, byte = 0; 673 int i; 674 675 /* Lock. */ 676 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 677 for (i = 0; i < 8000; i++) { 678 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 679 break; 680 DELAY(20); 681 } 682 if (i == 8000) 683 return (1); 684 685 /* Enable access. */ 686 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 687 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 688 689 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 690 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 691 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 692 DELAY(10); 693 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 694 DELAY(10); 695 break; 696 } 697 } 698 699 if (i == BGE_TIMEOUT * 10) { 700 if_printf(sc->bge_ifp, "nvram read timed out\n"); 701 return (1); 702 } 703 704 /* Get result. */ 705 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 706 707 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 708 709 /* Disable access. */ 710 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 711 712 /* Unlock. */ 713 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 714 CSR_READ_4(sc, BGE_NVRAM_SWARB); 715 716 return (0); 717} 718 719/* 720 * Read a sequence of bytes from NVRAM. 721 */ 722static int 723bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 724{ 725 int err = 0, i; 726 uint8_t byte = 0; 727 728 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 729 return (1); 730 731 for (i = 0; i < cnt; i++) { 732 err = bge_nvram_getbyte(sc, off + i, &byte); 733 if (err) 734 break; 735 *(dest + i) = byte; 736 } 737 738 return (err ? 1 : 0); 739} 740 741/* 742 * Read a byte of data stored in the EEPROM at address 'addr.' The 743 * BCM570x supports both the traditional bitbang interface and an 744 * auto access interface for reading the EEPROM. We use the auto 745 * access method. 746 */ 747static uint8_t 748bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 749{ 750 int i; 751 uint32_t byte = 0; 752 753 /* 754 * Enable use of auto EEPROM access so we can avoid 755 * having to use the bitbang method. 756 */ 757 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 758 759 /* Reset the EEPROM, load the clock period. */ 760 CSR_WRITE_4(sc, BGE_EE_ADDR, 761 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 762 DELAY(20); 763 764 /* Issue the read EEPROM command. */ 765 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 766 767 /* Wait for completion */ 768 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 769 DELAY(10); 770 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 771 break; 772 } 773 774 if (i == BGE_TIMEOUT * 10) { 775 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 776 return (1); 777 } 778 779 /* Get result. */ 780 byte = CSR_READ_4(sc, BGE_EE_DATA); 781 782 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 783 784 return (0); 785} 786 787/* 788 * Read a sequence of bytes from the EEPROM. 789 */ 790static int 791bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 792{ 793 int i, error = 0; 794 uint8_t byte = 0; 795 796 for (i = 0; i < cnt; i++) { 797 error = bge_eeprom_getbyte(sc, off + i, &byte); 798 if (error) 799 break; 800 *(dest + i) = byte; 801 } 802 803 return (error ? 1 : 0); 804} 805 806static int 807bge_miibus_readreg(device_t dev, int phy, int reg) 808{ 809 struct bge_softc *sc; 810 uint32_t val; 811 int i; 812 813 sc = device_get_softc(dev); 814 815 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 816 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 817 CSR_WRITE_4(sc, BGE_MI_MODE, 818 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 819 DELAY(80); 820 } 821 822 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 823 BGE_MIPHY(phy) | BGE_MIREG(reg)); 824 825 /* Poll for the PHY register access to complete. */ 826 for (i = 0; i < BGE_TIMEOUT; i++) { 827 DELAY(10); 828 val = CSR_READ_4(sc, BGE_MI_COMM); 829 if ((val & BGE_MICOMM_BUSY) == 0) { 830 DELAY(5); 831 val = CSR_READ_4(sc, BGE_MI_COMM); 832 break; 833 } 834 } 835 836 if (i == BGE_TIMEOUT) { 837 device_printf(sc->bge_dev, 838 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 839 phy, reg, val); 840 val = 0; 841 } 842 843 /* Restore the autopoll bit if necessary. */ 844 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 845 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 846 DELAY(80); 847 } 848 849 if (val & BGE_MICOMM_READFAIL) 850 return (0); 851 852 return (val & 0xFFFF); 853} 854 855static int 856bge_miibus_writereg(device_t dev, int phy, int reg, int val) 857{ 858 struct bge_softc *sc; 859 int i; 860 861 sc = device_get_softc(dev); 862 863 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 864 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 865 return (0); 866 867 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 868 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 869 CSR_WRITE_4(sc, BGE_MI_MODE, 870 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 871 DELAY(80); 872 } 873 874 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 875 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 876 877 for (i = 0; i < BGE_TIMEOUT; i++) { 878 DELAY(10); 879 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 880 DELAY(5); 881 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 882 break; 883 } 884 } 885 886 /* Restore the autopoll bit if necessary. */ 887 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 888 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 889 DELAY(80); 890 } 891 892 if (i == BGE_TIMEOUT) 893 device_printf(sc->bge_dev, 894 "PHY write timed out (phy %d, reg %d, val %d)\n", 895 phy, reg, val); 896 897 return (0); 898} 899 900static void 901bge_miibus_statchg(device_t dev) 902{ 903 struct bge_softc *sc; 904 struct mii_data *mii; 905 sc = device_get_softc(dev); 906 mii = device_get_softc(sc->bge_miibus); 907 908 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 909 (IFM_ACTIVE | IFM_AVALID)) { 910 switch (IFM_SUBTYPE(mii->mii_media_active)) { 911 case IFM_10_T: 912 case IFM_100_TX: 913 sc->bge_link = 1; 914 break; 915 case IFM_1000_T: 916 case IFM_1000_SX: 917 case IFM_2500_SX: 918 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 919 sc->bge_link = 1; 920 else 921 sc->bge_link = 0; 922 break; 923 default: 924 sc->bge_link = 0; 925 break; 926 } 927 } else 928 sc->bge_link = 0; 929 if (sc->bge_link == 0) 930 return; 931 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 932 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 933 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 934 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 935 else 936 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 937 938 if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) { 939 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 940 if ((IFM_OPTIONS(mii->mii_media_active) & 941 IFM_ETH_TXPAUSE) != 0) 942 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 943 else 944 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 945 if ((IFM_OPTIONS(mii->mii_media_active) & 946 IFM_ETH_RXPAUSE) != 0) 947 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 948 else 949 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 950 } else { 951 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 952 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 953 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 954 } 955} 956 957/* 958 * Intialize a standard receive ring descriptor. 959 */ 960static int 961bge_newbuf_std(struct bge_softc *sc, int i) 962{ 963 struct mbuf *m; 964 struct bge_rx_bd *r; 965 bus_dma_segment_t segs[1]; 966 bus_dmamap_t map; 967 int error, nsegs; 968 969 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 970 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 971 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 972 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 973 if (m == NULL) 974 return (ENOBUFS); 975 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 976 } else { 977 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 978 if (m == NULL) 979 return (ENOBUFS); 980 m->m_len = m->m_pkthdr.len = MCLBYTES; 981 } 982 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 983 m_adj(m, ETHER_ALIGN); 984 985 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 986 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 987 if (error != 0) { 988 m_freem(m); 989 return (error); 990 } 991 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 992 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 993 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 994 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 995 sc->bge_cdata.bge_rx_std_dmamap[i]); 996 } 997 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 998 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 999 sc->bge_cdata.bge_rx_std_sparemap = map; 1000 sc->bge_cdata.bge_rx_std_chain[i] = m; 1001 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 1002 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 1003 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1004 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1005 r->bge_flags = BGE_RXBDFLAG_END; 1006 r->bge_len = segs[0].ds_len; 1007 r->bge_idx = i; 1008 1009 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1010 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 1011 1012 return (0); 1013} 1014 1015/* 1016 * Initialize a jumbo receive ring descriptor. This allocates 1017 * a jumbo buffer from the pool managed internally by the driver. 1018 */ 1019static int 1020bge_newbuf_jumbo(struct bge_softc *sc, int i) 1021{ 1022 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1023 bus_dmamap_t map; 1024 struct bge_extrx_bd *r; 1025 struct mbuf *m; 1026 int error, nsegs; 1027 1028 MGETHDR(m, M_DONTWAIT, MT_DATA); 1029 if (m == NULL) 1030 return (ENOBUFS); 1031 1032 m_cljget(m, M_DONTWAIT, MJUM9BYTES); 1033 if (!(m->m_flags & M_EXT)) { 1034 m_freem(m); 1035 return (ENOBUFS); 1036 } 1037 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1038 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1039 m_adj(m, ETHER_ALIGN); 1040 1041 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1042 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1043 if (error != 0) { 1044 m_freem(m); 1045 return (error); 1046 } 1047 1048 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1049 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1050 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1051 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1052 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1053 } 1054 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1055 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1056 sc->bge_cdata.bge_rx_jumbo_sparemap; 1057 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1058 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1059 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1060 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1061 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1062 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1063 1064 /* 1065 * Fill in the extended RX buffer descriptor. 1066 */ 1067 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1068 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1069 r->bge_idx = i; 1070 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1071 switch (nsegs) { 1072 case 4: 1073 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1074 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1075 r->bge_len3 = segs[3].ds_len; 1076 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1077 case 3: 1078 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1079 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1080 r->bge_len2 = segs[2].ds_len; 1081 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1082 case 2: 1083 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1084 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1085 r->bge_len1 = segs[1].ds_len; 1086 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1087 case 1: 1088 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1089 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1090 r->bge_len0 = segs[0].ds_len; 1091 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1092 break; 1093 default: 1094 panic("%s: %d segments\n", __func__, nsegs); 1095 } 1096 1097 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1098 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1099 1100 return (0); 1101} 1102 1103static int 1104bge_init_rx_ring_std(struct bge_softc *sc) 1105{ 1106 int error, i; 1107 1108 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1109 sc->bge_std = 0; 1110 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1111 if ((error = bge_newbuf_std(sc, i)) != 0) 1112 return (error); 1113 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1114 } 1115 1116 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1117 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1118 1119 sc->bge_std = 0; 1120 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1121 1122 return (0); 1123} 1124 1125static void 1126bge_free_rx_ring_std(struct bge_softc *sc) 1127{ 1128 int i; 1129 1130 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1131 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1132 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1133 sc->bge_cdata.bge_rx_std_dmamap[i], 1134 BUS_DMASYNC_POSTREAD); 1135 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1136 sc->bge_cdata.bge_rx_std_dmamap[i]); 1137 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1138 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1139 } 1140 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1141 sizeof(struct bge_rx_bd)); 1142 } 1143} 1144 1145static int 1146bge_init_rx_ring_jumbo(struct bge_softc *sc) 1147{ 1148 struct bge_rcb *rcb; 1149 int error, i; 1150 1151 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1152 sc->bge_jumbo = 0; 1153 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1154 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1155 return (error); 1156 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1157 } 1158 1159 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1160 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1161 1162 sc->bge_jumbo = 0; 1163 1164 /* Enable the jumbo receive producer ring. */ 1165 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1166 rcb->bge_maxlen_flags = 1167 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1168 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1169 1170 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1171 1172 return (0); 1173} 1174 1175static void 1176bge_free_rx_ring_jumbo(struct bge_softc *sc) 1177{ 1178 int i; 1179 1180 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1181 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1182 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1183 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1184 BUS_DMASYNC_POSTREAD); 1185 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1186 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1187 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1188 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1189 } 1190 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1191 sizeof(struct bge_extrx_bd)); 1192 } 1193} 1194 1195static void 1196bge_free_tx_ring(struct bge_softc *sc) 1197{ 1198 int i; 1199 1200 if (sc->bge_ldata.bge_tx_ring == NULL) 1201 return; 1202 1203 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1204 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1205 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1206 sc->bge_cdata.bge_tx_dmamap[i], 1207 BUS_DMASYNC_POSTWRITE); 1208 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1209 sc->bge_cdata.bge_tx_dmamap[i]); 1210 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1211 sc->bge_cdata.bge_tx_chain[i] = NULL; 1212 } 1213 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1214 sizeof(struct bge_tx_bd)); 1215 } 1216} 1217 1218static int 1219bge_init_tx_ring(struct bge_softc *sc) 1220{ 1221 sc->bge_txcnt = 0; 1222 sc->bge_tx_saved_considx = 0; 1223 1224 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1225 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1226 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1227 1228 /* Initialize transmit producer index for host-memory send ring. */ 1229 sc->bge_tx_prodidx = 0; 1230 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1231 1232 /* 5700 b2 errata */ 1233 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1234 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1235 1236 /* NIC-memory send ring not used; initialize to zero. */ 1237 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1238 /* 5700 b2 errata */ 1239 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1240 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1241 1242 return (0); 1243} 1244 1245static void 1246bge_setpromisc(struct bge_softc *sc) 1247{ 1248 struct ifnet *ifp; 1249 1250 BGE_LOCK_ASSERT(sc); 1251 1252 ifp = sc->bge_ifp; 1253 1254 /* Enable or disable promiscuous mode as needed. */ 1255 if (ifp->if_flags & IFF_PROMISC) 1256 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1257 else 1258 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1259} 1260 1261static void 1262bge_setmulti(struct bge_softc *sc) 1263{ 1264 struct ifnet *ifp; 1265 struct ifmultiaddr *ifma; 1266 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1267 int h, i; 1268 1269 BGE_LOCK_ASSERT(sc); 1270 1271 ifp = sc->bge_ifp; 1272 1273 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1274 for (i = 0; i < 4; i++) 1275 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1276 return; 1277 } 1278 1279 /* First, zot all the existing filters. */ 1280 for (i = 0; i < 4; i++) 1281 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1282 1283 /* Now program new ones. */ 1284 if_maddr_rlock(ifp); 1285 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1286 if (ifma->ifma_addr->sa_family != AF_LINK) 1287 continue; 1288 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1289 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1290 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1291 } 1292 if_maddr_runlock(ifp); 1293 1294 for (i = 0; i < 4; i++) 1295 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1296} 1297 1298static void 1299bge_setvlan(struct bge_softc *sc) 1300{ 1301 struct ifnet *ifp; 1302 1303 BGE_LOCK_ASSERT(sc); 1304 1305 ifp = sc->bge_ifp; 1306 1307 /* Enable or disable VLAN tag stripping as needed. */ 1308 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1309 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1310 else 1311 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1312} 1313 1314static void 1315bge_sig_pre_reset(struct bge_softc *sc, int type) 1316{ 1317 1318 /* 1319 * Some chips don't like this so only do this if ASF is enabled 1320 */ 1321 if (sc->bge_asf_mode) 1322 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1323 1324 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1325 switch (type) { 1326 case BGE_RESET_START: 1327 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1328 BGE_FW_DRV_STATE_START); 1329 break; 1330 case BGE_RESET_STOP: 1331 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1332 BGE_FW_DRV_STATE_UNLOAD); 1333 break; 1334 } 1335 } 1336} 1337 1338static void 1339bge_sig_post_reset(struct bge_softc *sc, int type) 1340{ 1341 1342 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1343 switch (type) { 1344 case BGE_RESET_START: 1345 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1346 BGE_FW_DRV_STATE_START_DONE); 1347 /* START DONE */ 1348 break; 1349 case BGE_RESET_STOP: 1350 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1351 BGE_FW_DRV_STATE_UNLOAD_DONE); 1352 break; 1353 } 1354 } 1355} 1356 1357static void 1358bge_sig_legacy(struct bge_softc *sc, int type) 1359{ 1360 1361 if (sc->bge_asf_mode) { 1362 switch (type) { 1363 case BGE_RESET_START: 1364 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1365 BGE_FW_DRV_STATE_START); 1366 break; 1367 case BGE_RESET_STOP: 1368 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1369 BGE_FW_DRV_STATE_UNLOAD); 1370 break; 1371 } 1372 } 1373} 1374 1375static void 1376bge_stop_fw(struct bge_softc *sc) 1377{ 1378 int i; 1379 1380 if (sc->bge_asf_mode) { 1381 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1382 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 1383 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1384 1385 for (i = 0; i < 100; i++ ) { 1386 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1387 BGE_RX_CPU_DRV_EVENT)) 1388 break; 1389 DELAY(10); 1390 } 1391 } 1392} 1393 1394static uint32_t 1395bge_dma_swap_options(struct bge_softc *sc) 1396{ 1397 uint32_t dma_options; 1398 1399 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 1400 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 1401#if BYTE_ORDER == BIG_ENDIAN 1402 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 1403#endif 1404 if ((sc)->bge_asicrev == BGE_ASICREV_BCM5720) 1405 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1406 BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE | 1407 BGE_MODECTL_HTX2B_ENABLE; 1408 1409 return (dma_options); 1410} 1411 1412/* 1413 * Do endian, PCI and DMA initialization. 1414 */ 1415static int 1416bge_chipinit(struct bge_softc *sc) 1417{ 1418 uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1419 uint16_t val; 1420 int i; 1421 1422 /* Set endianness before we access any non-PCI registers. */ 1423 misc_ctl = BGE_INIT; 1424 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1425 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1426 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1427 1428 /* Clear the MAC control register */ 1429 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1430 1431 /* 1432 * Clear the MAC statistics block in the NIC's 1433 * internal memory. 1434 */ 1435 for (i = BGE_STATS_BLOCK; 1436 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1437 BGE_MEMWIN_WRITE(sc, i, 0); 1438 1439 for (i = BGE_STATUS_BLOCK; 1440 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1441 BGE_MEMWIN_WRITE(sc, i, 0); 1442 1443 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1444 /* 1445 * Fix data corruption caused by non-qword write with WB. 1446 * Fix master abort in PCI mode. 1447 * Fix PCI latency timer. 1448 */ 1449 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1450 val |= (1 << 10) | (1 << 12) | (1 << 13); 1451 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1452 } 1453 1454 /* 1455 * Set up the PCI DMA control register. 1456 */ 1457 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1458 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1459 if (sc->bge_flags & BGE_FLAG_PCIE) { 1460 /* Read watermark not used, 128 bytes for write. */ 1461 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1462 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1463 if (BGE_IS_5714_FAMILY(sc)) { 1464 /* 256 bytes for read and write. */ 1465 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1466 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1467 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1468 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1469 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1470 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1471 /* 1472 * In the BCM5703, the DMA read watermark should 1473 * be set to less than or equal to the maximum 1474 * memory read byte count of the PCI-X command 1475 * register. 1476 */ 1477 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1478 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1479 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1480 /* 1536 bytes for read, 384 bytes for write. */ 1481 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1482 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1483 } else { 1484 /* 384 bytes for read and write. */ 1485 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1486 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1487 0x0F; 1488 } 1489 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1490 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1491 uint32_t tmp; 1492 1493 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1494 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1495 if (tmp == 6 || tmp == 7) 1496 dma_rw_ctl |= 1497 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1498 1499 /* Set PCI-X DMA write workaround. */ 1500 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1501 } 1502 } else { 1503 /* Conventional PCI bus: 256 bytes for read and write. */ 1504 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1505 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1506 1507 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1508 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1509 dma_rw_ctl |= 0x0F; 1510 } 1511 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1512 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1513 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1514 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1515 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1516 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1517 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1518 if (BGE_IS_5717_PLUS(sc)) { 1519 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1520 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1521 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1522 /* 1523 * Enable HW workaround for controllers that misinterpret 1524 * a status tag update and leave interrupts permanently 1525 * disabled. 1526 */ 1527 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 1528 sc->bge_asicrev != BGE_ASICREV_BCM57765) 1529 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1530 } 1531 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1532 1533 /* 1534 * Set up general mode register. 1535 */ 1536 mode_ctl = bge_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR | 1537 BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM; 1538 1539 /* 1540 * BCM5701 B5 have a bug causing data corruption when using 1541 * 64-bit DMA reads, which can be terminated early and then 1542 * completed later as 32-bit accesses, in combination with 1543 * certain bridges. 1544 */ 1545 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1546 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1547 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1548 1549 /* 1550 * Tell the firmware the driver is running 1551 */ 1552 if (sc->bge_asf_mode & ASF_STACKUP) 1553 mode_ctl |= BGE_MODECTL_STACKUP; 1554 1555 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1556 1557 /* 1558 * Disable memory write invalidate. Apparently it is not supported 1559 * properly by these devices. Also ensure that INTx isn't disabled, 1560 * as these chips need it even when using MSI. 1561 */ 1562 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1563 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1564 1565 /* Set the timer prescaler (always 66Mhz) */ 1566 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1567 1568 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1569 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1570 DELAY(40); /* XXX */ 1571 1572 /* Put PHY into ready state */ 1573 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1574 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1575 DELAY(40); 1576 } 1577 1578 return (0); 1579} 1580 1581static int 1582bge_blockinit(struct bge_softc *sc) 1583{ 1584 struct bge_rcb *rcb; 1585 bus_size_t vrcb; 1586 bge_hostaddr taddr; 1587 uint32_t dmactl, val; 1588 int i, limit; 1589 1590 /* 1591 * Initialize the memory window pointer register so that 1592 * we can access the first 32K of internal NIC RAM. This will 1593 * allow us to set up the TX send ring RCBs and the RX return 1594 * ring RCBs, plus other things which live in NIC memory. 1595 */ 1596 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1597 1598 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1599 1600 if (!(BGE_IS_5705_PLUS(sc))) { 1601 /* Configure mbuf memory pool */ 1602 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1603 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1604 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1605 else 1606 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1607 1608 /* Configure DMA resource pool */ 1609 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1610 BGE_DMA_DESCRIPTORS); 1611 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1612 } 1613 1614 /* Configure mbuf pool watermarks */ 1615 if (BGE_IS_5717_PLUS(sc)) { 1616 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1617 if (sc->bge_ifp->if_mtu > ETHERMTU) { 1618 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 1619 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 1620 } else { 1621 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1622 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1623 } 1624 } else if (!BGE_IS_5705_PLUS(sc)) { 1625 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1626 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1627 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1628 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1629 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1630 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1631 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1632 } else { 1633 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1634 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1635 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1636 } 1637 1638 /* Configure DMA resource watermarks */ 1639 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1640 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1641 1642 /* Enable buffer manager */ 1643 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 1644 /* 1645 * Change the arbitration algorithm of TXMBUF read request to 1646 * round-robin instead of priority based for BCM5719. When 1647 * TXFIFO is almost empty, RDMA will hold its request until 1648 * TXFIFO is not almost empty. 1649 */ 1650 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 1651 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 1652 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 1653 1654 /* Poll for buffer manager start indication */ 1655 for (i = 0; i < BGE_TIMEOUT; i++) { 1656 DELAY(10); 1657 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1658 break; 1659 } 1660 1661 if (i == BGE_TIMEOUT) { 1662 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 1663 return (ENXIO); 1664 } 1665 1666 /* Enable flow-through queues */ 1667 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1668 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1669 1670 /* Wait until queue initialization is complete */ 1671 for (i = 0; i < BGE_TIMEOUT; i++) { 1672 DELAY(10); 1673 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1674 break; 1675 } 1676 1677 if (i == BGE_TIMEOUT) { 1678 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1679 return (ENXIO); 1680 } 1681 1682 /* 1683 * Summary of rings supported by the controller: 1684 * 1685 * Standard Receive Producer Ring 1686 * - This ring is used to feed receive buffers for "standard" 1687 * sized frames (typically 1536 bytes) to the controller. 1688 * 1689 * Jumbo Receive Producer Ring 1690 * - This ring is used to feed receive buffers for jumbo sized 1691 * frames (i.e. anything bigger than the "standard" frames) 1692 * to the controller. 1693 * 1694 * Mini Receive Producer Ring 1695 * - This ring is used to feed receive buffers for "mini" 1696 * sized frames to the controller. 1697 * - This feature required external memory for the controller 1698 * but was never used in a production system. Should always 1699 * be disabled. 1700 * 1701 * Receive Return Ring 1702 * - After the controller has placed an incoming frame into a 1703 * receive buffer that buffer is moved into a receive return 1704 * ring. The driver is then responsible to passing the 1705 * buffer up to the stack. Many versions of the controller 1706 * support multiple RR rings. 1707 * 1708 * Send Ring 1709 * - This ring is used for outgoing frames. Many versions of 1710 * the controller support multiple send rings. 1711 */ 1712 1713 /* Initialize the standard receive producer ring control block. */ 1714 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1715 rcb->bge_hostaddr.bge_addr_lo = 1716 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1717 rcb->bge_hostaddr.bge_addr_hi = 1718 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1719 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1720 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1721 if (BGE_IS_5717_PLUS(sc)) { 1722 /* 1723 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 1724 * Bits 15-2 : Maximum RX frame size 1725 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 1726 * Bit 0 : Reserved 1727 */ 1728 rcb->bge_maxlen_flags = 1729 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 1730 } else if (BGE_IS_5705_PLUS(sc)) { 1731 /* 1732 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 1733 * Bits 15-2 : Reserved (should be 0) 1734 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1735 * Bit 0 : Reserved 1736 */ 1737 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1738 } else { 1739 /* 1740 * Ring size is always XXX entries 1741 * Bits 31-16: Maximum RX frame size 1742 * Bits 15-2 : Reserved (should be 0) 1743 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1744 * Bit 0 : Reserved 1745 */ 1746 rcb->bge_maxlen_flags = 1747 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1748 } 1749 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 1750 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 1751 sc->bge_asicrev == BGE_ASICREV_BCM5720) 1752 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 1753 else 1754 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1755 /* Write the standard receive producer ring control block. */ 1756 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1757 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1758 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1759 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1760 1761 /* Reset the standard receive producer ring producer index. */ 1762 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1763 1764 /* 1765 * Initialize the jumbo RX producer ring control 1766 * block. We set the 'ring disabled' bit in the 1767 * flags field until we're actually ready to start 1768 * using this ring (i.e. once we set the MTU 1769 * high enough to require it). 1770 */ 1771 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1772 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1773 /* Get the jumbo receive producer ring RCB parameters. */ 1774 rcb->bge_hostaddr.bge_addr_lo = 1775 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1776 rcb->bge_hostaddr.bge_addr_hi = 1777 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1778 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1779 sc->bge_cdata.bge_rx_jumbo_ring_map, 1780 BUS_DMASYNC_PREREAD); 1781 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1782 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1783 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 1784 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 1785 sc->bge_asicrev == BGE_ASICREV_BCM5720) 1786 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 1787 else 1788 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1789 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1790 rcb->bge_hostaddr.bge_addr_hi); 1791 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1792 rcb->bge_hostaddr.bge_addr_lo); 1793 /* Program the jumbo receive producer ring RCB parameters. */ 1794 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1795 rcb->bge_maxlen_flags); 1796 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1797 /* Reset the jumbo receive producer ring producer index. */ 1798 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1799 } 1800 1801 /* Disable the mini receive producer ring RCB. */ 1802 if (BGE_IS_5700_FAMILY(sc)) { 1803 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1804 rcb->bge_maxlen_flags = 1805 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1806 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1807 rcb->bge_maxlen_flags); 1808 /* Reset the mini receive producer ring producer index. */ 1809 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1810 } 1811 1812 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 1813 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1814 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 1815 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 1816 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 1817 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 1818 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 1819 } 1820 /* 1821 * The BD ring replenish thresholds control how often the 1822 * hardware fetches new BD's from the producer rings in host 1823 * memory. Setting the value too low on a busy system can 1824 * starve the hardware and recue the throughpout. 1825 * 1826 * Set the BD ring replentish thresholds. The recommended 1827 * values are 1/8th the number of descriptors allocated to 1828 * each ring. 1829 * XXX The 5754 requires a lower threshold, so it might be a 1830 * requirement of all 575x family chips. The Linux driver sets 1831 * the lower threshold for all 5705 family chips as well, but there 1832 * are reports that it might not need to be so strict. 1833 * 1834 * XXX Linux does some extra fiddling here for the 5906 parts as 1835 * well. 1836 */ 1837 if (BGE_IS_5705_PLUS(sc)) 1838 val = 8; 1839 else 1840 val = BGE_STD_RX_RING_CNT / 8; 1841 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1842 if (BGE_IS_JUMBO_CAPABLE(sc)) 1843 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 1844 BGE_JUMBO_RX_RING_CNT/8); 1845 if (BGE_IS_5717_PLUS(sc)) { 1846 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 1847 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 1848 } 1849 1850 /* 1851 * Disable all send rings by setting the 'ring disabled' bit 1852 * in the flags field of all the TX send ring control blocks, 1853 * located in NIC memory. 1854 */ 1855 if (!BGE_IS_5705_PLUS(sc)) 1856 /* 5700 to 5704 had 16 send rings. */ 1857 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 1858 else 1859 limit = 1; 1860 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1861 for (i = 0; i < limit; i++) { 1862 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1863 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1864 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1865 vrcb += sizeof(struct bge_rcb); 1866 } 1867 1868 /* Configure send ring RCB 0 (we use only the first ring) */ 1869 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1870 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1871 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1872 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1873 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 1874 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 1875 sc->bge_asicrev == BGE_ASICREV_BCM5720) 1876 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 1877 else 1878 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1879 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1880 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1881 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1882 1883 /* 1884 * Disable all receive return rings by setting the 1885 * 'ring diabled' bit in the flags field of all the receive 1886 * return ring control blocks, located in NIC memory. 1887 */ 1888 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 1889 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 1890 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 1891 /* Should be 17, use 16 until we get an SRAM map. */ 1892 limit = 16; 1893 } else if (!BGE_IS_5705_PLUS(sc)) 1894 limit = BGE_RX_RINGS_MAX; 1895 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 1896 sc->bge_asicrev == BGE_ASICREV_BCM57765) 1897 limit = 4; 1898 else 1899 limit = 1; 1900 /* Disable all receive return rings. */ 1901 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1902 for (i = 0; i < limit; i++) { 1903 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1904 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1905 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1906 BGE_RCB_FLAG_RING_DISABLED); 1907 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1908 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1909 (i * (sizeof(uint64_t))), 0); 1910 vrcb += sizeof(struct bge_rcb); 1911 } 1912 1913 /* 1914 * Set up receive return ring 0. Note that the NIC address 1915 * for RX return rings is 0x0. The return rings live entirely 1916 * within the host, so the nicaddr field in the RCB isn't used. 1917 */ 1918 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1919 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1920 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1921 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1922 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1923 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1924 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1925 1926 /* Set random backoff seed for TX */ 1927 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1928 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1929 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1930 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1931 BGE_TX_BACKOFF_SEED_MASK); 1932 1933 /* Set inter-packet gap */ 1934 val = 0x2620; 1935 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 1936 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 1937 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 1938 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 1939 1940 /* 1941 * Specify which ring to use for packets that don't match 1942 * any RX rules. 1943 */ 1944 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1945 1946 /* 1947 * Configure number of RX lists. One interrupt distribution 1948 * list, sixteen active lists, one bad frames class. 1949 */ 1950 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1951 1952 /* Inialize RX list placement stats mask. */ 1953 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1954 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1955 1956 /* Disable host coalescing until we get it set up */ 1957 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1958 1959 /* Poll to make sure it's shut down. */ 1960 for (i = 0; i < BGE_TIMEOUT; i++) { 1961 DELAY(10); 1962 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1963 break; 1964 } 1965 1966 if (i == BGE_TIMEOUT) { 1967 device_printf(sc->bge_dev, 1968 "host coalescing engine failed to idle\n"); 1969 return (ENXIO); 1970 } 1971 1972 /* Set up host coalescing defaults */ 1973 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1974 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1975 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1976 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1977 if (!(BGE_IS_5705_PLUS(sc))) { 1978 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1979 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1980 } 1981 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1982 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1983 1984 /* Set up address of statistics block */ 1985 if (!(BGE_IS_5705_PLUS(sc))) { 1986 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1987 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1988 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1989 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1990 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1991 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1992 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1993 } 1994 1995 /* Set up address of status block */ 1996 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1997 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1998 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1999 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 2000 2001 /* Set up status block size. */ 2002 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2003 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2004 val = BGE_STATBLKSZ_FULL; 2005 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2006 } else { 2007 val = BGE_STATBLKSZ_32BYTE; 2008 bzero(sc->bge_ldata.bge_status_block, 32); 2009 } 2010 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2011 sc->bge_cdata.bge_status_map, 2012 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2013 2014 /* Turn on host coalescing state machine */ 2015 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2016 2017 /* Turn on RX BD completion state machine and enable attentions */ 2018 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2019 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2020 2021 /* Turn on RX list placement state machine */ 2022 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2023 2024 /* Turn on RX list selector state machine. */ 2025 if (!(BGE_IS_5705_PLUS(sc))) 2026 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2027 2028 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2029 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2030 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2031 BGE_MACMODE_FRMHDR_DMA_ENB; 2032 2033 if (sc->bge_flags & BGE_FLAG_TBI) 2034 val |= BGE_PORTMODE_TBI; 2035 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2036 val |= BGE_PORTMODE_GMII; 2037 else 2038 val |= BGE_PORTMODE_MII; 2039 2040 /* Turn on DMA, clear stats */ 2041 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2042 2043 /* Set misc. local control, enable interrupts on attentions */ 2044 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2045 2046#ifdef notdef 2047 /* Assert GPIO pins for PHY reset */ 2048 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 2049 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 2050 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 2051 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 2052#endif 2053 2054 /* Turn on DMA completion state machine */ 2055 if (!(BGE_IS_5705_PLUS(sc))) 2056 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2057 2058 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2059 2060 /* Enable host coalescing bug fix. */ 2061 if (BGE_IS_5755_PLUS(sc)) 2062 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2063 2064 /* Request larger DMA burst size to get better performance. */ 2065 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2066 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2067 2068 /* Turn on write DMA state machine */ 2069 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2070 DELAY(40); 2071 2072 /* Turn on read DMA state machine */ 2073 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2074 2075 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2076 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2077 2078 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2079 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2080 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2081 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2082 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2083 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2084 if (sc->bge_flags & BGE_FLAG_PCIE) 2085 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2086 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2087 val |= BGE_RDMAMODE_TSO4_ENABLE; 2088 if (sc->bge_flags & BGE_FLAG_TSO3 || 2089 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2090 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2091 val |= BGE_RDMAMODE_TSO6_ENABLE; 2092 } 2093 2094 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2095 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2096 BGE_RDMAMODE_H2BNC_VLAN_DET; 2097 /* 2098 * Allow multiple outstanding read requests from 2099 * non-LSO read DMA engine. 2100 */ 2101 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2102 } 2103 2104 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2105 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2106 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2107 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2108 BGE_IS_5717_PLUS(sc)) { 2109 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2110 /* 2111 * Adjust tx margin to prevent TX data corruption and 2112 * fix internal FIFO overflow. 2113 */ 2114 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2115 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2116 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2117 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2118 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2119 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2120 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2121 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2122 } 2123 /* 2124 * Enable fix for read DMA FIFO overruns. 2125 * The fix is to limit the number of RX BDs 2126 * the hardware would fetch at a fime. 2127 */ 2128 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 2129 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2130 } 2131 2132 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) { 2133 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2134 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2135 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2136 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2137 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2138 /* 2139 * Allow 4KB burst length reads for non-LSO frames. 2140 * Enable 512B burst length reads for buffer descriptors. 2141 */ 2142 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2143 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2144 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2145 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2146 } 2147 2148 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2149 DELAY(40); 2150 2151 /* Turn on RX data completion state machine */ 2152 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2153 2154 /* Turn on RX BD initiator state machine */ 2155 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2156 2157 /* Turn on RX data and RX BD initiator state machine */ 2158 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2159 2160 /* Turn on Mbuf cluster free state machine */ 2161 if (!(BGE_IS_5705_PLUS(sc))) 2162 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2163 2164 /* Turn on send BD completion state machine */ 2165 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2166 2167 /* Turn on send data completion state machine */ 2168 val = BGE_SDCMODE_ENABLE; 2169 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2170 val |= BGE_SDCMODE_CDELAY; 2171 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2172 2173 /* Turn on send data initiator state machine */ 2174 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2175 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2176 BGE_SDIMODE_HW_LSO_PRE_DMA); 2177 else 2178 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2179 2180 /* Turn on send BD initiator state machine */ 2181 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2182 2183 /* Turn on send BD selector state machine */ 2184 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2185 2186 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2187 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2188 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2189 2190 /* ack/clear link change events */ 2191 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2192 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2193 BGE_MACSTAT_LINK_CHANGED); 2194 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2195 2196 /* 2197 * Enable attention when the link has changed state for 2198 * devices that use auto polling. 2199 */ 2200 if (sc->bge_flags & BGE_FLAG_TBI) { 2201 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2202 } else { 2203 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2204 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2205 DELAY(80); 2206 } 2207 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2208 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2209 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2210 BGE_EVTENB_MI_INTERRUPT); 2211 } 2212 2213 /* 2214 * Clear any pending link state attention. 2215 * Otherwise some link state change events may be lost until attention 2216 * is cleared by bge_intr() -> bge_link_upd() sequence. 2217 * It's not necessary on newer BCM chips - perhaps enabling link 2218 * state change attentions implies clearing pending attention. 2219 */ 2220 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2221 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2222 BGE_MACSTAT_LINK_CHANGED); 2223 2224 /* Enable link state change attentions. */ 2225 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2226 2227 return (0); 2228} 2229 2230const struct bge_revision * 2231bge_lookup_rev(uint32_t chipid) 2232{ 2233 const struct bge_revision *br; 2234 2235 for (br = bge_revisions; br->br_name != NULL; br++) { 2236 if (br->br_chipid == chipid) 2237 return (br); 2238 } 2239 2240 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2241 if (br->br_chipid == BGE_ASICREV(chipid)) 2242 return (br); 2243 } 2244 2245 return (NULL); 2246} 2247 2248const struct bge_vendor * 2249bge_lookup_vendor(uint16_t vid) 2250{ 2251 const struct bge_vendor *v; 2252 2253 for (v = bge_vendors; v->v_name != NULL; v++) 2254 if (v->v_id == vid) 2255 return (v); 2256 2257 panic("%s: unknown vendor %d", __func__, vid); 2258 return (NULL); 2259} 2260 2261/* 2262 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2263 * against our list and return its name if we find a match. 2264 * 2265 * Note that since the Broadcom controller contains VPD support, we 2266 * try to get the device name string from the controller itself instead 2267 * of the compiled-in string. It guarantees we'll always announce the 2268 * right product name. We fall back to the compiled-in string when 2269 * VPD is unavailable or corrupt. 2270 */ 2271static int 2272bge_probe(device_t dev) 2273{ 2274 char buf[96]; 2275 char model[64]; 2276 const struct bge_revision *br; 2277 const char *pname; 2278 struct bge_softc *sc = device_get_softc(dev); 2279 const struct bge_type *t = bge_devs; 2280 const struct bge_vendor *v; 2281 uint32_t id; 2282 uint16_t did, vid; 2283 2284 sc->bge_dev = dev; 2285 vid = pci_get_vendor(dev); 2286 did = pci_get_device(dev); 2287 while(t->bge_vid != 0) { 2288 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2289 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2290 BGE_PCIMISCCTL_ASICREV_SHIFT; 2291 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2292 /* 2293 * Find the ASCI revision. Different chips 2294 * use different registers. 2295 */ 2296 switch (pci_get_device(dev)) { 2297 case BCOM_DEVICEID_BCM5717: 2298 case BCOM_DEVICEID_BCM5718: 2299 case BCOM_DEVICEID_BCM5719: 2300 case BCOM_DEVICEID_BCM5720: 2301 id = pci_read_config(dev, 2302 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2303 break; 2304 case BCOM_DEVICEID_BCM57761: 2305 case BCOM_DEVICEID_BCM57765: 2306 case BCOM_DEVICEID_BCM57781: 2307 case BCOM_DEVICEID_BCM57785: 2308 case BCOM_DEVICEID_BCM57791: 2309 case BCOM_DEVICEID_BCM57795: 2310 id = pci_read_config(dev, 2311 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2312 break; 2313 default: 2314 id = pci_read_config(dev, 2315 BGE_PCI_PRODID_ASICREV, 4); 2316 } 2317 } 2318 br = bge_lookup_rev(id); 2319 v = bge_lookup_vendor(vid); 2320 if (bge_has_eaddr(sc) && 2321 pci_get_vpd_ident(dev, &pname) == 0) 2322 snprintf(model, 64, "%s", pname); 2323 else 2324 snprintf(model, 64, "%s %s", v->v_name, 2325 br != NULL ? br->br_name : 2326 "NetXtreme Ethernet Controller"); 2327 snprintf(buf, 96, "%s, %sASIC rev. %#08x", model, 2328 br != NULL ? "" : "unknown ", id); 2329 device_set_desc_copy(dev, buf); 2330 return (0); 2331 } 2332 t++; 2333 } 2334 2335 return (ENXIO); 2336} 2337 2338static void 2339bge_dma_free(struct bge_softc *sc) 2340{ 2341 int i; 2342 2343 /* Destroy DMA maps for RX buffers. */ 2344 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2345 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2346 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2347 sc->bge_cdata.bge_rx_std_dmamap[i]); 2348 } 2349 if (sc->bge_cdata.bge_rx_std_sparemap) 2350 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2351 sc->bge_cdata.bge_rx_std_sparemap); 2352 2353 /* Destroy DMA maps for jumbo RX buffers. */ 2354 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2355 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2356 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2357 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2358 } 2359 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2360 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2361 sc->bge_cdata.bge_rx_jumbo_sparemap); 2362 2363 /* Destroy DMA maps for TX buffers. */ 2364 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2365 if (sc->bge_cdata.bge_tx_dmamap[i]) 2366 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2367 sc->bge_cdata.bge_tx_dmamap[i]); 2368 } 2369 2370 if (sc->bge_cdata.bge_rx_mtag) 2371 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2372 if (sc->bge_cdata.bge_mtag_jumbo) 2373 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo); 2374 if (sc->bge_cdata.bge_tx_mtag) 2375 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2376 2377 /* Destroy standard RX ring. */ 2378 if (sc->bge_cdata.bge_rx_std_ring_map) 2379 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2380 sc->bge_cdata.bge_rx_std_ring_map); 2381 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2382 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2383 sc->bge_ldata.bge_rx_std_ring, 2384 sc->bge_cdata.bge_rx_std_ring_map); 2385 2386 if (sc->bge_cdata.bge_rx_std_ring_tag) 2387 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2388 2389 /* Destroy jumbo RX ring. */ 2390 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2391 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2392 sc->bge_cdata.bge_rx_jumbo_ring_map); 2393 2394 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2395 sc->bge_ldata.bge_rx_jumbo_ring) 2396 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2397 sc->bge_ldata.bge_rx_jumbo_ring, 2398 sc->bge_cdata.bge_rx_jumbo_ring_map); 2399 2400 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2401 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2402 2403 /* Destroy RX return ring. */ 2404 if (sc->bge_cdata.bge_rx_return_ring_map) 2405 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2406 sc->bge_cdata.bge_rx_return_ring_map); 2407 2408 if (sc->bge_cdata.bge_rx_return_ring_map && 2409 sc->bge_ldata.bge_rx_return_ring) 2410 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2411 sc->bge_ldata.bge_rx_return_ring, 2412 sc->bge_cdata.bge_rx_return_ring_map); 2413 2414 if (sc->bge_cdata.bge_rx_return_ring_tag) 2415 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2416 2417 /* Destroy TX ring. */ 2418 if (sc->bge_cdata.bge_tx_ring_map) 2419 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2420 sc->bge_cdata.bge_tx_ring_map); 2421 2422 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2423 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2424 sc->bge_ldata.bge_tx_ring, 2425 sc->bge_cdata.bge_tx_ring_map); 2426 2427 if (sc->bge_cdata.bge_tx_ring_tag) 2428 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2429 2430 /* Destroy status block. */ 2431 if (sc->bge_cdata.bge_status_map) 2432 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2433 sc->bge_cdata.bge_status_map); 2434 2435 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2436 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2437 sc->bge_ldata.bge_status_block, 2438 sc->bge_cdata.bge_status_map); 2439 2440 if (sc->bge_cdata.bge_status_tag) 2441 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2442 2443 /* Destroy statistics block. */ 2444 if (sc->bge_cdata.bge_stats_map) 2445 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2446 sc->bge_cdata.bge_stats_map); 2447 2448 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2449 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2450 sc->bge_ldata.bge_stats, 2451 sc->bge_cdata.bge_stats_map); 2452 2453 if (sc->bge_cdata.bge_stats_tag) 2454 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2455 2456 if (sc->bge_cdata.bge_buffer_tag) 2457 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2458 2459 /* Destroy the parent tag. */ 2460 if (sc->bge_cdata.bge_parent_tag) 2461 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2462} 2463 2464static int 2465bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2466 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2467 bus_addr_t *paddr, const char *msg) 2468{ 2469 struct bge_dmamap_arg ctx; 2470 bus_addr_t lowaddr; 2471 bus_size_t ring_end; 2472 int error; 2473 2474 lowaddr = BUS_SPACE_MAXADDR; 2475again: 2476 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2477 alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2478 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2479 if (error != 0) { 2480 device_printf(sc->bge_dev, 2481 "could not create %s dma tag\n", msg); 2482 return (ENOMEM); 2483 } 2484 /* Allocate DMA'able memory for ring. */ 2485 error = bus_dmamem_alloc(*tag, (void **)ring, 2486 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2487 if (error != 0) { 2488 device_printf(sc->bge_dev, 2489 "could not allocate DMA'able memory for %s\n", msg); 2490 return (ENOMEM); 2491 } 2492 /* Load the address of the ring. */ 2493 ctx.bge_busaddr = 0; 2494 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2495 &ctx, BUS_DMA_NOWAIT); 2496 if (error != 0) { 2497 device_printf(sc->bge_dev, 2498 "could not load DMA'able memory for %s\n", msg); 2499 return (ENOMEM); 2500 } 2501 *paddr = ctx.bge_busaddr; 2502 ring_end = *paddr + maxsize; 2503 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 && 2504 BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) { 2505 /* 2506 * 4GB boundary crossed. Limit maximum allowable DMA 2507 * address space to 32bit and try again. 2508 */ 2509 bus_dmamap_unload(*tag, *map); 2510 bus_dmamem_free(*tag, *ring, *map); 2511 bus_dma_tag_destroy(*tag); 2512 if (bootverbose) 2513 device_printf(sc->bge_dev, "4GB boundary crossed, " 2514 "limit DMA address space to 32bit for %s\n", msg); 2515 *ring = NULL; 2516 *tag = NULL; 2517 *map = NULL; 2518 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2519 goto again; 2520 } 2521 return (0); 2522} 2523 2524static int 2525bge_dma_alloc(struct bge_softc *sc) 2526{ 2527 bus_addr_t lowaddr; 2528 bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz; 2529 int i, error; 2530 2531 lowaddr = BUS_SPACE_MAXADDR; 2532 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2533 lowaddr = BGE_DMA_MAXADDR; 2534 /* 2535 * Allocate the parent bus DMA tag appropriate for PCI. 2536 */ 2537 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2538 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2539 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2540 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2541 if (error != 0) { 2542 device_printf(sc->bge_dev, 2543 "could not allocate parent dma tag\n"); 2544 return (ENOMEM); 2545 } 2546 2547 /* Create tag for standard RX ring. */ 2548 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2549 &sc->bge_cdata.bge_rx_std_ring_tag, 2550 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2551 &sc->bge_cdata.bge_rx_std_ring_map, 2552 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2553 if (error) 2554 return (error); 2555 2556 /* Create tag for RX return ring. */ 2557 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2558 &sc->bge_cdata.bge_rx_return_ring_tag, 2559 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2560 &sc->bge_cdata.bge_rx_return_ring_map, 2561 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2562 if (error) 2563 return (error); 2564 2565 /* Create tag for TX ring. */ 2566 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2567 &sc->bge_cdata.bge_tx_ring_tag, 2568 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2569 &sc->bge_cdata.bge_tx_ring_map, 2570 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2571 if (error) 2572 return (error); 2573 2574 /* 2575 * Create tag for status block. 2576 * Because we only use single Tx/Rx/Rx return ring, use 2577 * minimum status block size except BCM5700 AX/BX which 2578 * seems to want to see full status block size regardless 2579 * of configured number of ring. 2580 */ 2581 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2582 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2583 sbsz = BGE_STATUS_BLK_SZ; 2584 else 2585 sbsz = 32; 2586 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 2587 &sc->bge_cdata.bge_status_tag, 2588 (uint8_t **)&sc->bge_ldata.bge_status_block, 2589 &sc->bge_cdata.bge_status_map, 2590 &sc->bge_ldata.bge_status_block_paddr, "status block"); 2591 if (error) 2592 return (error); 2593 2594 /* Create tag for statistics block. */ 2595 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 2596 &sc->bge_cdata.bge_stats_tag, 2597 (uint8_t **)&sc->bge_ldata.bge_stats, 2598 &sc->bge_cdata.bge_stats_map, 2599 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 2600 if (error) 2601 return (error); 2602 2603 /* Create tag for jumbo RX ring. */ 2604 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2605 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 2606 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 2607 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 2608 &sc->bge_cdata.bge_rx_jumbo_ring_map, 2609 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 2610 if (error) 2611 return (error); 2612 } 2613 2614 /* Create parent tag for buffers. */ 2615 boundary = 0; 2616 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 2617 boundary = BGE_DMA_BNDRY; 2618 /* 2619 * XXX 2620 * watchdog timeout issue was observed on BCM5704 which 2621 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 2622 * Both limiting DMA address space to 32bits and flushing 2623 * mailbox write seem to address the issue. 2624 */ 2625 if (sc->bge_pcixcap != 0) 2626 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2627 } 2628 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2629 1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL, 2630 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2631 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag); 2632 if (error != 0) { 2633 device_printf(sc->bge_dev, 2634 "could not allocate buffer dma tag\n"); 2635 return (ENOMEM); 2636 } 2637 /* Create tag for Tx mbufs. */ 2638 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2639 txsegsz = BGE_TSOSEG_SZ; 2640 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 2641 } else { 2642 txsegsz = MCLBYTES; 2643 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 2644 } 2645 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 2646 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 2647 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 2648 &sc->bge_cdata.bge_tx_mtag); 2649 2650 if (error) { 2651 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 2652 return (ENOMEM); 2653 } 2654 2655 /* Create tag for Rx mbufs. */ 2656 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 2657 rxmaxsegsz = MJUM9BYTES; 2658 else 2659 rxmaxsegsz = MCLBYTES; 2660 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 2661 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 2662 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 2663 2664 if (error) { 2665 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 2666 return (ENOMEM); 2667 } 2668 2669 /* Create DMA maps for RX buffers. */ 2670 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2671 &sc->bge_cdata.bge_rx_std_sparemap); 2672 if (error) { 2673 device_printf(sc->bge_dev, 2674 "can't create spare DMA map for RX\n"); 2675 return (ENOMEM); 2676 } 2677 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2678 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2679 &sc->bge_cdata.bge_rx_std_dmamap[i]); 2680 if (error) { 2681 device_printf(sc->bge_dev, 2682 "can't create DMA map for RX\n"); 2683 return (ENOMEM); 2684 } 2685 } 2686 2687 /* Create DMA maps for TX buffers. */ 2688 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2689 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 2690 &sc->bge_cdata.bge_tx_dmamap[i]); 2691 if (error) { 2692 device_printf(sc->bge_dev, 2693 "can't create DMA map for TX\n"); 2694 return (ENOMEM); 2695 } 2696 } 2697 2698 /* Create tags for jumbo RX buffers. */ 2699 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2700 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 2701 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2702 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 2703 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 2704 if (error) { 2705 device_printf(sc->bge_dev, 2706 "could not allocate jumbo dma tag\n"); 2707 return (ENOMEM); 2708 } 2709 /* Create DMA maps for jumbo RX buffers. */ 2710 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2711 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 2712 if (error) { 2713 device_printf(sc->bge_dev, 2714 "can't create spare DMA map for jumbo RX\n"); 2715 return (ENOMEM); 2716 } 2717 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2718 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2719 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2720 if (error) { 2721 device_printf(sc->bge_dev, 2722 "can't create DMA map for jumbo RX\n"); 2723 return (ENOMEM); 2724 } 2725 } 2726 } 2727 2728 return (0); 2729} 2730 2731/* 2732 * Return true if this device has more than one port. 2733 */ 2734static int 2735bge_has_multiple_ports(struct bge_softc *sc) 2736{ 2737 device_t dev = sc->bge_dev; 2738 u_int b, d, f, fscan, s; 2739 2740 d = pci_get_domain(dev); 2741 b = pci_get_bus(dev); 2742 s = pci_get_slot(dev); 2743 f = pci_get_function(dev); 2744 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2745 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 2746 return (1); 2747 return (0); 2748} 2749 2750/* 2751 * Return true if MSI can be used with this device. 2752 */ 2753static int 2754bge_can_use_msi(struct bge_softc *sc) 2755{ 2756 int can_use_msi = 0; 2757 2758#ifdef __HAIKU__ 2759 // temporary workaround, the int disable happens in msi enable through 2760 // setup intr in our case which undoes the re-enabling done by the driver 2761 return 0; 2762#endif 2763 2764 if (sc->bge_msi == 0) 2765 return (0); 2766 2767 /* Disable MSI for polling(4). */ 2768#ifdef DEVICE_POLLING 2769 return (0); 2770#endif 2771 switch (sc->bge_asicrev) { 2772 case BGE_ASICREV_BCM5714_A0: 2773 case BGE_ASICREV_BCM5714: 2774 /* 2775 * Apparently, MSI doesn't work when these chips are 2776 * configured in single-port mode. 2777 */ 2778 if (bge_has_multiple_ports(sc)) 2779 can_use_msi = 1; 2780 break; 2781 case BGE_ASICREV_BCM5750: 2782 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2783 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2784 can_use_msi = 1; 2785 break; 2786 default: 2787 if (BGE_IS_575X_PLUS(sc)) 2788 can_use_msi = 1; 2789 } 2790 return (can_use_msi); 2791} 2792 2793static int 2794bge_mbox_reorder(struct bge_softc *sc) 2795{ 2796#ifndef __HAIKU__ 2797 /* Lists of PCI bridges that are known to reorder mailbox writes. */ 2798 static const struct mbox_reorder { 2799 const uint16_t vendor; 2800 const uint16_t device; 2801 const char *desc; 2802 } const mbox_reorder_lists[] = { 2803 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, 2804 }; 2805 devclass_t pci, pcib; 2806 device_t bus, dev; 2807 int i; 2808 2809 pci = devclass_find("pci"); 2810 pcib = devclass_find("pcib"); 2811 dev = sc->bge_dev; 2812 bus = device_get_parent(dev); 2813 for (;;) { 2814 dev = device_get_parent(bus); 2815 bus = device_get_parent(dev); 2816 if (device_get_devclass(dev) != pcib) 2817 break; 2818 for (i = 0; i < nitems(mbox_reorder_lists); i++) { 2819 if (pci_get_vendor(dev) == 2820 mbox_reorder_lists[i].vendor && 2821 pci_get_device(dev) == 2822 mbox_reorder_lists[i].device) { 2823 device_printf(sc->bge_dev, 2824 "enabling MBOX workaround for %s\n", 2825 mbox_reorder_lists[i].desc); 2826 return (1); 2827 } 2828 } 2829 if (device_get_devclass(bus) != pci) 2830 break; 2831 } 2832#endif 2833 return (0); 2834} 2835 2836static void 2837bge_devinfo(struct bge_softc *sc) 2838{ 2839 uint32_t cfg, clk; 2840 2841 device_printf(sc->bge_dev, 2842 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ", 2843 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev); 2844 if (sc->bge_flags & BGE_FLAG_PCIE) 2845 printf("PCI-E\n"); 2846 else if (sc->bge_flags & BGE_FLAG_PCIX) { 2847 printf("PCI-X "); 2848 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 2849 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE) 2850 clk = 133; 2851 else { 2852 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 2853 switch (clk) { 2854 case 0: 2855 clk = 33; 2856 break; 2857 case 2: 2858 clk = 50; 2859 break; 2860 case 4: 2861 clk = 66; 2862 break; 2863 case 6: 2864 clk = 100; 2865 break; 2866 case 7: 2867 clk = 133; 2868 break; 2869 } 2870 } 2871 printf("%u MHz\n", clk); 2872 } else { 2873 if (sc->bge_pcixcap != 0) 2874 printf("PCI on PCI-X "); 2875 else 2876 printf("PCI "); 2877 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 2878 if (cfg & BGE_PCISTATE_PCI_BUSSPEED) 2879 clk = 66; 2880 else 2881 clk = 33; 2882 if (cfg & BGE_PCISTATE_32BIT_BUS) 2883 printf("%u MHz; 32bit\n", clk); 2884 else 2885 printf("%u MHz; 64bit\n", clk); 2886 } 2887} 2888 2889static int 2890bge_attach(device_t dev) 2891{ 2892 struct ifnet *ifp; 2893 struct bge_softc *sc; 2894 uint32_t hwcfg = 0, misccfg; 2895 u_char eaddr[ETHER_ADDR_LEN]; 2896 int capmask, error, f, msicount, phy_addr, reg, rid, trys; 2897 2898 sc = device_get_softc(dev); 2899 sc->bge_dev = dev; 2900 2901 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 2902 2903 /* 2904 * Map control/status registers. 2905 */ 2906 pci_enable_busmaster(dev); 2907 2908 rid = PCIR_BAR(0); 2909 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2910 RF_ACTIVE); 2911 2912 if (sc->bge_res == NULL) { 2913 device_printf (sc->bge_dev, "couldn't map memory\n"); 2914 error = ENXIO; 2915 goto fail; 2916 } 2917 2918 /* Save various chip information. */ 2919 sc->bge_chipid = 2920 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2921 BGE_PCIMISCCTL_ASICREV_SHIFT; 2922 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2923 /* 2924 * Find the ASCI revision. Different chips use different 2925 * registers. 2926 */ 2927 switch (pci_get_device(dev)) { 2928 case BCOM_DEVICEID_BCM5717: 2929 case BCOM_DEVICEID_BCM5718: 2930 case BCOM_DEVICEID_BCM5719: 2931 case BCOM_DEVICEID_BCM5720: 2932 sc->bge_chipid = pci_read_config(dev, 2933 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2934 break; 2935 case BCOM_DEVICEID_BCM57761: 2936 case BCOM_DEVICEID_BCM57765: 2937 case BCOM_DEVICEID_BCM57781: 2938 case BCOM_DEVICEID_BCM57785: 2939 case BCOM_DEVICEID_BCM57791: 2940 case BCOM_DEVICEID_BCM57795: 2941 sc->bge_chipid = pci_read_config(dev, 2942 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2943 break; 2944 default: 2945 sc->bge_chipid = pci_read_config(dev, 2946 BGE_PCI_PRODID_ASICREV, 4); 2947 } 2948 } 2949 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2950 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2951 2952 /* Set default PHY address. */ 2953 phy_addr = 1; 2954 /* 2955 * PHY address mapping for various devices. 2956 * 2957 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2958 * ---------+-------+-------+-------+-------+ 2959 * BCM57XX | 1 | X | X | X | 2960 * BCM5704 | 1 | X | 1 | X | 2961 * BCM5717 | 1 | 8 | 2 | 9 | 2962 * BCM5719 | 1 | 8 | 2 | 9 | 2963 * BCM5720 | 1 | 8 | 2 | 9 | 2964 * 2965 * Other addresses may respond but they are not 2966 * IEEE compliant PHYs and should be ignored. 2967 */ 2968 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2969 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2970 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2971 f = pci_get_function(dev); 2972 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2973 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 2974 BGE_SGDIGSTS_IS_SERDES) 2975 phy_addr = f + 8; 2976 else 2977 phy_addr = f + 1; 2978 } else { 2979 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2980 BGE_CPMU_PHY_STRAP_IS_SERDES) 2981 phy_addr = f + 8; 2982 else 2983 phy_addr = f + 1; 2984 } 2985 } 2986 2987 /* 2988 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2989 * 5705 A0 and A1 chips. 2990 */ 2991 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 2992 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2993 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2994 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2995 sc->bge_asicrev == BGE_ASICREV_BCM5906) 2996 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 2997 2998 if (bge_has_eaddr(sc)) 2999 sc->bge_flags |= BGE_FLAG_EADDR; 3000 3001 /* Save chipset family. */ 3002 switch (sc->bge_asicrev) { 3003 case BGE_ASICREV_BCM5717: 3004 case BGE_ASICREV_BCM5719: 3005 case BGE_ASICREV_BCM5720: 3006 case BGE_ASICREV_BCM57765: 3007 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 3008 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 3009 BGE_FLAG_JUMBO_FRAME; 3010 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3011 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3012 /* Jumbo frame on BCM5719 A0 does not work. */ 3013 sc->bge_flags &= ~BGE_FLAG_JUMBO; 3014 } 3015 break; 3016 case BGE_ASICREV_BCM5755: 3017 case BGE_ASICREV_BCM5761: 3018 case BGE_ASICREV_BCM5784: 3019 case BGE_ASICREV_BCM5785: 3020 case BGE_ASICREV_BCM5787: 3021 case BGE_ASICREV_BCM57780: 3022 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 3023 BGE_FLAG_5705_PLUS; 3024 break; 3025 case BGE_ASICREV_BCM5700: 3026 case BGE_ASICREV_BCM5701: 3027 case BGE_ASICREV_BCM5703: 3028 case BGE_ASICREV_BCM5704: 3029 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 3030 break; 3031 case BGE_ASICREV_BCM5714_A0: 3032 case BGE_ASICREV_BCM5780: 3033 case BGE_ASICREV_BCM5714: 3034 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 3035 /* FALLTHROUGH */ 3036 case BGE_ASICREV_BCM5750: 3037 case BGE_ASICREV_BCM5752: 3038 case BGE_ASICREV_BCM5906: 3039 sc->bge_flags |= BGE_FLAG_575X_PLUS; 3040 /* FALLTHROUGH */ 3041 case BGE_ASICREV_BCM5705: 3042 sc->bge_flags |= BGE_FLAG_5705_PLUS; 3043 break; 3044 } 3045 3046 /* Add SYSCTLs, requires the chipset family to be set. */ 3047 bge_add_sysctls(sc); 3048 3049 /* Set various PHY bug flags. */ 3050 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3051 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3052 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 3053 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 3054 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 3055 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 3056 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3057 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 3058 if (pci_get_subvendor(dev) == DELL_VENDORID) 3059 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 3060 if ((BGE_IS_5705_PLUS(sc)) && 3061 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 3062 sc->bge_asicrev != BGE_ASICREV_BCM5717 && 3063 sc->bge_asicrev != BGE_ASICREV_BCM5719 && 3064 sc->bge_asicrev != BGE_ASICREV_BCM5720 && 3065 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3066 sc->bge_asicrev != BGE_ASICREV_BCM57765 && 3067 sc->bge_asicrev != BGE_ASICREV_BCM57780) { 3068 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 3069 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3070 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3071 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 3072 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 3073 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 3074 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 3075 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 3076 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 3077 } else 3078 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 3079 } 3080 3081 /* Identify the chips that use an CPMU. */ 3082 if (BGE_IS_5717_PLUS(sc) || 3083 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3084 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3085 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 3086 sc->bge_asicrev == BGE_ASICREV_BCM57780) 3087 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 3088 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 3089 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 3090 else 3091 sc->bge_mi_mode = BGE_MIMODE_BASE; 3092 /* Enable auto polling for BCM570[0-5]. */ 3093 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 3094 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 3095 3096 /* 3097 * All Broadcom controllers have 4GB boundary DMA bug. 3098 * Whenever an address crosses a multiple of the 4GB boundary 3099 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 3100 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 3101 * state machine will lockup and cause the device to hang. 3102 */ 3103 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 3104 3105 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 3106 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3107 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 3108 3109 /* 3110 * BCM5719 cannot handle DMA requests for DMA segments that 3111 * have larger than 4KB in size. However the maximum DMA 3112 * segment size created in DMA tag is 4KB for TSO, so we 3113 * wouldn't encounter the issue here. 3114 */ 3115 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 3116 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 3117 3118 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3119 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 3120 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3121 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 3122 sc->bge_flags |= BGE_FLAG_5788; 3123 } 3124 3125 capmask = BMSR_DEFCAPMASK; 3126 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 3127 (misccfg == 0x4000 || misccfg == 0x8000)) || 3128 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3129 pci_get_vendor(dev) == BCOM_VENDORID && 3130 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 3131 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 3132 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 3133 (pci_get_vendor(dev) == BCOM_VENDORID && 3134 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3135 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3136 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3137 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3138 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3139 /* These chips are 10/100 only. */ 3140 capmask &= ~BMSR_EXTSTAT; 3141 } 3142 3143 /* 3144 * Some controllers seem to require a special firmware to use 3145 * TSO. But the firmware is not available to FreeBSD and Linux 3146 * claims that the TSO performed by the firmware is slower than 3147 * hardware based TSO. Moreover the firmware based TSO has one 3148 * known bug which can't handle TSO if ethernet header + IP/TCP 3149 * header is greater than 80 bytes. The workaround for the TSO 3150 * bug exist but it seems it's too expensive than not using 3151 * TSO at all. Some hardwares also have the TSO bug so limit 3152 * the TSO to the controllers that are not affected TSO issues 3153 * (e.g. 5755 or higher). 3154 */ 3155 if (BGE_IS_5717_PLUS(sc)) { 3156 /* BCM5717 requires different TSO configuration. */ 3157 sc->bge_flags |= BGE_FLAG_TSO3; 3158 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3159 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3160 /* TSO on BCM5719 A0 does not work. */ 3161 sc->bge_flags &= ~BGE_FLAG_TSO3; 3162 } 3163 } else if (BGE_IS_5755_PLUS(sc)) { 3164 /* 3165 * BCM5754 and BCM5787 shares the same ASIC id so 3166 * explicit device id check is required. 3167 * Due to unknown reason TSO does not work on BCM5755M. 3168 */ 3169 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3170 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3171 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3172 sc->bge_flags |= BGE_FLAG_TSO; 3173 } 3174 3175 /* 3176 * Check if this is a PCI-X or PCI Express device. 3177 */ 3178 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 3179 /* 3180 * Found a PCI Express capabilities register, this 3181 * must be a PCI Express device. 3182 */ 3183 sc->bge_flags |= BGE_FLAG_PCIE; 3184 sc->bge_expcap = reg; 3185 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3186 sc->bge_asicrev == BGE_ASICREV_BCM5720) 3187 pci_set_max_read_req(dev, 2048); 3188 else if (pci_get_max_read_req(dev) != 4096) 3189 pci_set_max_read_req(dev, 4096); 3190 } else { 3191 /* 3192 * Check if the device is in PCI-X Mode. 3193 * (This bit is not valid on PCI Express controllers.) 3194 */ 3195 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 3196 sc->bge_pcixcap = reg; 3197 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 3198 BGE_PCISTATE_PCI_BUSMODE) == 0) 3199 sc->bge_flags |= BGE_FLAG_PCIX; 3200 } 3201 3202 /* 3203 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3204 * not actually a MAC controller bug but an issue with the embedded 3205 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3206 */ 3207 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3208 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3209 /* 3210 * Some PCI-X bridges are known to trigger write reordering to 3211 * the mailbox registers. Typical phenomena is watchdog timeouts 3212 * caused by out-of-order TX completions. Enable workaround for 3213 * PCI-X devices that live behind these bridges. 3214 * Note, PCI-X controllers can run in PCI mode so we can't use 3215 * BGE_FLAG_PCIX flag to detect PCI-X controllers. 3216 */ 3217 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0) 3218 sc->bge_flags |= BGE_FLAG_MBOX_REORDER; 3219 /* 3220 * Allocate the interrupt, using MSI if possible. These devices 3221 * support 8 MSI messages, but only the first one is used in 3222 * normal operation. 3223 */ 3224 rid = 0; 3225 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 3226 sc->bge_msicap = reg; 3227 if (bge_can_use_msi(sc)) { 3228 msicount = pci_msi_count(dev); 3229 if (msicount > 1) 3230 msicount = 1; 3231 } else 3232 msicount = 0; 3233 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 3234 rid = 1; 3235 sc->bge_flags |= BGE_FLAG_MSI; 3236 } 3237 } 3238 3239 /* 3240 * All controllers except BCM5700 supports tagged status but 3241 * we use tagged status only for MSI case on BCM5717. Otherwise 3242 * MSI on BCM5717 does not work. 3243 */ 3244#ifndef DEVICE_POLLING 3245 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 3246 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 3247#endif 3248 3249 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3250 RF_SHAREABLE | RF_ACTIVE); 3251 3252 if (sc->bge_irq == NULL) { 3253 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3254 error = ENXIO; 3255 goto fail; 3256 } 3257 3258 bge_devinfo(sc); 3259 3260 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3261 3262 /* Try to reset the chip. */ 3263 if (bge_reset(sc)) { 3264 device_printf(sc->bge_dev, "chip reset failed\n"); 3265 error = ENXIO; 3266 goto fail; 3267 } 3268 3269 sc->bge_asf_mode = 0; 3270 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3271 BGE_SRAM_DATA_SIG_MAGIC)) { 3272 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) 3273 & BGE_HWCFG_ASF) { 3274 sc->bge_asf_mode |= ASF_ENABLE; 3275 sc->bge_asf_mode |= ASF_STACKUP; 3276 if (BGE_IS_575X_PLUS(sc)) 3277 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3278 } 3279 } 3280 3281 /* Try to reset the chip again the nice way. */ 3282 bge_stop_fw(sc); 3283 bge_sig_pre_reset(sc, BGE_RESET_STOP); 3284 if (bge_reset(sc)) { 3285 device_printf(sc->bge_dev, "chip reset failed\n"); 3286 error = ENXIO; 3287 goto fail; 3288 } 3289 3290 bge_sig_legacy(sc, BGE_RESET_STOP); 3291 bge_sig_post_reset(sc, BGE_RESET_STOP); 3292 3293 if (bge_chipinit(sc)) { 3294 device_printf(sc->bge_dev, "chip initialization failed\n"); 3295 error = ENXIO; 3296 goto fail; 3297 } 3298 3299 error = bge_get_eaddr(sc, eaddr); 3300 if (error) { 3301 device_printf(sc->bge_dev, 3302 "failed to read station address\n"); 3303 error = ENXIO; 3304 goto fail; 3305 } 3306 3307 /* 5705 limits RX return ring to 512 entries. */ 3308 if (BGE_IS_5717_PLUS(sc)) 3309 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3310 else if (BGE_IS_5705_PLUS(sc)) 3311 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3312 else 3313 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3314 3315 if (bge_dma_alloc(sc)) { 3316 device_printf(sc->bge_dev, 3317 "failed to allocate DMA resources\n"); 3318 error = ENXIO; 3319 goto fail; 3320 } 3321 3322 /* Set default tuneable values. */ 3323 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3324 sc->bge_rx_coal_ticks = 150; 3325 sc->bge_tx_coal_ticks = 150; 3326 sc->bge_rx_max_coal_bds = 10; 3327 sc->bge_tx_max_coal_bds = 10; 3328 3329 /* Initialize checksum features to use. */ 3330 sc->bge_csum_features = BGE_CSUM_FEATURES; 3331 if (sc->bge_forced_udpcsum != 0) 3332 sc->bge_csum_features |= CSUM_UDP; 3333 3334 /* Set up ifnet structure */ 3335 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3336 if (ifp == NULL) { 3337 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3338 error = ENXIO; 3339 goto fail; 3340 } 3341 ifp->if_softc = sc; 3342 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3343 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3344 ifp->if_ioctl = bge_ioctl; 3345 ifp->if_start = bge_start; 3346 ifp->if_init = bge_init; 3347 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 3348 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 3349 IFQ_SET_READY(&ifp->if_snd); 3350 ifp->if_hwassist = sc->bge_csum_features; 3351 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3352 IFCAP_VLAN_MTU; 3353 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3354 ifp->if_hwassist |= CSUM_TSO; 3355 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 3356 } 3357#ifdef IFCAP_VLAN_HWCSUM 3358 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 3359#endif 3360 ifp->if_capenable = ifp->if_capabilities; 3361#ifdef DEVICE_POLLING 3362 ifp->if_capabilities |= IFCAP_POLLING; 3363#endif 3364 3365 /* 3366 * 5700 B0 chips do not support checksumming correctly due 3367 * to hardware bugs. 3368 */ 3369 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3370 ifp->if_capabilities &= ~IFCAP_HWCSUM; 3371 ifp->if_capenable &= ~IFCAP_HWCSUM; 3372 ifp->if_hwassist = 0; 3373 } 3374 3375 /* 3376 * Figure out what sort of media we have by checking the 3377 * hardware config word in the first 32k of NIC internal memory, 3378 * or fall back to examining the EEPROM if necessary. 3379 * Note: on some BCM5700 cards, this value appears to be unset. 3380 * If that's the case, we have to rely on identifying the NIC 3381 * by its PCI subsystem ID, as we do below for the SysKonnect 3382 * SK-9D41. 3383 */ 3384 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3385 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3386 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3387 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3388 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3389 sizeof(hwcfg))) { 3390 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3391 error = ENXIO; 3392 goto fail; 3393 } 3394 hwcfg = ntohl(hwcfg); 3395 } 3396 3397 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3398 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3399 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3400 if (BGE_IS_5714_FAMILY(sc)) 3401 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3402 else 3403 sc->bge_flags |= BGE_FLAG_TBI; 3404 } 3405 3406 if (sc->bge_flags & BGE_FLAG_TBI) { 3407 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3408 bge_ifmedia_sts); 3409 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3410 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3411 0, NULL); 3412 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3413 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3414 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3415 } else { 3416 /* 3417 * Do transceiver setup and tell the firmware the 3418 * driver is down so we can try to get access the 3419 * probe if ASF is running. Retry a couple of times 3420 * if we get a conflict with the ASF firmware accessing 3421 * the PHY. 3422 */ 3423 trys = 0; 3424 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3425again: 3426 bge_asf_driver_up(sc); 3427 3428 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd, 3429 bge_ifmedia_sts, capmask, phy_addr, MII_OFFSET_ANY, 3430 MIIF_DOPAUSE); 3431 if (error != 0) { 3432 if (trys++ < 4) { 3433 device_printf(sc->bge_dev, "Try again\n"); 3434 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 3435 BMCR_RESET); 3436 goto again; 3437 } 3438 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3439 goto fail; 3440 } 3441 3442 /* 3443 * Now tell the firmware we are going up after probing the PHY 3444 */ 3445 if (sc->bge_asf_mode & ASF_STACKUP) 3446 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3447 } 3448 3449 /* 3450 * When using the BCM5701 in PCI-X mode, data corruption has 3451 * been observed in the first few bytes of some received packets. 3452 * Aligning the packet buffer in memory eliminates the corruption. 3453 * Unfortunately, this misaligns the packet payloads. On platforms 3454 * which do not support unaligned accesses, we will realign the 3455 * payloads by copying the received packets. 3456 */ 3457 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3458 sc->bge_flags & BGE_FLAG_PCIX) 3459 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3460 3461 /* 3462 * Call MI attach routine. 3463 */ 3464 ether_ifattach(ifp, eaddr); 3465 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3466 3467 /* Tell upper layer we support long frames. */ 3468 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 3469 3470 /* 3471 * Hookup IRQ last. 3472 */ 3473 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3474 /* Take advantage of single-shot MSI. */ 3475 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3476 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3477 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3478 taskqueue_thread_enqueue, &sc->bge_tq); 3479 if (sc->bge_tq == NULL) { 3480 device_printf(dev, "could not create taskqueue.\n"); 3481 ether_ifdetach(ifp); 3482 error = ENXIO; 3483 goto fail; 3484 } 3485 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq", 3486 device_get_nameunit(sc->bge_dev)); 3487 error = bus_setup_intr(dev, sc->bge_irq, 3488 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3489 &sc->bge_intrhand); 3490 if (error) 3491 ether_ifdetach(ifp); 3492 } else 3493 error = bus_setup_intr(dev, sc->bge_irq, 3494 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3495 &sc->bge_intrhand); 3496 3497 if (error) { 3498 bge_detach(dev); 3499 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3500 } 3501 3502 return (0); 3503 3504fail: 3505 bge_release_resources(sc); 3506 3507 return (error); 3508} 3509 3510static int 3511bge_detach(device_t dev) 3512{ 3513 struct bge_softc *sc; 3514 struct ifnet *ifp; 3515 3516 sc = device_get_softc(dev); 3517 ifp = sc->bge_ifp; 3518 3519#ifdef DEVICE_POLLING 3520 if (ifp->if_capenable & IFCAP_POLLING) 3521 ether_poll_deregister(ifp); 3522#endif 3523 3524 BGE_LOCK(sc); 3525 bge_stop(sc); 3526 bge_reset(sc); 3527 BGE_UNLOCK(sc); 3528 3529 callout_drain(&sc->bge_stat_ch); 3530 3531 if (sc->bge_tq) 3532 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3533 ether_ifdetach(ifp); 3534 3535 if (sc->bge_flags & BGE_FLAG_TBI) { 3536 ifmedia_removeall(&sc->bge_ifmedia); 3537 } else { 3538 bus_generic_detach(dev); 3539 device_delete_child(dev, sc->bge_miibus); 3540 } 3541 3542 bge_release_resources(sc); 3543 3544 return (0); 3545} 3546 3547static void 3548bge_release_resources(struct bge_softc *sc) 3549{ 3550 device_t dev; 3551 3552 dev = sc->bge_dev; 3553 3554 if (sc->bge_tq != NULL) 3555 taskqueue_free(sc->bge_tq); 3556 3557 if (sc->bge_intrhand != NULL) 3558 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3559 3560 if (sc->bge_irq != NULL) 3561 bus_release_resource(dev, SYS_RES_IRQ, 3562 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 3563 3564 if (sc->bge_flags & BGE_FLAG_MSI) 3565 pci_release_msi(dev); 3566 3567 if (sc->bge_res != NULL) 3568 bus_release_resource(dev, SYS_RES_MEMORY, 3569 PCIR_BAR(0), sc->bge_res); 3570 3571 if (sc->bge_ifp != NULL) 3572 if_free(sc->bge_ifp); 3573 3574 bge_dma_free(sc); 3575 3576 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 3577 BGE_LOCK_DESTROY(sc); 3578} 3579 3580static int 3581bge_reset(struct bge_softc *sc) 3582{ 3583 device_t dev; 3584 uint32_t cachesize, command, pcistate, reset, val; 3585 void (*write_op)(struct bge_softc *, int, int); 3586 uint16_t devctl; 3587 int i; 3588 3589 dev = sc->bge_dev; 3590 3591 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3592 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3593 if (sc->bge_flags & BGE_FLAG_PCIE) 3594 write_op = bge_writemem_direct; 3595 else 3596 write_op = bge_writemem_ind; 3597 } else 3598 write_op = bge_writereg_ind; 3599 3600 /* Save some important PCI state. */ 3601 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 3602 command = pci_read_config(dev, BGE_PCI_CMD, 4); 3603 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3604 3605 pci_write_config(dev, BGE_PCI_MISC_CTL, 3606 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3607 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3608 3609 /* Disable fastboot on controllers that support it. */ 3610 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 3611 BGE_IS_5755_PLUS(sc)) { 3612 if (bootverbose) 3613 device_printf(dev, "Disabling fastboot\n"); 3614 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 3615 } 3616 3617 /* 3618 * Write the magic number to SRAM at offset 0xB50. 3619 * When firmware finishes its initialization it will 3620 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 3621 */ 3622 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 3623 3624 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3625 3626 /* XXX: Broadcom Linux driver. */ 3627 if (sc->bge_flags & BGE_FLAG_PCIE) { 3628 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 3629 CSR_WRITE_4(sc, 0x7E2C, 0x20); 3630 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3631 /* Prevent PCIE link training during global reset */ 3632 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3633 reset |= 1 << 29; 3634 } 3635 } 3636 3637 /* 3638 * Set GPHY Power Down Override to leave GPHY 3639 * powered up in D0 uninitialized. 3640 */ 3641 if (BGE_IS_5705_PLUS(sc) && 3642 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 3643 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3644 3645 /* Issue global reset */ 3646 write_op(sc, BGE_MISC_CFG, reset); 3647 3648 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3649 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3650 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3651 val | BGE_VCPU_STATUS_DRV_RESET); 3652 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3653 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3654 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3655 } 3656 3657 DELAY(1000); 3658 3659 /* XXX: Broadcom Linux driver. */ 3660 if (sc->bge_flags & BGE_FLAG_PCIE) { 3661 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3662 DELAY(500000); /* wait for link training to complete */ 3663 val = pci_read_config(dev, 0xC4, 4); 3664 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 3665 } 3666 devctl = pci_read_config(dev, 3667 sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 3668 /* Clear enable no snoop and disable relaxed ordering. */ 3669 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE | 3670 PCIM_EXP_CTL_NOSNOOP_ENABLE); 3671 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 3672 devctl, 2); 3673 /* Clear error status. */ 3674 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA, 3675 PCIM_EXP_STA_CORRECTABLE_ERROR | 3676 PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR | 3677 PCIM_EXP_STA_UNSUPPORTED_REQ, 2); 3678 } 3679 3680 /* Reset some of the PCI state that got zapped by reset. */ 3681 pci_write_config(dev, BGE_PCI_MISC_CTL, 3682 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3683 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3684 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 3685 pci_write_config(dev, BGE_PCI_CMD, command, 4); 3686 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 3687 /* 3688 * Disable PCI-X relaxed ordering to ensure status block update 3689 * comes first then packet buffer DMA. Otherwise driver may 3690 * read stale status block. 3691 */ 3692 if (sc->bge_flags & BGE_FLAG_PCIX) { 3693 devctl = pci_read_config(dev, 3694 sc->bge_pcixcap + PCIXR_COMMAND, 2); 3695 devctl &= ~PCIXM_COMMAND_ERO; 3696 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 3697 devctl &= ~PCIXM_COMMAND_MAX_READ; 3698 devctl |= PCIXM_COMMAND_MAX_READ_2048; 3699 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3700 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 3701 PCIXM_COMMAND_MAX_READ); 3702 devctl |= PCIXM_COMMAND_MAX_READ_2048; 3703 } 3704 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 3705 devctl, 2); 3706 } 3707 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 3708 if (BGE_IS_5714_FAMILY(sc)) { 3709 /* This chip disables MSI on reset. */ 3710 if (sc->bge_flags & BGE_FLAG_MSI) { 3711 val = pci_read_config(dev, 3712 sc->bge_msicap + PCIR_MSI_CTRL, 2); 3713 pci_write_config(dev, 3714 sc->bge_msicap + PCIR_MSI_CTRL, 3715 val | PCIM_MSICTRL_MSI_ENABLE, 2); 3716 val = CSR_READ_4(sc, BGE_MSI_MODE); 3717 CSR_WRITE_4(sc, BGE_MSI_MODE, 3718 val | BGE_MSIMODE_ENABLE); 3719 } 3720 val = CSR_READ_4(sc, BGE_MARB_MODE); 3721 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3722 } else 3723 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3724 3725 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3726 for (i = 0; i < BGE_TIMEOUT; i++) { 3727 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3728 if (val & BGE_VCPU_STATUS_INIT_DONE) 3729 break; 3730 DELAY(100); 3731 } 3732 if (i == BGE_TIMEOUT) { 3733 device_printf(dev, "reset timed out\n"); 3734 return (1); 3735 } 3736 } else { 3737 /* 3738 * Poll until we see the 1's complement of the magic number. 3739 * This indicates that the firmware initialization is complete. 3740 * We expect this to fail if no chip containing the Ethernet 3741 * address is fitted though. 3742 */ 3743 for (i = 0; i < BGE_TIMEOUT; i++) { 3744 DELAY(10); 3745 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 3746 if (val == ~BGE_SRAM_FW_MB_MAGIC) 3747 break; 3748 } 3749 3750 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 3751 device_printf(dev, 3752 "firmware handshake timed out, found 0x%08x\n", 3753 val); 3754 /* BCM57765 A0 needs additional time before accessing. */ 3755 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 3756 DELAY(10 * 1000); /* XXX */ 3757 } 3758 3759 /* 3760 * XXX Wait for the value of the PCISTATE register to 3761 * return to its original pre-reset state. This is a 3762 * fairly good indicator of reset completion. If we don't 3763 * wait for the reset to fully complete, trying to read 3764 * from the device's non-PCI registers may yield garbage 3765 * results. 3766 */ 3767 for (i = 0; i < BGE_TIMEOUT; i++) { 3768 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 3769 break; 3770 DELAY(10); 3771 } 3772 3773 /* Fix up byte swapping. */ 3774 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 3775 3776 /* Tell the ASF firmware we are up */ 3777 if (sc->bge_asf_mode & ASF_STACKUP) 3778 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3779 3780 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3781 3782 /* 3783 * The 5704 in TBI mode apparently needs some special 3784 * adjustment to insure the SERDES drive level is set 3785 * to 1.2V. 3786 */ 3787 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 3788 sc->bge_flags & BGE_FLAG_TBI) { 3789 val = CSR_READ_4(sc, BGE_SERDES_CFG); 3790 val = (val & ~0xFFF) | 0x880; 3791 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 3792 } 3793 3794 /* XXX: Broadcom Linux driver. */ 3795 if (sc->bge_flags & BGE_FLAG_PCIE && 3796 !BGE_IS_5717_PLUS(sc) && 3797 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3798 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 3799 /* Enable Data FIFO protection. */ 3800 val = CSR_READ_4(sc, 0x7C00); 3801 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 3802 } 3803 DELAY(10000); 3804 3805 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 3806 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 3807 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 3808 3809 return (0); 3810} 3811 3812static __inline void 3813bge_rxreuse_std(struct bge_softc *sc, int i) 3814{ 3815 struct bge_rx_bd *r; 3816 3817 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 3818 r->bge_flags = BGE_RXBDFLAG_END; 3819 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 3820 r->bge_idx = i; 3821 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3822} 3823 3824static __inline void 3825bge_rxreuse_jumbo(struct bge_softc *sc, int i) 3826{ 3827 struct bge_extrx_bd *r; 3828 3829 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 3830 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 3831 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 3832 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 3833 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 3834 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 3835 r->bge_idx = i; 3836 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3837} 3838 3839/* 3840 * Frame reception handling. This is called if there's a frame 3841 * on the receive return list. 3842 * 3843 * Note: we have to be able to handle two possibilities here: 3844 * 1) the frame is from the jumbo receive ring 3845 * 2) the frame is from the standard receive ring 3846 */ 3847 3848static int 3849bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 3850{ 3851 struct ifnet *ifp; 3852 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 3853 uint16_t rx_cons; 3854 3855 rx_cons = sc->bge_rx_saved_considx; 3856 3857 /* Nothing to do. */ 3858 if (rx_cons == rx_prod) 3859 return (rx_npkts); 3860 3861 ifp = sc->bge_ifp; 3862 3863 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3864 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 3865 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3866 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 3867 if (BGE_IS_JUMBO_CAPABLE(sc) && 3868 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 3869 (MCLBYTES - ETHER_ALIGN)) 3870 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3871 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 3872 3873 while (rx_cons != rx_prod) { 3874 struct bge_rx_bd *cur_rx; 3875 uint32_t rxidx; 3876 struct mbuf *m = NULL; 3877 uint16_t vlan_tag = 0; 3878 int have_tag = 0; 3879 3880#ifdef DEVICE_POLLING 3881 if (ifp->if_capenable & IFCAP_POLLING) { 3882 if (sc->rxcycles <= 0) 3883 break; 3884 sc->rxcycles--; 3885 } 3886#endif 3887 3888 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 3889 3890 rxidx = cur_rx->bge_idx; 3891 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3892 3893 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 3894 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3895 have_tag = 1; 3896 vlan_tag = cur_rx->bge_vlan_tag; 3897 } 3898 3899 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3900 jumbocnt++; 3901 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3902 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3903 bge_rxreuse_jumbo(sc, rxidx); 3904 continue; 3905 } 3906 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 3907 bge_rxreuse_jumbo(sc, rxidx); 3908 ifp->if_iqdrops++; 3909 continue; 3910 } 3911 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3912 } else { 3913 stdcnt++; 3914 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3915 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3916 bge_rxreuse_std(sc, rxidx); 3917 continue; 3918 } 3919 if (bge_newbuf_std(sc, rxidx) != 0) { 3920 bge_rxreuse_std(sc, rxidx); 3921 ifp->if_iqdrops++; 3922 continue; 3923 } 3924 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3925 } 3926 3927 ifp->if_ipackets++; 3928#ifndef __NO_STRICT_ALIGNMENT 3929 /* 3930 * For architectures with strict alignment we must make sure 3931 * the payload is aligned. 3932 */ 3933 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3934 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3935 cur_rx->bge_len); 3936 m->m_data += ETHER_ALIGN; 3937 } 3938#endif 3939 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3940 m->m_pkthdr.rcvif = ifp; 3941 3942 if (ifp->if_capenable & IFCAP_RXCSUM) 3943 bge_rxcsum(sc, cur_rx, m); 3944 3945 /* 3946 * If we received a packet with a vlan tag, 3947 * attach that information to the packet. 3948 */ 3949 if (have_tag) { 3950 m->m_pkthdr.ether_vtag = vlan_tag; 3951 m->m_flags |= M_VLANTAG; 3952 } 3953 3954 if (holdlck != 0) { 3955 BGE_UNLOCK(sc); 3956 (*ifp->if_input)(ifp, m); 3957 BGE_LOCK(sc); 3958 } else 3959 (*ifp->if_input)(ifp, m); 3960 rx_npkts++; 3961 3962 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 3963 return (rx_npkts); 3964 } 3965 3966 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3967 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 3968 if (stdcnt > 0) 3969 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3970 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3971 3972 if (jumbocnt > 0) 3973 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3974 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3975 3976 sc->bge_rx_saved_considx = rx_cons; 3977 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3978 if (stdcnt) 3979 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 3980 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 3981 if (jumbocnt) 3982 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 3983 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 3984#ifdef notyet 3985 /* 3986 * This register wraps very quickly under heavy packet drops. 3987 * If you need correct statistics, you can enable this check. 3988 */ 3989 if (BGE_IS_5705_PLUS(sc)) 3990 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3991#endif 3992 return (rx_npkts); 3993} 3994 3995static void 3996bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 3997{ 3998 3999 if (BGE_IS_5717_PLUS(sc)) { 4000 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4001 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4002 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4003 if ((cur_rx->bge_error_flag & 4004 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 4005 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4006 } 4007 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4008 m->m_pkthdr.csum_data = 4009 cur_rx->bge_tcp_udp_csum; 4010 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4011 CSUM_PSEUDO_HDR; 4012 } 4013 } 4014 } else { 4015 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4016 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4017 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 4018 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4019 } 4020 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4021 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 4022 m->m_pkthdr.csum_data = 4023 cur_rx->bge_tcp_udp_csum; 4024 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4025 CSUM_PSEUDO_HDR; 4026 } 4027 } 4028} 4029 4030static void 4031bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 4032{ 4033 struct bge_tx_bd *cur_tx; 4034 struct ifnet *ifp; 4035 4036 BGE_LOCK_ASSERT(sc); 4037 4038 /* Nothing to do. */ 4039 if (sc->bge_tx_saved_considx == tx_cons) 4040 return; 4041 4042 ifp = sc->bge_ifp; 4043 4044 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4045 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 4046 /* 4047 * Go through our tx ring and free mbufs for those 4048 * frames that have been sent. 4049 */ 4050 while (sc->bge_tx_saved_considx != tx_cons) { 4051 uint32_t idx; 4052 4053 idx = sc->bge_tx_saved_considx; 4054 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 4055 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4056 ifp->if_opackets++; 4057 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 4058 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 4059 sc->bge_cdata.bge_tx_dmamap[idx], 4060 BUS_DMASYNC_POSTWRITE); 4061 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 4062 sc->bge_cdata.bge_tx_dmamap[idx]); 4063 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 4064 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4065 } 4066 sc->bge_txcnt--; 4067 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4068 } 4069 4070 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4071 if (sc->bge_txcnt == 0) 4072 sc->bge_timer = 0; 4073} 4074 4075#ifdef DEVICE_POLLING 4076static int 4077bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 4078{ 4079 struct bge_softc *sc = ifp->if_softc; 4080 uint16_t rx_prod, tx_cons; 4081 uint32_t statusword; 4082 int rx_npkts = 0; 4083 4084 BGE_LOCK(sc); 4085 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4086 BGE_UNLOCK(sc); 4087 return (rx_npkts); 4088 } 4089 4090 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4091 sc->bge_cdata.bge_status_map, 4092 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4093 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4094 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4095 4096 statusword = sc->bge_ldata.bge_status_block->bge_status; 4097 sc->bge_ldata.bge_status_block->bge_status = 0; 4098 4099 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4100 sc->bge_cdata.bge_status_map, 4101 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4102 4103 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 4104 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 4105 sc->bge_link_evt++; 4106 4107 if (cmd == POLL_AND_CHECK_STATUS) 4108 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4109 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4110 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 4111 bge_link_upd(sc); 4112 4113 sc->rxcycles = count; 4114 rx_npkts = bge_rxeof(sc, rx_prod, 1); 4115 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4116 BGE_UNLOCK(sc); 4117 return (rx_npkts); 4118 } 4119 bge_txeof(sc, tx_cons); 4120 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4121 bge_start_locked(ifp); 4122 4123 BGE_UNLOCK(sc); 4124 return (rx_npkts); 4125} 4126#endif /* DEVICE_POLLING */ 4127 4128static int 4129bge_msi_intr(void *arg) 4130{ 4131 struct bge_softc *sc; 4132 4133 sc = (struct bge_softc *)arg; 4134 /* 4135 * This interrupt is not shared and controller already 4136 * disabled further interrupt. 4137 */ 4138 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4139 return (FILTER_HANDLED); 4140} 4141 4142static void 4143bge_intr_task(void *arg, int pending) 4144{ 4145 struct bge_softc *sc; 4146 struct ifnet *ifp; 4147 uint32_t status, status_tag; 4148 uint16_t rx_prod, tx_cons; 4149 4150 sc = (struct bge_softc *)arg; 4151 ifp = sc->bge_ifp; 4152 4153 BGE_LOCK(sc); 4154 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 4155 BGE_UNLOCK(sc); 4156 return; 4157 } 4158 4159 /* Get updated status block. */ 4160 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4161 sc->bge_cdata.bge_status_map, 4162 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4163 4164 /* Save producer/consumer indexess. */ 4165 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4166 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4167 status = sc->bge_ldata.bge_status_block->bge_status; 4168 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 4169 sc->bge_ldata.bge_status_block->bge_status = 0; 4170 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4171 sc->bge_cdata.bge_status_map, 4172 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4173 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 4174 status_tag = 0; 4175 4176 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 4177 bge_link_upd(sc); 4178 4179 /* Let controller work. */ 4180 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4181 4182 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4183 sc->bge_rx_saved_considx != rx_prod) { 4184 /* Check RX return ring producer/consumer. */ 4185 BGE_UNLOCK(sc); 4186 bge_rxeof(sc, rx_prod, 0); 4187 BGE_LOCK(sc); 4188 } 4189 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4190 /* Check TX ring producer/consumer. */ 4191 bge_txeof(sc, tx_cons); 4192 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4193 bge_start_locked(ifp); 4194 } 4195 BGE_UNLOCK(sc); 4196} 4197 4198static void 4199bge_intr(void *xsc) 4200{ 4201 struct bge_softc *sc; 4202 struct ifnet *ifp; 4203 uint32_t statusword; 4204 uint16_t rx_prod, tx_cons; 4205 4206 sc = xsc; 4207 4208 BGE_LOCK(sc); 4209 4210 ifp = sc->bge_ifp; 4211 4212#ifdef DEVICE_POLLING 4213 if (ifp->if_capenable & IFCAP_POLLING) { 4214 BGE_UNLOCK(sc); 4215 return; 4216 } 4217#endif 4218 4219 /* 4220 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4221 * disable interrupts by writing nonzero like we used to, since with 4222 * our current organization this just gives complications and 4223 * pessimizations for re-enabling interrupts. We used to have races 4224 * instead of the necessary complications. Disabling interrupts 4225 * would just reduce the chance of a status update while we are 4226 * running (by switching to the interrupt-mode coalescence 4227 * parameters), but this chance is already very low so it is more 4228 * efficient to get another interrupt than prevent it. 4229 * 4230 * We do the ack first to ensure another interrupt if there is a 4231 * status update after the ack. We don't check for the status 4232 * changing later because it is more efficient to get another 4233 * interrupt than prevent it, not quite as above (not checking is 4234 * a smaller optimization than not toggling the interrupt enable, 4235 * since checking doesn't involve PCI accesses and toggling require 4236 * the status check). So toggling would probably be a pessimization 4237 * even with MSI. It would only be needed for using a task queue. 4238 */ 4239 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4240 4241 /* 4242 * Do the mandatory PCI flush as well as get the link status. 4243 */ 4244 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4245 4246 /* Make sure the descriptor ring indexes are coherent. */ 4247 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4248 sc->bge_cdata.bge_status_map, 4249 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4250 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4251 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4252 sc->bge_ldata.bge_status_block->bge_status = 0; 4253 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4254 sc->bge_cdata.bge_status_map, 4255 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4256 4257 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4258 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4259 statusword || sc->bge_link_evt) 4260 bge_link_upd(sc); 4261 4262 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4263 /* Check RX return ring producer/consumer. */ 4264 bge_rxeof(sc, rx_prod, 1); 4265 } 4266 4267 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4268 /* Check TX ring producer/consumer. */ 4269 bge_txeof(sc, tx_cons); 4270 } 4271 4272 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4273 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4274 bge_start_locked(ifp); 4275 4276 BGE_UNLOCK(sc); 4277} 4278 4279static void 4280bge_asf_driver_up(struct bge_softc *sc) 4281{ 4282 if (sc->bge_asf_mode & ASF_STACKUP) { 4283 /* Send ASF heartbeat aprox. every 2s */ 4284 if (sc->bge_asf_count) 4285 sc->bge_asf_count --; 4286 else { 4287 sc->bge_asf_count = 2; 4288 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4289 BGE_FW_CMD_DRV_ALIVE); 4290 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4291 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4292 BGE_FW_HB_TIMEOUT_SEC); 4293 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 4294 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4295 BGE_RX_CPU_DRV_EVENT); 4296 } 4297 } 4298} 4299 4300static void 4301bge_tick(void *xsc) 4302{ 4303 struct bge_softc *sc = xsc; 4304 struct mii_data *mii = NULL; 4305 4306 BGE_LOCK_ASSERT(sc); 4307 4308 /* Synchronize with possible callout reset/stop. */ 4309 if (callout_pending(&sc->bge_stat_ch) || 4310 !callout_active(&sc->bge_stat_ch)) 4311 return; 4312 4313 if (BGE_IS_5705_PLUS(sc)) 4314 bge_stats_update_regs(sc); 4315 else 4316 bge_stats_update(sc); 4317 4318 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4319 mii = device_get_softc(sc->bge_miibus); 4320 /* 4321 * Do not touch PHY if we have link up. This could break 4322 * IPMI/ASF mode or produce extra input errors 4323 * (extra errors was reported for bcm5701 & bcm5704). 4324 */ 4325 if (!sc->bge_link) 4326 mii_tick(mii); 4327 } else { 4328 /* 4329 * Since in TBI mode auto-polling can't be used we should poll 4330 * link status manually. Here we register pending link event 4331 * and trigger interrupt. 4332 */ 4333#ifdef DEVICE_POLLING 4334 /* In polling mode we poll link state in bge_poll(). */ 4335 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 4336#endif 4337 { 4338 sc->bge_link_evt++; 4339 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4340 sc->bge_flags & BGE_FLAG_5788) 4341 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4342 else 4343 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4344 } 4345 } 4346 4347 bge_asf_driver_up(sc); 4348 bge_watchdog(sc); 4349 4350 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4351} 4352 4353static void 4354bge_stats_update_regs(struct bge_softc *sc) 4355{ 4356 struct ifnet *ifp; 4357 struct bge_mac_stats *stats; 4358 4359 ifp = sc->bge_ifp; 4360 stats = &sc->bge_mac_stats; 4361 4362 stats->ifHCOutOctets += 4363 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4364 stats->etherStatsCollisions += 4365 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4366 stats->outXonSent += 4367 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4368 stats->outXoffSent += 4369 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4370 stats->dot3StatsInternalMacTransmitErrors += 4371 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4372 stats->dot3StatsSingleCollisionFrames += 4373 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4374 stats->dot3StatsMultipleCollisionFrames += 4375 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4376 stats->dot3StatsDeferredTransmissions += 4377 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4378 stats->dot3StatsExcessiveCollisions += 4379 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4380 stats->dot3StatsLateCollisions += 4381 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4382 stats->ifHCOutUcastPkts += 4383 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4384 stats->ifHCOutMulticastPkts += 4385 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4386 stats->ifHCOutBroadcastPkts += 4387 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4388 4389 stats->ifHCInOctets += 4390 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4391 stats->etherStatsFragments += 4392 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4393 stats->ifHCInUcastPkts += 4394 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4395 stats->ifHCInMulticastPkts += 4396 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4397 stats->ifHCInBroadcastPkts += 4398 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4399 stats->dot3StatsFCSErrors += 4400 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4401 stats->dot3StatsAlignmentErrors += 4402 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4403 stats->xonPauseFramesReceived += 4404 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4405 stats->xoffPauseFramesReceived += 4406 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4407 stats->macControlFramesReceived += 4408 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4409 stats->xoffStateEntered += 4410 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4411 stats->dot3StatsFramesTooLong += 4412 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4413 stats->etherStatsJabbers += 4414 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4415 stats->etherStatsUndersizePkts += 4416 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4417 4418 stats->FramesDroppedDueToFilters += 4419 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4420 stats->DmaWriteQueueFull += 4421 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4422 stats->DmaWriteHighPriQueueFull += 4423 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4424 stats->NoMoreRxBDs += 4425 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4426 /* 4427 * XXX 4428 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4429 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4430 * includes number of unwanted multicast frames. This comes 4431 * from silicon bug and known workaround to get rough(not 4432 * exact) counter is to enable interrupt on MBUF low water 4433 * attention. This can be accomplished by setting 4434 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4435 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4436 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4437 * However that change would generate more interrupts and 4438 * there are still possibilities of losing multiple frames 4439 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4440 * Given that the workaround still would not get correct 4441 * counter I don't think it's worth to implement it. So 4442 * ignore reading the counter on controllers that have the 4443 * silicon bug. 4444 */ 4445 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4446 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4447 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 4448 stats->InputDiscards += 4449 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4450 stats->InputErrors += 4451 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4452 stats->RecvThresholdHit += 4453 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4454 4455 ifp->if_collisions = (u_long)stats->etherStatsCollisions; 4456 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards + 4457 stats->InputErrors); 4458} 4459 4460static void 4461bge_stats_clear_regs(struct bge_softc *sc) 4462{ 4463 4464 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4465 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4466 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4467 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4468 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4469 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4470 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4471 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4472 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4473 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4474 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4475 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4476 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4477 4478 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4479 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4480 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4481 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4482 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4483 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4484 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4485 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4486 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4487 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4488 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4489 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4490 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4491 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4492 4493 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4494 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4495 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4496 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4497 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4498 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4499 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4500} 4501 4502static void 4503bge_stats_update(struct bge_softc *sc) 4504{ 4505 struct ifnet *ifp; 4506 bus_size_t stats; 4507 uint32_t cnt; /* current register value */ 4508 4509 ifp = sc->bge_ifp; 4510 4511 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4512 4513#define READ_STAT(sc, stats, stat) \ 4514 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4515 4516 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 4517 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 4518 sc->bge_tx_collisions = cnt; 4519 4520 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 4521 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds); 4522 sc->bge_rx_nobds = cnt; 4523 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 4524 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs); 4525 sc->bge_rx_inerrs = cnt; 4526 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 4527 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 4528 sc->bge_rx_discards = cnt; 4529 4530 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 4531 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 4532 sc->bge_tx_discards = cnt; 4533 4534#undef READ_STAT 4535} 4536 4537/* 4538 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4539 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4540 * but when such padded frames employ the bge IP/TCP checksum offload, 4541 * the hardware checksum assist gives incorrect results (possibly 4542 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4543 * If we pad such runts with zeros, the onboard checksum comes out correct. 4544 */ 4545static __inline int 4546bge_cksum_pad(struct mbuf *m) 4547{ 4548 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 4549 struct mbuf *last; 4550 4551 /* If there's only the packet-header and we can pad there, use it. */ 4552 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 4553 M_TRAILINGSPACE(m) >= padlen) { 4554 last = m; 4555 } else { 4556 /* 4557 * Walk packet chain to find last mbuf. We will either 4558 * pad there, or append a new mbuf and pad it. 4559 */ 4560 for (last = m; last->m_next != NULL; last = last->m_next); 4561 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 4562 /* Allocate new empty mbuf, pad it. Compact later. */ 4563 struct mbuf *n; 4564 4565 MGET(n, M_DONTWAIT, MT_DATA); 4566 if (n == NULL) 4567 return (ENOBUFS); 4568 n->m_len = 0; 4569 last->m_next = n; 4570 last = n; 4571 } 4572 } 4573 4574 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 4575 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 4576 last->m_len += padlen; 4577 m->m_pkthdr.len += padlen; 4578 4579 return (0); 4580} 4581 4582static struct mbuf * 4583bge_check_short_dma(struct mbuf *m) 4584{ 4585 struct mbuf *n; 4586 int found; 4587 4588 /* 4589 * If device receive two back-to-back send BDs with less than 4590 * or equal to 8 total bytes then the device may hang. The two 4591 * back-to-back send BDs must in the same frame for this failure 4592 * to occur. Scan mbuf chains and see whether two back-to-back 4593 * send BDs are there. If this is the case, allocate new mbuf 4594 * and copy the frame to workaround the silicon bug. 4595 */ 4596 for (n = m, found = 0; n != NULL; n = n->m_next) { 4597 if (n->m_len < 8) { 4598 found++; 4599 if (found > 1) 4600 break; 4601 continue; 4602 } 4603 found = 0; 4604 } 4605 4606 if (found > 1) { 4607 n = m_defrag(m, M_DONTWAIT); 4608 if (n == NULL) 4609 m_freem(m); 4610 } else 4611 n = m; 4612 return (n); 4613} 4614 4615static struct mbuf * 4616bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 4617 uint16_t *flags) 4618{ 4619 struct ip *ip; 4620 struct tcphdr *tcp; 4621 struct mbuf *n; 4622 uint16_t hlen; 4623 uint32_t poff; 4624 4625 if (M_WRITABLE(m) == 0) { 4626 /* Get a writable copy. */ 4627 n = m_dup(m, M_DONTWAIT); 4628 m_freem(m); 4629 if (n == NULL) 4630 return (NULL); 4631 m = n; 4632 } 4633 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 4634 if (m == NULL) 4635 return (NULL); 4636 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 4637 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 4638 m = m_pullup(m, poff + sizeof(struct tcphdr)); 4639 if (m == NULL) 4640 return (NULL); 4641 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 4642 m = m_pullup(m, poff + (tcp->th_off << 2)); 4643 if (m == NULL) 4644 return (NULL); 4645 /* 4646 * It seems controller doesn't modify IP length and TCP pseudo 4647 * checksum. These checksum computed by upper stack should be 0. 4648 */ 4649 *mss = m->m_pkthdr.tso_segsz; 4650 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 4651 ip->ip_sum = 0; 4652 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 4653 /* Clear pseudo checksum computed by TCP stack. */ 4654 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 4655 tcp->th_sum = 0; 4656 /* 4657 * Broadcom controllers uses different descriptor format for 4658 * TSO depending on ASIC revision. Due to TSO-capable firmware 4659 * license issue and lower performance of firmware based TSO 4660 * we only support hardware based TSO. 4661 */ 4662 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 4663 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 4664 if (sc->bge_flags & BGE_FLAG_TSO3) { 4665 /* 4666 * For BCM5717 and newer controllers, hardware based TSO 4667 * uses the 14 lower bits of the bge_mss field to store the 4668 * MSS and the upper 2 bits to store the lowest 2 bits of 4669 * the IP/TCP header length. The upper 6 bits of the header 4670 * length are stored in the bge_flags[14:10,4] field. Jumbo 4671 * frames are supported. 4672 */ 4673 *mss |= ((hlen & 0x3) << 14); 4674 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 4675 } else { 4676 /* 4677 * For BCM5755 and newer controllers, hardware based TSO uses 4678 * the lower 11 bits to store the MSS and the upper 5 bits to 4679 * store the IP/TCP header length. Jumbo frames are not 4680 * supported. 4681 */ 4682 *mss |= (hlen << 11); 4683 } 4684 return (m); 4685} 4686 4687/* 4688 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4689 * pointers to descriptors. 4690 */ 4691static int 4692bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 4693{ 4694 bus_dma_segment_t segs[BGE_NSEG_NEW]; 4695 bus_dmamap_t map; 4696 struct bge_tx_bd *d; 4697 struct mbuf *m = *m_head; 4698 uint32_t idx = *txidx; 4699 uint16_t csum_flags, mss, vlan_tag; 4700 int nsegs, i, error; 4701 4702 csum_flags = 0; 4703 mss = 0; 4704 vlan_tag = 0; 4705 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 4706 m->m_next != NULL) { 4707 *m_head = bge_check_short_dma(m); 4708 if (*m_head == NULL) 4709 return (ENOBUFS); 4710 m = *m_head; 4711 } 4712 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 4713 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 4714 if (*m_head == NULL) 4715 return (ENOBUFS); 4716 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 4717 BGE_TXBDFLAG_CPU_POST_DMA; 4718 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 4719 if (m->m_pkthdr.csum_flags & CSUM_IP) 4720 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4721 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 4722 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4723 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 4724 (error = bge_cksum_pad(m)) != 0) { 4725 m_freem(m); 4726 *m_head = NULL; 4727 return (error); 4728 } 4729 } 4730 if (m->m_flags & M_LASTFRAG) 4731 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 4732 else if (m->m_flags & M_FRAG) 4733 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 4734 } 4735 4736 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 4737 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 4738 m->m_pkthdr.len > ETHER_MAX_LEN) 4739 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 4740 if (sc->bge_forced_collapse > 0 && 4741 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 4742 /* 4743 * Forcedly collapse mbuf chains to overcome hardware 4744 * limitation which only support a single outstanding 4745 * DMA read operation. 4746 */ 4747 if (sc->bge_forced_collapse == 1) 4748 m = m_defrag(m, M_DONTWAIT); 4749 else 4750 m = m_collapse(m, M_DONTWAIT, 4751 sc->bge_forced_collapse); 4752 if (m == NULL) 4753 m = *m_head; 4754 *m_head = m; 4755 } 4756 } 4757 4758 map = sc->bge_cdata.bge_tx_dmamap[idx]; 4759 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 4760 &nsegs, BUS_DMA_NOWAIT); 4761 if (error == EFBIG) { 4762 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); 4763 if (m == NULL) { 4764 m_freem(*m_head); 4765 *m_head = NULL; 4766 return (ENOBUFS); 4767 } 4768 *m_head = m; 4769 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 4770 m, segs, &nsegs, BUS_DMA_NOWAIT); 4771 if (error) { 4772 m_freem(m); 4773 *m_head = NULL; 4774 return (error); 4775 } 4776 } else if (error != 0) 4777 return (error); 4778 4779 /* Check if we have enough free send BDs. */ 4780 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 4781 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 4782 return (ENOBUFS); 4783 } 4784 4785 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 4786 4787 if (m->m_flags & M_VLANTAG) { 4788 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 4789 vlan_tag = m->m_pkthdr.ether_vtag; 4790 } 4791 for (i = 0; ; i++) { 4792 d = &sc->bge_ldata.bge_tx_ring[idx]; 4793 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 4794 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 4795 d->bge_len = segs[i].ds_len; 4796 d->bge_flags = csum_flags; 4797 d->bge_vlan_tag = vlan_tag; 4798 d->bge_mss = mss; 4799 if (i == nsegs - 1) 4800 break; 4801 BGE_INC(idx, BGE_TX_RING_CNT); 4802 } 4803 4804 /* Mark the last segment as end of packet... */ 4805 d->bge_flags |= BGE_TXBDFLAG_END; 4806 4807 /* 4808 * Insure that the map for this transmission 4809 * is placed at the array index of the last descriptor 4810 * in this chain. 4811 */ 4812 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 4813 sc->bge_cdata.bge_tx_dmamap[idx] = map; 4814 sc->bge_cdata.bge_tx_chain[idx] = m; 4815 sc->bge_txcnt += nsegs; 4816 4817 BGE_INC(idx, BGE_TX_RING_CNT); 4818 *txidx = idx; 4819 4820 return (0); 4821} 4822 4823/* 4824 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4825 * to the mbuf data regions directly in the transmit descriptors. 4826 */ 4827static void 4828bge_start_locked(struct ifnet *ifp) 4829{ 4830 struct bge_softc *sc; 4831 struct mbuf *m_head; 4832 uint32_t prodidx; 4833 int count; 4834 4835 sc = ifp->if_softc; 4836 BGE_LOCK_ASSERT(sc); 4837 4838 if (!sc->bge_link || 4839 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4840 IFF_DRV_RUNNING) 4841 return; 4842 4843 prodidx = sc->bge_tx_prodidx; 4844 4845 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 4846 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 4847 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4848 break; 4849 } 4850 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 4851 if (m_head == NULL) 4852 break; 4853 4854 /* 4855 * XXX 4856 * The code inside the if() block is never reached since we 4857 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 4858 * requests to checksum TCP/UDP in a fragmented packet. 4859 * 4860 * XXX 4861 * safety overkill. If this is a fragmented packet chain 4862 * with delayed TCP/UDP checksums, then only encapsulate 4863 * it if we have enough descriptors to handle the entire 4864 * chain at once. 4865 * (paranoia -- may not actually be needed) 4866 */ 4867 if (m_head->m_flags & M_FIRSTFRAG && 4868 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4869 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4870 m_head->m_pkthdr.csum_data + 16) { 4871 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4872 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4873 break; 4874 } 4875 } 4876 4877 /* 4878 * Pack the data into the transmit ring. If we 4879 * don't have room, set the OACTIVE flag and wait 4880 * for the NIC to drain the ring. 4881 */ 4882 if (bge_encap(sc, &m_head, &prodidx)) { 4883 if (m_head == NULL) 4884 break; 4885 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4886 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4887 break; 4888 } 4889 ++count; 4890 4891 /* 4892 * If there's a BPF listener, bounce a copy of this frame 4893 * to him. 4894 */ 4895#ifdef ETHER_BPF_MTAP 4896 ETHER_BPF_MTAP(ifp, m_head); 4897#else 4898 BPF_MTAP(ifp, m_head); 4899#endif 4900 } 4901 4902 if (count > 0) { 4903 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4904 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 4905 /* Transmit. */ 4906 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4907 /* 5700 b2 errata */ 4908 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 4909 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4910 4911 sc->bge_tx_prodidx = prodidx; 4912 4913 /* 4914 * Set a timeout in case the chip goes out to lunch. 4915 */ 4916 sc->bge_timer = 5; 4917 } 4918} 4919 4920/* 4921 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4922 * to the mbuf data regions directly in the transmit descriptors. 4923 */ 4924static void 4925bge_start(struct ifnet *ifp) 4926{ 4927 struct bge_softc *sc; 4928 4929 sc = ifp->if_softc; 4930 BGE_LOCK(sc); 4931 bge_start_locked(ifp); 4932 BGE_UNLOCK(sc); 4933} 4934 4935static void 4936bge_init_locked(struct bge_softc *sc) 4937{ 4938 struct ifnet *ifp; 4939 uint16_t *m; 4940 uint32_t mode; 4941 4942 BGE_LOCK_ASSERT(sc); 4943 4944 ifp = sc->bge_ifp; 4945 4946 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4947 return; 4948 4949 /* Cancel pending I/O and flush buffers. */ 4950 bge_stop(sc); 4951 4952 bge_stop_fw(sc); 4953 bge_sig_pre_reset(sc, BGE_RESET_START); 4954 bge_reset(sc); 4955 bge_sig_legacy(sc, BGE_RESET_START); 4956 bge_sig_post_reset(sc, BGE_RESET_START); 4957 4958 bge_chipinit(sc); 4959 4960 /* 4961 * Init the various state machines, ring 4962 * control blocks and firmware. 4963 */ 4964 if (bge_blockinit(sc)) { 4965 device_printf(sc->bge_dev, "initialization failure\n"); 4966 return; 4967 } 4968 4969 ifp = sc->bge_ifp; 4970 4971 /* Specify MTU. */ 4972 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4973 ETHER_HDR_LEN + ETHER_CRC_LEN + 4974 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 4975 4976 /* Load our MAC address. */ 4977 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 4978 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4979 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4980 4981 /* Program promiscuous mode. */ 4982 bge_setpromisc(sc); 4983 4984 /* Program multicast filter. */ 4985 bge_setmulti(sc); 4986 4987 /* Program VLAN tag stripping. */ 4988 bge_setvlan(sc); 4989 4990 /* Override UDP checksum offloading. */ 4991 if (sc->bge_forced_udpcsum == 0) 4992 sc->bge_csum_features &= ~CSUM_UDP; 4993 else 4994 sc->bge_csum_features |= CSUM_UDP; 4995 if (ifp->if_capabilities & IFCAP_TXCSUM && 4996 ifp->if_capenable & IFCAP_TXCSUM) { 4997 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP); 4998 ifp->if_hwassist |= sc->bge_csum_features; 4999 } 5000 5001 /* Init RX ring. */ 5002 if (bge_init_rx_ring_std(sc) != 0) { 5003 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 5004 bge_stop(sc); 5005 return; 5006 } 5007 5008 /* 5009 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5010 * memory to insure that the chip has in fact read the first 5011 * entry of the ring. 5012 */ 5013 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5014 uint32_t v, i; 5015 for (i = 0; i < 10; i++) { 5016 DELAY(20); 5017 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5018 if (v == (MCLBYTES - ETHER_ALIGN)) 5019 break; 5020 } 5021 if (i == 10) 5022 device_printf (sc->bge_dev, 5023 "5705 A0 chip failed to load RX ring\n"); 5024 } 5025 5026 /* Init jumbo RX ring. */ 5027 if (BGE_IS_JUMBO_CAPABLE(sc) && 5028 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 5029 (MCLBYTES - ETHER_ALIGN)) { 5030 if (bge_init_rx_ring_jumbo(sc) != 0) { 5031 device_printf(sc->bge_dev, 5032 "no memory for jumbo Rx buffers.\n"); 5033 bge_stop(sc); 5034 return; 5035 } 5036 } 5037 5038 /* Init our RX return ring index. */ 5039 sc->bge_rx_saved_considx = 0; 5040 5041 /* Init our RX/TX stat counters. */ 5042 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 5043 5044 /* Init TX ring. */ 5045 bge_init_tx_ring(sc); 5046 5047 /* Enable TX MAC state machine lockup fix. */ 5048 mode = CSR_READ_4(sc, BGE_TX_MODE); 5049 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 5050 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5051 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 5052 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5053 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5054 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5055 } 5056 /* Turn on transmitter. */ 5057 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5058 5059 /* Turn on receiver. */ 5060 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5061 5062 /* 5063 * Set the number of good frames to receive after RX MBUF 5064 * Low Watermark has been reached. After the RX MAC receives 5065 * this number of frames, it will drop subsequent incoming 5066 * frames until the MBUF High Watermark is reached. 5067 */ 5068 if (sc->bge_asicrev == BGE_ASICREV_BCM57765) 5069 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 5070 else 5071 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5072 5073 /* Clear MAC statistics. */ 5074 if (BGE_IS_5705_PLUS(sc)) 5075 bge_stats_clear_regs(sc); 5076 5077 /* Tell firmware we're alive. */ 5078 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5079 5080#ifdef DEVICE_POLLING 5081 /* Disable interrupts if we are polling. */ 5082 if (ifp->if_capenable & IFCAP_POLLING) { 5083 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5084 BGE_PCIMISCCTL_MASK_PCI_INTR); 5085 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5086 } else 5087#endif 5088 5089 /* Enable host interrupts. */ 5090 { 5091 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5092 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5093 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5094 } 5095 5096 bge_ifmedia_upd_locked(ifp); 5097 5098 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5099 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5100 5101 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 5102} 5103 5104static void 5105bge_init(void *xsc) 5106{ 5107 struct bge_softc *sc = xsc; 5108 5109 BGE_LOCK(sc); 5110 bge_init_locked(sc); 5111 BGE_UNLOCK(sc); 5112} 5113 5114/* 5115 * Set media options. 5116 */ 5117static int 5118bge_ifmedia_upd(struct ifnet *ifp) 5119{ 5120 struct bge_softc *sc = ifp->if_softc; 5121 int res; 5122 5123 BGE_LOCK(sc); 5124 res = bge_ifmedia_upd_locked(ifp); 5125 BGE_UNLOCK(sc); 5126 5127 return (res); 5128} 5129 5130static int 5131bge_ifmedia_upd_locked(struct ifnet *ifp) 5132{ 5133 struct bge_softc *sc = ifp->if_softc; 5134 struct mii_data *mii; 5135 struct mii_softc *miisc; 5136 struct ifmedia *ifm; 5137 5138 BGE_LOCK_ASSERT(sc); 5139 5140 ifm = &sc->bge_ifmedia; 5141 5142 /* If this is a 1000baseX NIC, enable the TBI port. */ 5143 if (sc->bge_flags & BGE_FLAG_TBI) { 5144 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5145 return (EINVAL); 5146 switch(IFM_SUBTYPE(ifm->ifm_media)) { 5147 case IFM_AUTO: 5148 /* 5149 * The BCM5704 ASIC appears to have a special 5150 * mechanism for programming the autoneg 5151 * advertisement registers in TBI mode. 5152 */ 5153 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5154 uint32_t sgdig; 5155 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5156 if (sgdig & BGE_SGDIGSTS_DONE) { 5157 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5158 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5159 sgdig |= BGE_SGDIGCFG_AUTO | 5160 BGE_SGDIGCFG_PAUSE_CAP | 5161 BGE_SGDIGCFG_ASYM_PAUSE; 5162 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5163 sgdig | BGE_SGDIGCFG_SEND); 5164 DELAY(5); 5165 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5166 } 5167 } 5168 break; 5169 case IFM_1000_SX: 5170 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5171 BGE_CLRBIT(sc, BGE_MAC_MODE, 5172 BGE_MACMODE_HALF_DUPLEX); 5173 } else { 5174 BGE_SETBIT(sc, BGE_MAC_MODE, 5175 BGE_MACMODE_HALF_DUPLEX); 5176 } 5177 break; 5178 default: 5179 return (EINVAL); 5180 } 5181 return (0); 5182 } 5183 5184 sc->bge_link_evt++; 5185 mii = device_get_softc(sc->bge_miibus); 5186 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5187 PHY_RESET(miisc); 5188 mii_mediachg(mii); 5189 5190 /* 5191 * Force an interrupt so that we will call bge_link_upd 5192 * if needed and clear any pending link state attention. 5193 * Without this we are not getting any further interrupts 5194 * for link state changes and thus will not UP the link and 5195 * not be able to send in bge_start_locked. The only 5196 * way to get things working was to receive a packet and 5197 * get an RX intr. 5198 * bge_tick should help for fiber cards and we might not 5199 * need to do this here if BGE_FLAG_TBI is set but as 5200 * we poll for fiber anyway it should not harm. 5201 */ 5202 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 5203 sc->bge_flags & BGE_FLAG_5788) 5204 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5205 else 5206 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5207 5208 return (0); 5209} 5210 5211/* 5212 * Report current media status. 5213 */ 5214static void 5215bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5216{ 5217 struct bge_softc *sc = ifp->if_softc; 5218 struct mii_data *mii; 5219 5220 BGE_LOCK(sc); 5221 5222 if (sc->bge_flags & BGE_FLAG_TBI) { 5223 ifmr->ifm_status = IFM_AVALID; 5224 ifmr->ifm_active = IFM_ETHER; 5225 if (CSR_READ_4(sc, BGE_MAC_STS) & 5226 BGE_MACSTAT_TBI_PCS_SYNCHED) 5227 ifmr->ifm_status |= IFM_ACTIVE; 5228 else { 5229 ifmr->ifm_active |= IFM_NONE; 5230 BGE_UNLOCK(sc); 5231 return; 5232 } 5233 ifmr->ifm_active |= IFM_1000_SX; 5234 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5235 ifmr->ifm_active |= IFM_HDX; 5236 else 5237 ifmr->ifm_active |= IFM_FDX; 5238 BGE_UNLOCK(sc); 5239 return; 5240 } 5241 5242 mii = device_get_softc(sc->bge_miibus); 5243 mii_pollstat(mii); 5244 ifmr->ifm_active = mii->mii_media_active; 5245 ifmr->ifm_status = mii->mii_media_status; 5246 5247 BGE_UNLOCK(sc); 5248} 5249 5250static int 5251bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 5252{ 5253 struct bge_softc *sc = ifp->if_softc; 5254 struct ifreq *ifr = (struct ifreq *) data; 5255 struct mii_data *mii; 5256 int flags, mask, error = 0; 5257 5258 switch (command) { 5259 case SIOCSIFMTU: 5260 if (BGE_IS_JUMBO_CAPABLE(sc) || 5261 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 5262 if (ifr->ifr_mtu < ETHERMIN || 5263 ifr->ifr_mtu > BGE_JUMBO_MTU) { 5264 error = EINVAL; 5265 break; 5266 } 5267 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5268 error = EINVAL; 5269 break; 5270 } 5271 BGE_LOCK(sc); 5272 if (ifp->if_mtu != ifr->ifr_mtu) { 5273 ifp->if_mtu = ifr->ifr_mtu; 5274 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5275 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5276 bge_init_locked(sc); 5277 } 5278 } 5279 BGE_UNLOCK(sc); 5280 break; 5281 case SIOCSIFFLAGS: 5282 BGE_LOCK(sc); 5283 if (ifp->if_flags & IFF_UP) { 5284 /* 5285 * If only the state of the PROMISC flag changed, 5286 * then just use the 'set promisc mode' command 5287 * instead of reinitializing the entire NIC. Doing 5288 * a full re-init means reloading the firmware and 5289 * waiting for it to start up, which may take a 5290 * second or two. Similarly for ALLMULTI. 5291 */ 5292 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5293 flags = ifp->if_flags ^ sc->bge_if_flags; 5294 if (flags & IFF_PROMISC) 5295 bge_setpromisc(sc); 5296 if (flags & IFF_ALLMULTI) 5297 bge_setmulti(sc); 5298 } else 5299 bge_init_locked(sc); 5300 } else { 5301 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5302 bge_stop(sc); 5303 } 5304 } 5305 sc->bge_if_flags = ifp->if_flags; 5306 BGE_UNLOCK(sc); 5307 error = 0; 5308 break; 5309 case SIOCADDMULTI: 5310 case SIOCDELMULTI: 5311 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5312 BGE_LOCK(sc); 5313 bge_setmulti(sc); 5314 BGE_UNLOCK(sc); 5315 error = 0; 5316 } 5317 break; 5318 case SIOCSIFMEDIA: 5319 case SIOCGIFMEDIA: 5320 if (sc->bge_flags & BGE_FLAG_TBI) { 5321 error = ifmedia_ioctl(ifp, ifr, 5322 &sc->bge_ifmedia, command); 5323 } else { 5324 mii = device_get_softc(sc->bge_miibus); 5325 error = ifmedia_ioctl(ifp, ifr, 5326 &mii->mii_media, command); 5327 } 5328 break; 5329 case SIOCSIFCAP: 5330 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 5331#ifdef DEVICE_POLLING 5332 if (mask & IFCAP_POLLING) { 5333 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5334 error = ether_poll_register(bge_poll, ifp); 5335 if (error) 5336 return (error); 5337 BGE_LOCK(sc); 5338 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5339 BGE_PCIMISCCTL_MASK_PCI_INTR); 5340 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5341 ifp->if_capenable |= IFCAP_POLLING; 5342 BGE_UNLOCK(sc); 5343 } else { 5344 error = ether_poll_deregister(ifp); 5345 /* Enable interrupt even in error case */ 5346 BGE_LOCK(sc); 5347 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5348 BGE_PCIMISCCTL_MASK_PCI_INTR); 5349 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5350 ifp->if_capenable &= ~IFCAP_POLLING; 5351 BGE_UNLOCK(sc); 5352 } 5353 } 5354#endif 5355 if ((mask & IFCAP_TXCSUM) != 0 && 5356 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 5357 ifp->if_capenable ^= IFCAP_TXCSUM; 5358 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 5359 ifp->if_hwassist |= sc->bge_csum_features; 5360 else 5361 ifp->if_hwassist &= ~sc->bge_csum_features; 5362 } 5363 5364 if ((mask & IFCAP_RXCSUM) != 0 && 5365 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 5366 ifp->if_capenable ^= IFCAP_RXCSUM; 5367 5368 if ((mask & IFCAP_TSO4) != 0 && 5369 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 5370 ifp->if_capenable ^= IFCAP_TSO4; 5371 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 5372 ifp->if_hwassist |= CSUM_TSO; 5373 else 5374 ifp->if_hwassist &= ~CSUM_TSO; 5375 } 5376 5377 if (mask & IFCAP_VLAN_MTU) { 5378 ifp->if_capenable ^= IFCAP_VLAN_MTU; 5379 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5380 bge_init(sc); 5381 } 5382 5383 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5384 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 5385 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 5386 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5387 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 5388 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 5389 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 5390 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 5391 BGE_LOCK(sc); 5392 bge_setvlan(sc); 5393 BGE_UNLOCK(sc); 5394 } 5395#ifdef VLAN_CAPABILITIES 5396 VLAN_CAPABILITIES(ifp); 5397#endif 5398 break; 5399 default: 5400 error = ether_ioctl(ifp, command, data); 5401 break; 5402 } 5403 5404 return (error); 5405} 5406 5407static void 5408bge_watchdog(struct bge_softc *sc) 5409{ 5410 struct ifnet *ifp; 5411 5412 BGE_LOCK_ASSERT(sc); 5413 5414 if (sc->bge_timer == 0 || --sc->bge_timer) 5415 return; 5416 5417 ifp = sc->bge_ifp; 5418 5419 if_printf(ifp, "watchdog timeout -- resetting\n"); 5420 5421 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5422 bge_init_locked(sc); 5423 5424 ifp->if_oerrors++; 5425} 5426 5427static void 5428bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5429{ 5430 int i; 5431 5432 BGE_CLRBIT(sc, reg, bit); 5433 5434 for (i = 0; i < BGE_TIMEOUT; i++) { 5435 if ((CSR_READ_4(sc, reg) & bit) == 0) 5436 return; 5437 DELAY(100); 5438 } 5439} 5440 5441/* 5442 * Stop the adapter and free any mbufs allocated to the 5443 * RX and TX lists. 5444 */ 5445static void 5446bge_stop(struct bge_softc *sc) 5447{ 5448 struct ifnet *ifp; 5449 5450 BGE_LOCK_ASSERT(sc); 5451 5452 ifp = sc->bge_ifp; 5453 5454 callout_stop(&sc->bge_stat_ch); 5455 5456 /* Disable host interrupts. */ 5457 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5458 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5459 5460 /* 5461 * Tell firmware we're shutting down. 5462 */ 5463 bge_stop_fw(sc); 5464 bge_sig_pre_reset(sc, BGE_RESET_STOP); 5465 5466 /* 5467 * Disable all of the receiver blocks. 5468 */ 5469 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5470 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5471 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5472 if (BGE_IS_5700_FAMILY(sc)) 5473 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5474 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5475 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5476 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5477 5478 /* 5479 * Disable all of the transmit blocks. 5480 */ 5481 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5482 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5483 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5484 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5485 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5486 if (BGE_IS_5700_FAMILY(sc)) 5487 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5488 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5489 5490 /* 5491 * Shut down all of the memory managers and related 5492 * state machines. 5493 */ 5494 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5495 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5496 if (BGE_IS_5700_FAMILY(sc)) 5497 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5498 5499 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5500 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5501 if (!(BGE_IS_5705_PLUS(sc))) { 5502 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5503 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5504 } 5505 /* Update MAC statistics. */ 5506 if (BGE_IS_5705_PLUS(sc)) 5507 bge_stats_update_regs(sc); 5508 5509 bge_reset(sc); 5510 bge_sig_legacy(sc, BGE_RESET_STOP); 5511 bge_sig_post_reset(sc, BGE_RESET_STOP); 5512 5513 /* 5514 * Keep the ASF firmware running if up. 5515 */ 5516 if (sc->bge_asf_mode & ASF_STACKUP) 5517 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5518 else 5519 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5520 5521 /* Free the RX lists. */ 5522 bge_free_rx_ring_std(sc); 5523 5524 /* Free jumbo RX list. */ 5525 if (BGE_IS_JUMBO_CAPABLE(sc)) 5526 bge_free_rx_ring_jumbo(sc); 5527 5528 /* Free TX buffers. */ 5529 bge_free_tx_ring(sc); 5530 5531 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5532 5533 /* Clear MAC's link state (PHY may still have link UP). */ 5534 if (bootverbose && sc->bge_link) 5535 if_printf(sc->bge_ifp, "link DOWN\n"); 5536 sc->bge_link = 0; 5537 5538 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 5539} 5540 5541/* 5542 * Stop all chip I/O so that the kernel's probe routines don't 5543 * get confused by errant DMAs when rebooting. 5544 */ 5545static int 5546bge_shutdown(device_t dev) 5547{ 5548 struct bge_softc *sc; 5549 5550 sc = device_get_softc(dev); 5551 BGE_LOCK(sc); 5552 bge_stop(sc); 5553 bge_reset(sc); 5554 BGE_UNLOCK(sc); 5555 5556 return (0); 5557} 5558 5559static int 5560bge_suspend(device_t dev) 5561{ 5562 struct bge_softc *sc; 5563 5564 sc = device_get_softc(dev); 5565 BGE_LOCK(sc); 5566 bge_stop(sc); 5567 BGE_UNLOCK(sc); 5568 5569 return (0); 5570} 5571 5572static int 5573bge_resume(device_t dev) 5574{ 5575 struct bge_softc *sc; 5576 struct ifnet *ifp; 5577 5578 sc = device_get_softc(dev); 5579 BGE_LOCK(sc); 5580 ifp = sc->bge_ifp; 5581 if (ifp->if_flags & IFF_UP) { 5582 bge_init_locked(sc); 5583 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5584 bge_start_locked(ifp); 5585 } 5586 BGE_UNLOCK(sc); 5587 5588 return (0); 5589} 5590 5591static void 5592bge_link_upd(struct bge_softc *sc) 5593{ 5594 struct mii_data *mii; 5595 uint32_t link, status; 5596 5597 BGE_LOCK_ASSERT(sc); 5598 5599 /* Clear 'pending link event' flag. */ 5600 sc->bge_link_evt = 0; 5601 5602 /* 5603 * Process link state changes. 5604 * Grrr. The link status word in the status block does 5605 * not work correctly on the BCM5700 rev AX and BX chips, 5606 * according to all available information. Hence, we have 5607 * to enable MII interrupts in order to properly obtain 5608 * async link changes. Unfortunately, this also means that 5609 * we have to read the MAC status register to detect link 5610 * changes, thereby adding an additional register access to 5611 * the interrupt handler. 5612 * 5613 * XXX: perhaps link state detection procedure used for 5614 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 5615 */ 5616 5617 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 5618 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 5619 status = CSR_READ_4(sc, BGE_MAC_STS); 5620 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5621 mii = device_get_softc(sc->bge_miibus); 5622 mii_pollstat(mii); 5623 if (!sc->bge_link && 5624 mii->mii_media_status & IFM_ACTIVE && 5625 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5626 sc->bge_link++; 5627 if (bootverbose) 5628 if_printf(sc->bge_ifp, "link UP\n"); 5629 } else if (sc->bge_link && 5630 (!(mii->mii_media_status & IFM_ACTIVE) || 5631 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 5632 sc->bge_link = 0; 5633 if (bootverbose) 5634 if_printf(sc->bge_ifp, "link DOWN\n"); 5635 } 5636 5637 /* Clear the interrupt. */ 5638 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5639 BGE_EVTENB_MI_INTERRUPT); 5640 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 5641 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 5642 BRGPHY_INTRS); 5643 } 5644 return; 5645 } 5646 5647 if (sc->bge_flags & BGE_FLAG_TBI) { 5648 status = CSR_READ_4(sc, BGE_MAC_STS); 5649 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5650 if (!sc->bge_link) { 5651 sc->bge_link++; 5652 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 5653 BGE_CLRBIT(sc, BGE_MAC_MODE, 5654 BGE_MACMODE_TBI_SEND_CFGS); 5655 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5656 if (bootverbose) 5657 if_printf(sc->bge_ifp, "link UP\n"); 5658 if_link_state_change(sc->bge_ifp, 5659 LINK_STATE_UP); 5660 } 5661 } else if (sc->bge_link) { 5662 sc->bge_link = 0; 5663 if (bootverbose) 5664 if_printf(sc->bge_ifp, "link DOWN\n"); 5665 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 5666 } 5667 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 5668 /* 5669 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 5670 * in status word always set. Workaround this bug by reading 5671 * PHY link status directly. 5672 */ 5673 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 5674 5675 if (link != sc->bge_link || 5676 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 5677 mii = device_get_softc(sc->bge_miibus); 5678 mii_pollstat(mii); 5679 if (!sc->bge_link && 5680 mii->mii_media_status & IFM_ACTIVE && 5681 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5682 sc->bge_link++; 5683 if (bootverbose) 5684 if_printf(sc->bge_ifp, "link UP\n"); 5685 } else if (sc->bge_link && 5686 (!(mii->mii_media_status & IFM_ACTIVE) || 5687 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 5688 sc->bge_link = 0; 5689 if (bootverbose) 5690 if_printf(sc->bge_ifp, "link DOWN\n"); 5691 } 5692 } 5693 } else { 5694 /* 5695 * For controllers that call mii_tick, we have to poll 5696 * link status. 5697 */ 5698 mii = device_get_softc(sc->bge_miibus); 5699 mii_pollstat(mii); 5700 bge_miibus_statchg(sc->bge_dev); 5701 } 5702 5703 /* Clear the attention. */ 5704 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 5705 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 5706 BGE_MACSTAT_LINK_CHANGED); 5707} 5708 5709static void 5710bge_add_sysctls(struct bge_softc *sc) 5711{ 5712 struct sysctl_ctx_list *ctx; 5713 struct sysctl_oid_list *children; 5714 char tn[32]; 5715 int unit; 5716 5717 ctx = device_get_sysctl_ctx(sc->bge_dev); 5718 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 5719 5720#ifdef BGE_REGISTER_DEBUG 5721 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 5722 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 5723 "Debug Information"); 5724 5725 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 5726 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 5727 "Register Read"); 5728 5729 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 5730 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 5731 "Memory Read"); 5732 5733#endif 5734 5735 unit = device_get_unit(sc->bge_dev); 5736 /* 5737 * A common design characteristic for many Broadcom client controllers 5738 * is that they only support a single outstanding DMA read operation 5739 * on the PCIe bus. This means that it will take twice as long to fetch 5740 * a TX frame that is split into header and payload buffers as it does 5741 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 5742 * these controllers, coalescing buffers to reduce the number of memory 5743 * reads is effective way to get maximum performance(about 940Mbps). 5744 * Without collapsing TX buffers the maximum TCP bulk transfer 5745 * performance is about 850Mbps. However forcing coalescing mbufs 5746 * consumes a lot of CPU cycles, so leave it off by default. 5747 */ 5748 sc->bge_forced_collapse = 0; 5749 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit); 5750 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse); 5751 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 5752 CTLFLAG_RW, &sc->bge_forced_collapse, 0, 5753 "Number of fragmented TX buffers of a frame allowed before " 5754 "forced collapsing"); 5755 5756 sc->bge_msi = 1; 5757 snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit); 5758 TUNABLE_INT_FETCH(tn, &sc->bge_msi); 5759 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi", 5760 CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI"); 5761 5762 /* 5763 * It seems all Broadcom controllers have a bug that can generate UDP 5764 * datagrams with checksum value 0 when TX UDP checksum offloading is 5765 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 5766 * Even though the probability of generating such UDP datagrams is 5767 * low, I don't want to see FreeBSD boxes to inject such datagrams 5768 * into network so disable UDP checksum offloading by default. Users 5769 * still override this behavior by setting a sysctl variable, 5770 * dev.bge.0.forced_udpcsum. 5771 */ 5772 sc->bge_forced_udpcsum = 0; 5773 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit); 5774 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum); 5775 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 5776 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0, 5777 "Enable UDP checksum offloading even if controller can " 5778 "generate UDP checksum value 0"); 5779 5780 if (BGE_IS_5705_PLUS(sc)) 5781 bge_add_sysctl_stats_regs(sc, ctx, children); 5782 else 5783 bge_add_sysctl_stats(sc, ctx, children); 5784} 5785 5786#define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 5787 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 5788 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 5789 desc) 5790 5791static void 5792bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 5793 struct sysctl_oid_list *parent) 5794{ 5795 struct sysctl_oid *tree; 5796 struct sysctl_oid_list *children, *schildren; 5797 5798 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 5799 NULL, "BGE Statistics"); 5800 schildren = children = SYSCTL_CHILDREN(tree); 5801 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 5802 children, COSFramesDroppedDueToFilters, 5803 "FramesDroppedDueToFilters"); 5804 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 5805 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 5806 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 5807 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 5808 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 5809 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 5810 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 5811 children, ifInDiscards, "InputDiscards"); 5812 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 5813 children, ifInErrors, "InputErrors"); 5814 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 5815 children, nicRecvThresholdHit, "RecvThresholdHit"); 5816 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 5817 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 5818 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 5819 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 5820 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 5821 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 5822 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 5823 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 5824 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 5825 children, nicRingStatusUpdate, "RingStatusUpdate"); 5826 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 5827 children, nicInterrupts, "Interrupts"); 5828 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 5829 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 5830 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 5831 children, nicSendThresholdHit, "SendThresholdHit"); 5832 5833 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 5834 NULL, "BGE RX Statistics"); 5835 children = SYSCTL_CHILDREN(tree); 5836 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 5837 children, rxstats.ifHCInOctets, "ifHCInOctets"); 5838 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 5839 children, rxstats.etherStatsFragments, "Fragments"); 5840 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 5841 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 5842 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 5843 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 5844 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 5845 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 5846 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 5847 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 5848 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 5849 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 5850 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 5851 children, rxstats.xoffPauseFramesReceived, 5852 "xoffPauseFramesReceived"); 5853 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 5854 children, rxstats.macControlFramesReceived, 5855 "ControlFramesReceived"); 5856 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 5857 children, rxstats.xoffStateEntered, "xoffStateEntered"); 5858 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 5859 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 5860 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 5861 children, rxstats.etherStatsJabbers, "Jabbers"); 5862 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 5863 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 5864 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 5865 children, rxstats.inRangeLengthError, "inRangeLengthError"); 5866 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 5867 children, rxstats.outRangeLengthError, "outRangeLengthError"); 5868 5869 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 5870 NULL, "BGE TX Statistics"); 5871 children = SYSCTL_CHILDREN(tree); 5872 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 5873 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 5874 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 5875 children, txstats.etherStatsCollisions, "Collisions"); 5876 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 5877 children, txstats.outXonSent, "XonSent"); 5878 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 5879 children, txstats.outXoffSent, "XoffSent"); 5880 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 5881 children, txstats.flowControlDone, "flowControlDone"); 5882 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 5883 children, txstats.dot3StatsInternalMacTransmitErrors, 5884 "InternalMacTransmitErrors"); 5885 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 5886 children, txstats.dot3StatsSingleCollisionFrames, 5887 "SingleCollisionFrames"); 5888 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 5889 children, txstats.dot3StatsMultipleCollisionFrames, 5890 "MultipleCollisionFrames"); 5891 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 5892 children, txstats.dot3StatsDeferredTransmissions, 5893 "DeferredTransmissions"); 5894 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 5895 children, txstats.dot3StatsExcessiveCollisions, 5896 "ExcessiveCollisions"); 5897 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 5898 children, txstats.dot3StatsLateCollisions, 5899 "LateCollisions"); 5900 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 5901 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 5902 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 5903 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 5904 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 5905 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 5906 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 5907 children, txstats.dot3StatsCarrierSenseErrors, 5908 "CarrierSenseErrors"); 5909 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 5910 children, txstats.ifOutDiscards, "Discards"); 5911 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 5912 children, txstats.ifOutErrors, "Errors"); 5913} 5914 5915#undef BGE_SYSCTL_STAT 5916 5917#define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 5918 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 5919 5920static void 5921bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 5922 struct sysctl_oid_list *parent) 5923{ 5924 struct sysctl_oid *tree; 5925 struct sysctl_oid_list *child, *schild; 5926 struct bge_mac_stats *stats; 5927 5928 stats = &sc->bge_mac_stats; 5929 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 5930 NULL, "BGE Statistics"); 5931 schild = child = SYSCTL_CHILDREN(tree); 5932 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 5933 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 5934 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 5935 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 5936 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 5937 &stats->DmaWriteHighPriQueueFull, 5938 "NIC DMA Write High Priority Queue Full"); 5939 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 5940 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 5941 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 5942 &stats->InputDiscards, "Discarded Input Frames"); 5943 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 5944 &stats->InputErrors, "Input Errors"); 5945 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 5946 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 5947 5948 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 5949 NULL, "BGE RX Statistics"); 5950 child = SYSCTL_CHILDREN(tree); 5951 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 5952 &stats->ifHCInOctets, "Inbound Octets"); 5953 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 5954 &stats->etherStatsFragments, "Fragments"); 5955 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 5956 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 5957 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 5958 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 5959 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 5960 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 5961 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 5962 &stats->dot3StatsFCSErrors, "FCS Errors"); 5963 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 5964 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 5965 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 5966 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 5967 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 5968 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 5969 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 5970 &stats->macControlFramesReceived, "MAC Control Frames Received"); 5971 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 5972 &stats->xoffStateEntered, "XOFF State Entered"); 5973 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 5974 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 5975 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 5976 &stats->etherStatsJabbers, "Jabbers"); 5977 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 5978 &stats->etherStatsUndersizePkts, "Undersized Packets"); 5979 5980 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 5981 NULL, "BGE TX Statistics"); 5982 child = SYSCTL_CHILDREN(tree); 5983 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 5984 &stats->ifHCOutOctets, "Outbound Octets"); 5985 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 5986 &stats->etherStatsCollisions, "TX Collisions"); 5987 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 5988 &stats->outXonSent, "XON Sent"); 5989 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 5990 &stats->outXoffSent, "XOFF Sent"); 5991 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 5992 &stats->dot3StatsInternalMacTransmitErrors, 5993 "Internal MAC TX Errors"); 5994 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 5995 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 5996 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 5997 &stats->dot3StatsMultipleCollisionFrames, 5998 "Multiple Collision Frames"); 5999 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 6000 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 6001 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 6002 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 6003 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 6004 &stats->dot3StatsLateCollisions, "Late Collisions"); 6005 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6006 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 6007 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6008 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 6009 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6010 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 6011} 6012 6013#undef BGE_SYSCTL_STAT_ADD64 6014 6015static int 6016bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 6017{ 6018 struct bge_softc *sc; 6019 uint32_t result; 6020 int offset; 6021 6022 sc = (struct bge_softc *)arg1; 6023 offset = arg2; 6024 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 6025 offsetof(bge_hostaddr, bge_addr_lo)); 6026 return (sysctl_handle_int(oidp, &result, 0, req)); 6027} 6028 6029#ifdef BGE_REGISTER_DEBUG 6030static int 6031bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 6032{ 6033 struct bge_softc *sc; 6034 uint16_t *sbdata; 6035 int error, result, sbsz; 6036 int i, j; 6037 6038 result = -1; 6039 error = sysctl_handle_int(oidp, &result, 0, req); 6040 if (error || (req->newptr == NULL)) 6041 return (error); 6042 6043 if (result == 1) { 6044 sc = (struct bge_softc *)arg1; 6045 6046 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6047 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 6048 sbsz = BGE_STATUS_BLK_SZ; 6049 else 6050 sbsz = 32; 6051 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 6052 printf("Status Block:\n"); 6053 BGE_LOCK(sc); 6054 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6055 sc->bge_cdata.bge_status_map, 6056 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6057 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 6058 printf("%06x:", i); 6059 for (j = 0; j < 8; j++) 6060 printf(" %04x", sbdata[i++]); 6061 printf("\n"); 6062 } 6063 6064 printf("Registers:\n"); 6065 for (i = 0x800; i < 0xA00; ) { 6066 printf("%06x:", i); 6067 for (j = 0; j < 8; j++) { 6068 printf(" %08x", CSR_READ_4(sc, i)); 6069 i += 4; 6070 } 6071 printf("\n"); 6072 } 6073 BGE_UNLOCK(sc); 6074 6075 printf("Hardware Flags:\n"); 6076 if (BGE_IS_5717_PLUS(sc)) 6077 printf(" - 5717 Plus\n"); 6078 if (BGE_IS_5755_PLUS(sc)) 6079 printf(" - 5755 Plus\n"); 6080 if (BGE_IS_575X_PLUS(sc)) 6081 printf(" - 575X Plus\n"); 6082 if (BGE_IS_5705_PLUS(sc)) 6083 printf(" - 5705 Plus\n"); 6084 if (BGE_IS_5714_FAMILY(sc)) 6085 printf(" - 5714 Family\n"); 6086 if (BGE_IS_5700_FAMILY(sc)) 6087 printf(" - 5700 Family\n"); 6088 if (sc->bge_flags & BGE_FLAG_JUMBO) 6089 printf(" - Supports Jumbo Frames\n"); 6090 if (sc->bge_flags & BGE_FLAG_PCIX) 6091 printf(" - PCI-X Bus\n"); 6092 if (sc->bge_flags & BGE_FLAG_PCIE) 6093 printf(" - PCI Express Bus\n"); 6094 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 6095 printf(" - No 3 LEDs\n"); 6096 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 6097 printf(" - RX Alignment Bug\n"); 6098 } 6099 6100 return (error); 6101} 6102 6103static int 6104bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 6105{ 6106 struct bge_softc *sc; 6107 int error; 6108 uint16_t result; 6109 uint32_t val; 6110 6111 result = -1; 6112 error = sysctl_handle_int(oidp, &result, 0, req); 6113 if (error || (req->newptr == NULL)) 6114 return (error); 6115 6116 if (result < 0x8000) { 6117 sc = (struct bge_softc *)arg1; 6118 val = CSR_READ_4(sc, result); 6119 printf("reg 0x%06X = 0x%08X\n", result, val); 6120 } 6121 6122 return (error); 6123} 6124 6125static int 6126bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 6127{ 6128 struct bge_softc *sc; 6129 int error; 6130 uint16_t result; 6131 uint32_t val; 6132 6133 result = -1; 6134 error = sysctl_handle_int(oidp, &result, 0, req); 6135 if (error || (req->newptr == NULL)) 6136 return (error); 6137 6138 if (result < 0x8000) { 6139 sc = (struct bge_softc *)arg1; 6140 val = bge_readmem_ind(sc, result); 6141 printf("mem 0x%06X = 0x%08X\n", result, val); 6142 } 6143 6144 return (error); 6145} 6146#endif 6147 6148static int 6149bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6150{ 6151 6152 if (sc->bge_flags & BGE_FLAG_EADDR) 6153 return (1); 6154 6155#ifdef __sparc64__ 6156 OF_getetheraddr(sc->bge_dev, ether_addr); 6157 return (0); 6158#endif 6159 return (1); 6160} 6161 6162static int 6163bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6164{ 6165 uint32_t mac_addr; 6166 6167 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6168 if ((mac_addr >> 16) == 0x484b) { 6169 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6170 ether_addr[1] = (uint8_t)mac_addr; 6171 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6172 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6173 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6174 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6175 ether_addr[5] = (uint8_t)mac_addr; 6176 return (0); 6177 } 6178 return (1); 6179} 6180 6181static int 6182bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6183{ 6184 int mac_offset = BGE_EE_MAC_OFFSET; 6185 6186 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6187 mac_offset = BGE_EE_MAC_OFFSET_5906; 6188 6189 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6190 ETHER_ADDR_LEN)); 6191} 6192 6193static int 6194bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6195{ 6196 6197 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6198 return (1); 6199 6200 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6201 ETHER_ADDR_LEN)); 6202} 6203 6204static int 6205bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6206{ 6207 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6208 /* NOTE: Order is critical */ 6209 bge_get_eaddr_fw, 6210 bge_get_eaddr_mem, 6211 bge_get_eaddr_nvram, 6212 bge_get_eaddr_eeprom, 6213 NULL 6214 }; 6215 const bge_eaddr_fcn_t *func; 6216 6217 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6218 if ((*func)(sc, eaddr) == 0) 6219 break; 6220 } 6221 return (*func == NULL ? ENXIO : 0); 6222} 6223