1 2/******************************************************************************/ 3/* */ 4/* Broadcom BCM4400 Linux Network Driver, Copyright (c) 2002 Broadcom */ 5/* Corporation. */ 6/* All rights reserved. */ 7/* */ 8/* This program is free software; you can redistribute it and/or modify */ 9/* it under the terms of the GNU General Public License as published by */ 10/* the Free Software Foundation, located in the file LICENSE. */ 11/* */ 12/* History: */ 13/* 02/25/00 Hav Khauv Initial version. */ 14/******************************************************************************/ 15 16#ifndef B44LM_H 17#define B44LM_H 18 19#include "b44queue.h" 20 21 22 23/******************************************************************************/ 24/* Basic types. */ 25/******************************************************************************/ 26 27typedef char LM_CHAR, *PLM_CHAR; 28typedef unsigned int LM_UINT, *PLM_UINT; 29typedef unsigned char LM_UINT8, *PLM_UINT8; 30typedef unsigned short LM_UINT16, *PLM_UINT16; 31typedef unsigned int LM_UINT32, *PLM_UINT32; 32typedef unsigned long LM_COUNTER, *PLM_COUNTER; 33typedef void LM_VOID, *PLM_VOID; 34typedef char LM_BOOL, *PLM_BOOL; 35 36typedef LM_UINT32 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; 37 38#ifndef TRUE 39#define TRUE 1 40#endif /* TRUE */ 41 42#ifndef FALSE 43#define FALSE 0 44#endif /* FALSE */ 45 46#ifndef NULL 47#define NULL ((void *) 0) 48#endif /* NULL */ 49 50#ifndef OFFSETOF 51#define OFFSETOF(_s, _m) (B44_MM_PTR(&(((_s *) 0)->_m))) 52#endif /* OFFSETOF */ 53 54 55 56/******************************************************************************/ 57/* Simple macros. */ 58/******************************************************************************/ 59 60#define IS_ETH_BROADCAST(_pEthAddr) \ 61 (((unsigned char *) (_pEthAddr))[0] == ((unsigned char) 0xff)) 62 63#define IS_ETH_MULTICAST(_pEthAddr) \ 64 (((unsigned char *) (_pEthAddr))[0] & ((unsigned char) 0x01)) 65 66#define IS_ETH_ADDRESS_EQUAL(_pEtherAddr1, _pEtherAddr2) \ 67 ((((unsigned char *) (_pEtherAddr1))[0] == \ 68 ((unsigned char *) (_pEtherAddr2))[0]) && \ 69 (((unsigned char *) (_pEtherAddr1))[1] == \ 70 ((unsigned char *) (_pEtherAddr2))[1]) && \ 71 (((unsigned char *) (_pEtherAddr1))[2] == \ 72 ((unsigned char *) (_pEtherAddr2))[2]) && \ 73 (((unsigned char *) (_pEtherAddr1))[3] == \ 74 ((unsigned char *) (_pEtherAddr2))[3]) && \ 75 (((unsigned char *) (_pEtherAddr1))[4] == \ 76 ((unsigned char *) (_pEtherAddr2))[4]) && \ 77 (((unsigned char *) (_pEtherAddr1))[5] == \ 78 ((unsigned char *) (_pEtherAddr2))[5])) 79 80#define COPY_ETH_ADDRESS(_Src, _Dst) \ 81 ((unsigned char *) (_Dst))[0] = ((unsigned char *) (_Src))[0]; \ 82 ((unsigned char *) (_Dst))[1] = ((unsigned char *) (_Src))[1]; \ 83 ((unsigned char *) (_Dst))[2] = ((unsigned char *) (_Src))[2]; \ 84 ((unsigned char *) (_Dst))[3] = ((unsigned char *) (_Src))[3]; \ 85 ((unsigned char *) (_Dst))[4] = ((unsigned char *) (_Src))[4]; \ 86 ((unsigned char *) (_Dst))[5] = ((unsigned char *) (_Src))[5]; 87 88 89 90/******************************************************************************/ 91/* Constants. */ 92/******************************************************************************/ 93 94#define ETHERNET_ADDRESS_SIZE 6 95#define ETHERNET_PACKET_HEADER_SIZE 14 96#define MIN_ETHERNET_PACKET_SIZE 64 /* with 4 byte crc. */ 97#define MAX_ETHERNET_PACKET_SIZE 1518 /* with 4 byte crc. */ 98#define MIN_ETHERNET_PACKET_SIZE_NO_CRC 60 99#define MAX_ETHERNET_PACKET_SIZE_NO_CRC 1514 100#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */ 101 102#ifndef LM_MAX_MC_TABLE_SIZE 103#define LM_MAX_MC_TABLE_SIZE 63 104#endif /* LM_MAX_MC_TABLE_SIZE */ 105#define LM_MC_ENTRY_SIZE (ETHERNET_ADDRESS_SIZE+1) 106#define LM_MC_INSTANCE_COUNT_INDEX (LM_MC_ENTRY_SIZE-1) 107 108 109/* Receive filter masks. */ 110#define LM_ACCEPT_UNICAST 0x0001 111#define LM_ACCEPT_MULTICAST 0x0002 112#define LM_ACCEPT_ALL_MULTICAST 0x0004 113#define LM_ACCEPT_BROADCAST 0x0008 114#define LM_ACCEPT_ERROR_PACKET 0x0010 115 116#define LM_PROMISCUOUS_MODE 0x10000 117 118 119 120/******************************************************************************/ 121/* PCI registers. */ 122/******************************************************************************/ 123 124#define PCI_VENDOR_ID_REG 0x00 125#define PCI_DEVICE_ID_REG 0x02 126 127#define PCI_COMMAND_REG 0x04 128#define PCI_IO_SPACE_ENABLE 0x0001 129#define PCI_MEM_SPACE_ENABLE 0x0002 130#define PCI_BUSMASTER_ENABLE 0x0004 131#define PCI_MEMORY_WRITE_INVALIDATE 0x0010 132#define PCI_PARITY_ERROR_ENABLE 0x0040 133#define PCI_SYSTEM_ERROR_ENABLE 0x0100 134#define PCI_FAST_BACK_TO_BACK_ENABLE 0x0200 135 136#define PCI_STATUS_REG 0x06 137#define PCI_REV_ID_REG 0x08 138 139#define PCI_CACHE_LINE_SIZE_REG 0x0c 140 141#define PCI_IO_BASE_ADDR_REG 0x10 142#define PCI_IO_BASE_ADDR_MASK 0xfffffff0 143 144#define PCI_MEM_BASE_ADDR_LOW 0x10 145#define PCI_MEM_BASE_ADDR_HIGH 0x14 146 147#define PCI_SUBSYSTEM_VENDOR_ID_REG 0x2c 148#define PCI_SUBSYSTEM_ID_REG 0x2e 149#define PCI_INT_LINE_REG 0x3c 150 151#define PCIX_CAP_REG 0x40 152#define PCIX_ENABLE_RELAXED_ORDERING BIT_17 153 154/******************************************************************************/ 155/* Fragment structure. */ 156/******************************************************************************/ 157 158typedef struct { 159 LM_UINT32 FragSize; 160 LM_PHYSICAL_ADDRESS FragBuf; 161} LM_FRAG, *PLM_FRAG; 162 163typedef struct { 164 /* FragCount is initialized for the caller to the maximum array size, on */ 165 /* return FragCount is the number of the actual fragments in the array. */ 166 LM_UINT32 FragCount; 167 168 /* Total buffer size. */ 169 LM_UINT32 TotalSize; 170 171 /* Fragment array buffer. */ 172 LM_FRAG Fragments[1]; 173} LM_FRAG_LIST, *PLM_FRAG_LIST; 174 175#define DECLARE_FRAG_LIST_BUFFER_TYPE(_FRAG_LIST_TYPE_NAME, _MAX_FRAG_COUNT) \ 176 typedef struct { \ 177 LM_FRAG_LIST FragList; \ 178 LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1]; \ 179 } _FRAG_LIST_TYPE_NAME, *P##_FRAG_LIST_TYPE_NAME 180 181 182 183/******************************************************************************/ 184/* Status codes. */ 185/******************************************************************************/ 186 187#define LM_STATUS_SUCCESS 0 188#define LM_STATUS_FAILURE 1 189 190#define LM_STATUS_INTERRUPT_ACTIVE 2 191#define LM_STATUS_INTERRUPT_NOT_ACTIVE 3 192 193#define LM_STATUS_LINK_ACTIVE 4 194#define LM_STATUS_LINK_DOWN 5 195#define LM_STATUS_LINK_SETTING_MISMATCH 6 196 197#define LM_STATUS_TOO_MANY_FRAGMENTS 7 198#define LM_STATUS_TRANSMIT_ABORTED 8 199#define LM_STATUS_TRANSMIT_ERROR 9 200#define LM_STATUS_RECEIVE_ABORTED 10 201#define LM_STATUS_RECEIVE_ERROR 11 202#define LM_STATUS_INVALID_PACKET_SIZE 12 203#define LM_STATUS_OUT_OF_MAP_REGISTERS 13 204#define LM_STATUS_UNKNOWN_ADAPTER 14 205 206typedef LM_UINT LM_STATUS, *PLM_STATUS; 207 208 209/******************************************************************************/ 210/* Line speed. */ 211/******************************************************************************/ 212 213#define LM_LINE_SPEED_UNKNOWN 0 214#define LM_LINE_SPEED_AUTO LM_LINE_SPEED_UNKNOWN 215#define LM_LINE_SPEED_10MBPS 10 216#define LM_LINE_SPEED_100MBPS 100 217 218typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED; 219 220 221 222/******************************************************************************/ 223/* Duplex mode. */ 224/******************************************************************************/ 225 226#define LM_DUPLEX_MODE_UNKNOWN 0 227#define LM_DUPLEX_MODE_HALF 1 228#define LM_DUPLEX_MODE_FULL 2 229 230typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE; 231 232 233 234/******************************************************************************/ 235/* Power state. */ 236/******************************************************************************/ 237 238#define LM_POWER_STATE_D0 0 239#define LM_POWER_STATE_D1 1 240#define LM_POWER_STATE_D2 2 241#define LM_POWER_STATE_D3 3 242 243typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE; 244 245 246 247/******************************************************************************/ 248/* Task offloading. */ 249/******************************************************************************/ 250 251#define LM_TASK_OFFLOAD_NONE 0x0000 252#define LM_TASK_OFFLOAD_TX_IP_CHECKSUM 0x0001 253#define LM_TASK_OFFLOAD_RX_IP_CHECKSUM 0x0002 254#define LM_TASK_OFFLOAD_TX_TCP_CHECKSUM 0x0004 255#define LM_TASK_OFFLOAD_RX_TCP_CHECKSUM 0x0008 256#define LM_TASK_OFFLOAD_TX_UDP_CHECKSUM 0x0010 257#define LM_TASK_OFFLOAD_RX_UDP_CHECKSUM 0x0020 258#define LM_TASK_OFFLOAD_TCP_SEGMENTATION 0x0040 259 260typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD; 261 262 263 264/******************************************************************************/ 265/* Flow control. */ 266/******************************************************************************/ 267 268#define LM_FLOW_CONTROL_NONE 0x00 269#define LM_FLOW_CONTROL_RECEIVE_PAUSE 0x01 270#define LM_FLOW_CONTROL_TRANSMIT_PAUSE 0x02 271#define LM_FLOW_CONTROL_RX_TX_PAUSE (LM_FLOW_CONTROL_RECEIVE_PAUSE | \ 272 LM_FLOW_CONTROL_TRANSMIT_PAUSE) 273 274/* This value can be or-ed with RECEIVE_PAUSE and TRANSMIT_PAUSE. If the */ 275/* auto-negotiation is disabled and the RECEIVE_PAUSE and TRANSMIT_PAUSE */ 276/* bits are set, then flow control is enabled regardless of link partner's */ 277/* flow control capability. */ 278#define LM_FLOW_CONTROL_AUTO_PAUSE 0x80000000 279 280typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL; 281 282 283 284/******************************************************************************/ 285/* Wake up mode. */ 286/******************************************************************************/ 287 288#define LM_WAKE_UP_MODE_NONE 0 289#define LM_WAKE_UP_MODE_MAGIC_PACKET 1 290#define LM_WAKE_UP_MODE_NWUF 2 291#define LM_WAKE_UP_MODE_LINK_CHANGE 4 292 293typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE; 294 295 296 297/******************************************************************************/ 298/* Counters. */ 299/******************************************************************************/ 300 301#define LM_COUNTER_FRAMES_XMITTED_OK 0 302#define LM_COUNTER_FRAMES_RECEIVED_OK 1 303#define LM_COUNTER_ERRORED_TRANSMIT_COUNT 2 304#define LM_COUNTER_ERRORED_RECEIVE_COUNT 3 305#define LM_COUNTER_RCV_CRC_ERROR 4 306#define LM_COUNTER_ALIGNMENT_ERROR 5 307#define LM_COUNTER_SINGLE_COLLISION_FRAMES 6 308#define LM_COUNTER_MULTIPLE_COLLISION_FRAMES 7 309#define LM_COUNTER_FRAMES_DEFERRED 8 310#define LM_COUNTER_MAX_COLLISIONS 9 311#define LM_COUNTER_RCV_OVERRUN 10 312#define LM_COUNTER_XMIT_UNDERRUN 11 313#define LM_COUNTER_UNICAST_FRAMES_XMIT 12 314#define LM_COUNTER_MULTICAST_FRAMES_XMIT 13 315#define LM_COUNTER_BROADCAST_FRAMES_XMIT 14 316#define LM_COUNTER_UNICAST_FRAMES_RCV 15 317#define LM_COUNTER_MULTICAST_FRAMES_RCV 16 318#define LM_COUNTER_BROADCAST_FRAMES_RCV 17 319 320typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE; 321 322 323 324/******************************************************************************/ 325/* Forward definition. */ 326/******************************************************************************/ 327 328typedef struct _LM_DEVICE_BLOCK *PLM_DEVICE_BLOCK; 329typedef struct _LM_PACKET *PLM_PACKET; 330 331 332 333/******************************************************************************/ 334/* Function prototypes. */ 335/******************************************************************************/ 336 337LM_STATUS b44_LM_GetAdapterInfo(PLM_DEVICE_BLOCK pDevice); 338LM_STATUS b44_LM_InitializeAdapter(PLM_DEVICE_BLOCK pDevice); 339LM_STATUS b44_LM_ResetAdapter(PLM_DEVICE_BLOCK pDevice, LM_BOOL full); 340LM_STATUS b44_LM_DisableInterrupt(PLM_DEVICE_BLOCK pDevice); 341LM_STATUS b44_LM_EnableInterrupt(PLM_DEVICE_BLOCK pDevice); 342LM_STATUS b44_LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); 343LM_STATUS b44_LM_ServiceInterrupts(PLM_DEVICE_BLOCK pDevice); 344#ifdef BCM_NAPI_RXPOLL 345int b44_LM_ServiceRxPoll(PLM_DEVICE_BLOCK pDevice, int limit); 346#endif 347LM_STATUS b44_LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice); 348LM_STATUS b44_LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask); 349LM_STATUS b44_LM_Halt(PLM_DEVICE_BLOCK pDevice); 350LM_STATUS b44_LM_Abort(PLM_DEVICE_BLOCK pDevice); 351LM_STATUS b44_LM_MulticastAdd(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); 352LM_STATUS b44_LM_MulticastDel(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); 353LM_STATUS b44_LM_MulticastClear(PLM_DEVICE_BLOCK pDevice); 354LM_STATUS b44_LM_SetMacAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress); 355LM_STATUS b44_LM_LoopbackAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress); 356 357LM_WAKE_UP_MODE b44_LM_PMCapabilities(PLM_DEVICE_BLOCK pDevice); 358LM_STATUS b44_LM_SetPowerState(PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel); 359 360LM_VOID b44_LM_ReadPhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, 361 PLM_UINT32 pData32); 362LM_VOID b44_LM_WritePhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, 363 LM_UINT32 Data32); 364 365LM_STATUS b44_LM_SetupPhy(PLM_DEVICE_BLOCK pDevice); 366LM_STATUS b44_LM_ResetPhy(PLM_DEVICE_BLOCK pDevice); 367LM_STATUS b44_LM_GetStats(PLM_DEVICE_BLOCK pDevice); 368LM_STATUS b44_LM_NvramRead(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, 369 LM_UINT32 *pData); 370LM_STATUS b44_LM_NvramWriteBlock(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, 371 LM_UINT32 *pData, LM_UINT32 Size); 372void b44_LM_PollLink(PLM_DEVICE_BLOCK pDevice); 373LM_STATUS b44_LM_StatsUpdate(PLM_DEVICE_BLOCK pDevice); 374#ifdef BCM_WOL 375LM_VOID b44_LM_pmset(PLM_DEVICE_BLOCK pDevice); 376#endif 377LM_VOID b44_LM_PowerDownPhy(PLM_DEVICE_BLOCK pDevice); 378 379/******************************************************************************/ 380/* These are the OS specific functions called by LMAC. */ 381/******************************************************************************/ 382 383LM_STATUS b44_MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, 384 LM_UINT16 *pValue16); 385LM_STATUS b44_MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, 386 LM_UINT16 Value16); 387LM_STATUS b44_MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, 388 LM_UINT32 *pValue32); 389LM_STATUS b44_MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, 390 LM_UINT32 Value32); 391LM_STATUS b44_MM_MapMemBase(PLM_DEVICE_BLOCK pDevice); 392LM_STATUS b44_MM_MapIoBase(PLM_DEVICE_BLOCK pDevice); 393LM_STATUS b44_MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice); 394LM_STATUS b44_MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice); 395LM_STATUS b44_MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); 396LM_STATUS b44_MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); 397LM_STATUS b44_MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, 398 PLM_VOID *pMemoryBlockVirt); 399LM_STATUS b44_MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, 400 PLM_VOID *pMemoryBlockVirt, PLM_PHYSICAL_ADDRESS pMemoryBlockPhy); 401LM_STATUS b44_MM_GetConfig(PLM_DEVICE_BLOCK pDevice); 402LM_STATUS b44_MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status); 403LM_STATUS b44_MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice); 404LM_STATUS b44_MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); 405#ifdef BCM_NAPI_RXPOLL 406LM_STATUS b44_MM_ScheduleRxPoll(PLM_DEVICE_BLOCK pDevice); 407#endif 408 409 410#endif /* B44LM_H */ 411 412