1/*
2 * BeOS Driver for Intel ICH AC'97 Link interface
3 *
4 * Copyright (c) 2002, Marcus Overhagen <marcus@overhagen.de>
5 *
6 * All rights reserved.
7 * Redistribution and use in source and binary forms, with or without modification,
8 * are permitted provided that the following conditions are met:
9 *
10 * - Redistributions of source code must retain the above copyright notice,
11 *   this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright notice,
13 *   this list of conditions and the following disclaimer in the documentation
14 *   and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
24 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
25 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 */
28#ifndef _HARDWARE_H_
29#define _HARDWARE_H_
30
31/* Native Audio Bus Master Control Registers */
32enum ICH_GLOBAL_REGISTER
33{
34	ICH_REG_GLOB_CNT	= 0x2C,
35	ICH_REG_GLOB_STA	= 0x30,
36	ICH_REG_ACC_SEMA	= 0x34,
37	ICH_REG_SDM			= 0x80
38};
39
40enum ICH_X_REGISTER_BASE /* base addresses for the following offsets */
41{
42	ICH_REG_PI_BASE		= 0x00,
43	ICH_REG_PO_BASE		= 0x10,
44	ICH_REG_MC_BASE		= 0x20
45};
46
47enum ICH_X_REGISTER_OFFSETS /* add base address to get the PI, PO or MC reg */
48{
49	ICH_REG_X_BDBAR		= 0x00,
50	ICH_REG_X_CIV		= 0x04,
51	ICH_REG_X_LVI		= 0x05,
52	_ICH_REG_X_SR		= 0x06, /* use GET_REG_X_SR()   macro from config.h */
53	_ICH_REG_X_PICB		= 0x08, /* use GET_REG_X_PICB() macro from config.h */
54	ICH_REG_X_PIV		= 0x0A,
55	ICH_REG_X_CR		= 0x0B
56};
57
58/* ICH_REG_X_SR (Status Register) Bits */
59enum REG_X_SR_BITS
60{
61	SR_DCH				= 0x0001,
62	SR_CELV				= 0x0002,
63	SR_LVBCI			= 0x0004,
64	SR_BCIS				= 0x0008,
65	SR_FIFOE			= 0x0010
66};
67
68/* ICH_REG_X_CR (Control Register) Bits */
69enum REG_X_CR_BITS
70{
71	CR_RPBM				= 0x01,
72	CR_RR				= 0x02,
73	CR_LVBIE			= 0x04,
74	CR_FEIE				= 0x08,
75	CR_IOCE				= 0x10
76};
77
78/* ICH_REG_GLOB_CNT (Global Control Register) Bits */
79enum REG_GLOB_CNT_BITS
80{
81	CNT_GIE				= 0x01,
82	CNT_COLD			= 0x02,
83	CNT_WARM			= 0x04,
84	CNT_SHUT			= 0x08,
85	CNT_PRIE			= 0x10,
86	CNT_SRIE			= 0x20
87};
88
89/* ICH_REG_GLOB_STA (Global Status Register) Bits */
90enum REG_GLOB_STA_BITS
91{
92	STA_GSCI			= 0x00000001, /* GPI Status Change Interrupt */
93	STA_MIINT			= 0x00000002, /* Modem In Interrupt */
94	STA_MOINT			= 0x00000004, /* Modem Out Interrupt */
95	STA_PIINT			= 0x00000020, /* PCM In Interrupt */
96	STA_POINT			= 0x00000040, /* PCM Out Interrupt */
97	STA_MINT			= 0x00000080, /* Mic In Interrupt */
98	STA_S0CR			= 0x00000100, /* AC_SDIN0 Codec Ready */
99	STA_S1CR			= 0x00000200, /* AC_SDIN1 Codec Ready */
100	STA_S0RI			= 0x00000400, /* AC_SDIN0 Resume Interrupt */
101	STA_S1RI			= 0x00000800, /* AC_SDIN1 Resume Interrupt */
102	STA_RCS				= 0x00008000, /* Read Completition Status */
103	STA_AD3				= 0x00010000,
104	STA_MD3				= 0x00020000,
105	STA_M2INT			= 0x01000000,	/* Microphone 2 In Interrupt */
106	STA_P2INT			= 0x02000000,	/* PCM In 2 Interrupt */
107	STA_SPINT			= 0x04000000,	/* S/PDIF Interrupt */
108	STA_BCS				= 0x08000000,	/* Bit Clock Stopped */
109	STA_S2CR			= 0x10000000,	/* AC_SDIN2 Codec Ready */
110	STA_S2RI			= 0x20000000,	/* AC_SDIN2 Resume Interrupt */
111	STA_INTMASK			= (STA_MIINT | STA_MOINT | STA_PIINT | STA_POINT | STA_MINT | STA_S0RI | STA_S1RI | STA_M2INT | STA_P2INT | STA_SPINT | STA_S2RI)
112};
113
114#define ICH_BD_COUNT	32
115/* The Hardware Buffer Descriptor */
116typedef struct {
117	volatile uint32 buffer;
118	volatile uint16 length;
119	volatile uint16 flags;
120	#define ICH_BDC_FLAG_IOC 0x8000
121} ich_bd;
122
123/* PCI Configuration Space */
124
125#define PCI_PCICMD		0x04
126#define PCI_PCICMD_IOS	0x01
127#define PCI_PCICMD_MSE	0x02
128#define PCI_PCICMD_BME	0x04
129
130#define PCI_CFG			0x41
131#define PCI_CFG_IOSE	0x01
132
133#define ICH4_MMBAR_SIZE	512
134#define ICH4_MBBAR_SIZE	256
135
136#endif
137