1/* 2 * auich BeOS Driver for Intel Southbridge audio 3 * 4 * Copyright (c) 2003, Jerome Duval (jerome.duval@free.fr) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 16 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#ifndef _DEV_PCI_AUICH_H_ 29#define _DEV_PCI_AUICH_H_ 30 31#include <Drivers.h> 32#include <SupportDefs.h> 33#include <OS.h> 34#include <PCI.h> 35#include "auichreg.h" 36#include "config.h" 37#include "queue.h" 38#include "hmulti_audio.h" 39#include "multi.h" 40 41#define INTEL_VENDOR_ID 0x8086 /* Intel */ 42#define INTEL_82443MX_AC97_DEVICE_ID 0x7195 43#define INTEL_82801AA_AC97_DEVICE_ID 0x2415 44#define INTEL_82801AB_AC97_DEVICE_ID 0x2425 45#define INTEL_82801BA_AC97_DEVICE_ID 0x2445 46#define INTEL_82801CA_AC97_DEVICE_ID 0x2485 47#define INTEL_82801DB_AC97_DEVICE_ID 0x24c5 48#define INTEL_82801EB_AC97_DEVICE_ID 0x24d5 49#define INTEL_82801FB_AC97_DEVICE_ID 0x266e 50#define INTEL_82801GB_AC97_DEVICE_ID 0x27de 51#define INTEL_6300ESB_AC97_DEVICE_ID 0x25a6 52#define SIS_VENDOR_ID 0x1039 /* Sis */ 53#define SIS_SI7012_AC97_DEVICE_ID 0x7012 54#define NVIDIA_VENDOR_ID 0x10de /* Nvidia */ 55#define NVIDIA_nForce_AC97_DEVICE_ID 0x01b1 56#define NVIDIA_nForce2_AC97_DEVICE_ID 0x006a 57#define NVIDIA_nForce2_400_AC97_DEVICE_ID 0x008a 58#define NVIDIA_nForce3_AC97_DEVICE_ID 0x00da 59#define NVIDIA_nForce3_250_AC97_DEVICE_ID 0x00ea 60#define NVIDIA_CK804_AC97_DEVICE_ID 0x0059 61#define NVIDIA_MCP51_AC97_DEVICE_ID 0x026b 62#define NVIDIA_MCP04_AC97_DEVICE_ID 0x003a 63#define AMD_VENDOR_ID 0x1022 /* Amd */ 64#define AMD_AMD8111_AC97_DEVICE_ID 0x764d 65#define AMD_AMD768_AC97_DEVICE_ID 0x7445 66 67#define VERSION "Version alpha 1, Copyright (c) 2003 Jérôme Duval, compiled on " ## __DATE__ ## " " ## __TIME__ 68#define DRIVER_NAME "auich" 69#define FRIENDLY_NAME "Auich" 70#define AUTHOR "Jérôme Duval" 71 72#define FRIENDLY_NAME_ICH "Auich ICH" 73#define FRIENDLY_NAME_SIS "Auich SiS" 74#define FRIENDLY_NAME_NVIDIA "Auich nVidia" 75#define FRIENDLY_NAME_AMD "Auich AMD" 76 77#define AUICH_DMALIST_MAX 32 78typedef struct _auich_dmalist { 79 uint32 base; 80 uint32 len; 81#define AUICH_DMAF_IOC 0x80000000 /* 1-int on complete */ 82#define AUICH_DMAF_BUP 0x40000000 /* 0-retrans last, 1-transmit 0 */ 83} auich_dmalist; 84 85#define AUICH_USE_PLAY (1 << 0) 86#define AUICH_USE_RECORD (1 << 1) 87#define AUICH_STATE_STARTED (1 << 0) 88 89/* 90 * auich memory managment 91 */ 92 93typedef struct _auich_mem { 94 LIST_ENTRY(_auich_mem) next; 95 void *log_base; 96 phys_addr_t phy_base; 97 area_id area; 98 size_t size; 99} auich_mem; 100 101/* 102 * Streams 103 */ 104 105typedef struct _auich_stream { 106 struct _auich_dev *card; 107 uint8 use; 108 uint8 state; 109 uint8 b16; 110 uint32 sample_rate; 111 uint8 channels; 112 uint32 bufframes; 113 uint8 bufcount; 114 115 uint32 base; 116 117 LIST_ENTRY(_auich_stream) next; 118 119 void (*inth) (void *); 120 void *inthparam; 121 122 void *dmaops_log_base; 123 phys_addr_t dmaops_phy_base; 124 area_id dmaops_area; 125 126 auich_mem *buffer; 127 uint16 blksize; /* in samples */ 128 uint16 trigblk; /* blk on which to trigger inth */ 129 uint16 blkmod; /* Modulo value to wrap trigblk */ 130 131 uint16 sta; /* GLOB_STA int bit */ 132 133 /* multi_audio */ 134 volatile int64 frames_count; // for play or record 135 volatile bigtime_t real_time; // for play or record 136 volatile int32 buffer_cycle; // for play or record 137 int32 first_channel; 138 bool update_needed; 139} auich_stream; 140 141/* 142 * Devices 143 */ 144 145typedef struct _auich_dev { 146 char name[DEVNAME]; /* used for resources */ 147 pci_info info; 148 device_config config; 149 150 void *ptb_log_base; 151 void *ptb_phy_base; 152 area_id ptb_area; 153 154 sem_id buffer_ready_sem; 155 156 uint32 interrupt_mask; 157 158 LIST_HEAD(, _auich_stream) streams; 159 160 LIST_HEAD(, _auich_mem) mems; 161 162 auich_stream *pstream; 163 auich_stream *rstream; 164 165 /* multi_audio */ 166 multi_dev multi; 167} auich_dev; 168 169 170#define AUICH_SETTINGS "auich.settings" 171 172typedef struct { 173 uint32 sample_rate; 174 uint32 buffer_frames; 175 int32 buffer_count; 176 bool use_thread; 177} auich_settings; 178 179extern auich_settings current_settings; 180 181extern int32 num_cards; 182extern auich_dev cards[NUM_CARDS]; 183 184status_t auich_stream_set_audioparms(auich_stream *stream, uint8 channels, 185 uint8 b16, uint32 sample_rate); 186status_t auich_stream_commit_parms(auich_stream *stream); 187status_t auich_stream_get_nth_buffer(auich_stream *stream, uint8 chan, uint8 buf, 188 char** buffer, size_t *stride); 189void auich_stream_start(auich_stream *stream, void (*inth) (void *), void *inthparam); 190void auich_stream_halt(auich_stream *stream); 191auich_stream *auich_stream_new(auich_dev *card, uint8 use, uint32 bufframes, uint8 bufcount); 192void auich_stream_delete(auich_stream *stream); 193 194#endif /* _DEV_PCI_AUICH_H_ */ 195