1/* 2 * Copyright 2005-2008, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Jan-Rixt Van Hoye 7 * Salvatore Benedetto <salvatore.benedetto@gmail.com> 8 * Michael Lotz <mmlr@mlotz.ch> 9 */ 10 11#ifndef OHCI_HARDWARE_H 12#define OHCI_HARDWARE_H 13 14// -------------------------------- 15// The OHCI registers 16// -------------------------------- 17 18// -------------------------------- 19// Revision register (section 7.1.1) 20// -------------------------------- 21 22#define OHCI_REVISION 0x00 23#define OHCI_REVISION_LOW(rev) ((rev) & 0x0f) 24#define OHCI_REVISION_HIGH(rev) (((rev) >> 4) & 0x03) 25#define OHCI_REVISION_LEGACY(rev) ((rev) & 0x10) 26 27// -------------------------------- 28// Control register (section 7.1.2) 29// -------------------------------- 30 31#define OHCI_CONTROL 0x04 32#define OHCI_CONTROL_BULK_SERVICE_RATIO_MASK 0x00000003 33#define OHCI_CONTROL_BULK_RATIO_1_1 0x00000000 34#define OHCI_CONTROL_BULK_RATIO_1_2 0x00000001 35#define OHCI_CONTROL_BULK_RATIO_1_3 0x00000002 36#define OHCI_CONTROL_BULK_RATIO_1_4 0x00000003 37#define OHCI_PERIODIC_LIST_ENABLE 0x00000004 38#define OHCI_ISOCHRONOUS_ENABLE 0x00000008 39#define OHCI_CONTROL_LIST_ENABLE 0x00000010 40#define OHCI_BULK_LIST_ENABLE 0x00000020 41#define OHCI_HC_FUNCTIONAL_STATE_MASK 0x000000c0 42#define OHCI_HC_FUNCTIONAL_STATE_RESET 0x00000000 43#define OHCI_HC_FUNCTIONAL_STATE_RESUME 0x00000040 44#define OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL 0x00000080 45#define OHCI_HC_FUNCTIONAL_STATE_SUSPEND 0x000000c0 46#define OHCI_INTERRUPT_ROUTING 0x00000100 47#define OHCI_REMOTE_WAKEUP_CONNECTED 0x00000200 48#define OHCI_REMORE_WAKEUP_ENABLED 0x00000400 49 50// -------------------------------- 51// Command status register (section 7.1.3) 52// -------------------------------- 53 54#define OHCI_COMMAND_STATUS 0x08 55#define OHCI_HOST_CONTROLLER_RESET 0x00000001 56#define OHCI_CONTROL_LIST_FILLED 0x00000002 57#define OHCI_BULK_LIST_FILLED 0x00000004 58#define OHCI_OWNERSHIP_CHANGE_REQUEST 0x00000008 59#define OHCI_SCHEDULING_OVERRUN_COUNT_MASK 0x00030000 60 61// -------------------------------- 62// Interrupt status register (section 7.1.4) 63// -------------------------------- 64 65#define OHCI_INTERRUPT_STATUS 0x0c 66#define OHCI_SCHEDULING_OVERRUN 0x00000001 67#define OHCI_WRITEBACK_DONE_HEAD 0x00000002 68#define OHCI_START_OF_FRAME 0x00000004 69#define OHCI_RESUME_DETECTED 0x00000008 70#define OHCI_UNRECOVERABLE_ERROR 0x00000010 71#define OHCI_FRAME_NUMBER_OVERFLOW 0x00000020 72#define OHCI_ROOT_HUB_STATUS_CHANGE 0x00000040 73#define OHCI_OWNERSHIP_CHANGE 0x40000000 74#define OHCI_MASTER_INTERRUPT_ENABLE 0x80000000 75 76// -------------------------------- 77// Interupt enable register (section 7.1.5) 78// -------------------------------- 79 80#define OHCI_INTERRUPT_ENABLE 0x10 81 82// -------------------------------- 83// Interupt disable register (section 7.1.6) 84// -------------------------------- 85 86#define OHCI_INTERRUPT_DISABLE 0x14 87 88// ------------------------------------- 89// Memory Pointer Partition (section 7.2) 90// ------------------------------------- 91 92// -------------------------------- 93// HCCA register (section 7.2.1) 94// -------------------------------- 95 96#define OHCI_HCCA 0x18 97 98// -------------------------------- 99// Period current ED register (section 7.2.2) 100// -------------------------------- 101 102#define OHCI_PERIOD_CURRENT_ED 0x1c 103 104// -------------------------------- 105// Control head ED register (section 7.2.3) 106// -------------------------------- 107 108#define OHCI_CONTROL_HEAD_ED 0x20 109 110// -------------------------------- 111// Current control ED register (section 7.2.4) 112// -------------------------------- 113 114#define OHCI_CONTROL_CURRENT_ED 0x24 115 116// -------------------------------- 117// Bulk head ED register (section 7.2.5) 118// -------------------------------- 119 120#define OHCI_BULK_HEAD_ED 0x28 121 122// -------------------------------- 123// Current bulk ED register (section 7.2.6) 124// -------------------------------- 125 126#define OHCI_BULK_CURRENT_ED 0x2c 127 128// -------------------------------- 129// Done head register (section 7.2.7) 130// -------------------------------- 131 132#define OHCI_DONE_HEAD 0x30 133 134// -------------------------------- 135// Frame Counter partition (section 7.3) 136// -------------------------------- 137 138// -------------------------------- 139// Frame interval register (section 7.3.1) 140// -------------------------------- 141 142#define OHCI_FRAME_INTERVAL 0x34 143#define OHCI_GET_INTERVAL_VALUE(s) ((s) & 0x3fff) 144#define OHCI_GET_FS_LARGEST_DATA_PACKET(s) (((s) >> 16) & 0x7fff) 145#define OHCI_FRAME_INTERVAL_TOGGLE 0x80000000 146 147// -------------------------------- 148// Frame remaining register (section 7.3.2) 149// -------------------------------- 150 151#define OHCI_FRAME_REMAINING 0x38 152 153// -------------------------------- 154// Frame number register (section 7.3.3) 155// -------------------------------- 156 157#define OHCI_FRAME_NUMBER 0x3c 158 159// -------------------------------- 160// Periodic start register (section 7.3.4) 161// -------------------------------- 162 163#define OHCI_PERIODIC_START 0x40 164 165// -------------------------------- 166// Low Speed (LS) treshold register (section 7.3.5) 167// -------------------------------- 168 169#define OHCI_LOW_SPEED_THRESHOLD 0x44 170 171// -------------------------------- 172// Root Hub Partition (section 7.4) 173// -------------------------------- 174 175// -------------------------------- 176// Root Hub Descriptor A register (section 7.4.1) 177// -------------------------------- 178 179#define OHCI_RH_DESCRIPTOR_A 0x48 180#define OHCI_RH_GET_PORT_COUNT(s) ((s) & 0xff) 181#define OHCI_RH_POWER_SWITCHING_MODE 0x0100 182#define OHCI_RH_NO_POWER_SWITCHING 0x0200 183#define OHCI_RH_DEVICE_TYPE 0x0400 184#define OHCI_RH_OVER_CURRENT_PROTECTION_MODE 0x0800 185#define OHCI_RH_NO_OVER_CURRENT_PROTECTION 0x1000 186#define OHCI_RH_GET_POWER_ON_TO_POWER_GOOD_TIME(s) ((s) >> 24) 187 188// -------------------------------- 189// Root Hub Descriptor B register (section 7.4.2) 190// -------------------------------- 191 192#define OHCI_RH_DESCRIPTOR_B 0x4c 193 194// -------------------------------- 195// Root Hub status register (section 7.4.3) 196// -------------------------------- 197 198#define OHCI_RH_STATUS 0x50 199#define OHCI_RH_LOCAL_POWER_STATUS 0x00000001 200#define OHCI_RH_OVER_CURRENT_INDICATOR 0x00000002 201#define OHCI_RH_DEVICE_REMOTE_WAKEUP_ENABLE 0x00008000 202#define OHCI_RH_LOCAL_POWER_STATUS_CHANGE 0x00010000 203#define OHCI_RH_OVER_CURRENT_INDICATOR_CHANGE 0x00020000 204#define OHCI_RH_CLEAR_REMOTE_WAKEUP_ENABLE 0x80000000 205 206// -------------------------------- 207// Root Hub port status (n) register (section 7.4.4) 208// -------------------------------- 209 210#define OHCI_RH_PORT_STATUS(n) (0x54 + (n) * 4)// 0 based indexing 211#define OHCI_RH_PORTSTATUS_CCS 0x00000001 // Current Connection Status 212#define OHCI_RH_PORTSTATUS_PES 0x00000002 // Port Enable Status 213#define OHCI_RH_PORTSTATUS_PSS 0x00000004 // Port Suspend Status 214#define OHCI_RH_PORTSTATUS_POCI 0x00000008 // Port Overcurrent Indicator 215#define OHCI_RH_PORTSTATUS_PRS 0x00000010 // Port Reset Status 216#define OHCI_RH_PORTSTATUS_PPS 0x00000100 // Port Power Status 217#define OHCI_RH_PORTSTATUS_LSDA 0x00000200 // Low Speed Device Attached 218#define OHCI_RH_PORTSTATUS_CSC 0x00010000 // Connection Status Change 219#define OHCI_RH_PORTSTATUS_PESC 0x00020000 // Port Enable Status Change 220#define OHCI_RH_PORTSTATUS_PSSC 0x00040000 // Port Suspend Status change 221#define OHCI_RH_PORTSTATUS_OCIC 0x00080000 // Port Overcurrent Change 222#define OHCI_RH_PORTSTATUS_PRSC 0x00100000 // Port Reset Status Change 223 224// -------------------------------- 225// Enable List 226// -------------------------------- 227 228#define OHCI_ENABLE_LIST (OHCI_PERIODIC_LIST_ENABLE \ 229 | OHCI_ISOCHRONOUS_ENABLE \ 230 | OHCI_CONTROL_LIST_ENABLE \ 231 | OHCI_BULK_LIST_ENABLE) 232 233// -------------------------------- 234// All interupts 235// -------------------------------- 236 237#define OHCI_ALL_INTERRUPTS (OHCI_SCHEDULING_OVERRUN \ 238 | OHCI_WRITEBACK_DONE_HEAD \ 239 | OHCI_START_OF_FRAME \ 240 | OHCI_RESUME_DETECTED \ 241 | OHCI_UNRECOVERABLE_ERROR \ 242 | OHCI_FRAME_NUMBER_OVERFLOW \ 243 | OHCI_ROOT_HUB_STATUS_CHANGE \ 244 | OHCI_OWNERSHIP_CHANGE) 245 246// -------------------------------- 247// All normal interupts 248// -------------------------------- 249 250#define OHCI_NORMAL_INTERRUPTS (OHCI_SCHEDULING_OVERRUN \ 251 | OHCI_WRITEBACK_DONE_HEAD \ 252 | OHCI_RESUME_DETECTED \ 253 | OHCI_UNRECOVERABLE_ERROR \ 254 | OHCI_ROOT_HUB_STATUS_CHANGE) 255 256// -------------------------------- 257// FSMPS 258// -------------------------------- 259 260#define OHCI_FSMPS(i) (((i - 210) * 6 / 7) << 16) 261 262// -------------------------------- 263// Periodic 264// -------------------------------- 265 266#define OHCI_PERIODIC(i) ((i) * 9 / 10) 267 268// -------------------------------- 269// HCCA structure (section 4.4) 270// 256 bytes aligned 271// -------------------------------- 272 273#define OHCI_NUMBER_OF_INTERRUPTS 32 274#define OHCI_STATIC_ENDPOINT_COUNT 6 275#define OHCI_BIGGEST_INTERVAL 32 276 277typedef struct { 278 uint32 interrupt_table[OHCI_NUMBER_OF_INTERRUPTS]; 279 uint32 current_frame_number; 280 uint32 done_head; 281 // The following is 120 instead of 116 because the spec 282 // only specifies 252 bytes 283 uint8 reserved_for_hc[120]; 284} ohci_hcca; 285 286#define OHCI_DONE_INTERRUPTS 1 287#define OHCI_HCCA_SIZE 256 288#define OHCI_HCCA_ALIGN 256 289#define OHCI_PAGE_SIZE 0x1000 290#define OHCI_PAGE(x) ((x) &~ 0xfff) 291#define OHCI_PAGE_OFFSET(x) ((x) & 0xfff) 292 293// -------------------------------- 294// Endpoint descriptor structure (section 4.2) 295// -------------------------------- 296 297typedef struct { 298 // Hardware part 299 uint32 flags; // Flags field 300 uint32 tail_physical_descriptor; // Queue tail physical pointer 301 uint32 head_physical_descriptor; // Queue head physical pointer 302 uint32 next_physical_endpoint; // Physical pointer to the next endpoint 303 // Software part 304 uint32 physical_address; // Physical pointer to this address 305 void *tail_logical_descriptor; // Queue tail logical pointer 306 void *next_logical_endpoint; // Logical pointer to the next endpoint 307 mutex *lock; // Protects tail changes and checks 308} ohci_endpoint_descriptor; 309 310#define OHCI_ENDPOINT_ADDRESS_MASK 0x0000007f 311#define OHCI_ENDPOINT_GET_DEVICE_ADDRESS(s) ((s) & 0x7f) 312#define OHCI_ENDPOINT_SET_DEVICE_ADDRESS(s) (s) 313#define OHCI_ENDPOINT_GET_ENDPOINT_NUMBER(s) (((s) >> 7) & 0xf) 314#define OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(s) ((s) << 7) 315#define OHCI_ENDPOINT_DIRECTION_MASK 0x00001800 316#define OHCI_ENDPOINT_DIRECTION_DESCRIPTOR 0x00000000 317#define OHCI_ENDPOINT_DIRECTION_OUT 0x00000800 318#define OHCI_ENDPOINT_DIRECTION_IN 0x00001000 319#define OHCI_ENDPOINT_LOW_SPEED 0x00002000 320#define OHCI_ENDPOINT_FULL_SPEED 0x00000000 321#define OHCI_ENDPOINT_SKIP 0x00004000 322#define OHCI_ENDPOINT_GENERAL_FORMAT 0x00000000 323#define OHCI_ENDPOINT_ISOCHRONOUS_FORMAT 0x00008000 324#define OHCI_ENDPOINT_MAX_PACKET_SIZE_MASK (0x7ff << 16) 325#define OHCI_ENDPOINT_GET_MAX_PACKET_SIZE(s) (((s) >> 16) & 0x07ff) 326#define OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(s) ((s) << 16) 327#define OHCI_ENDPOINT_HALTED 0x00000001 328#define OHCI_ENDPOINT_TOGGLE_CARRY 0x00000002 329#define OHCI_ENDPOINT_HEAD_MASK 0xfffffffc 330 331 332// -------------------------------- 333// General transfer descriptor structure (section 4.3.1) 334// -------------------------------- 335 336typedef struct { 337 // Hardware part 16 bytes 338 uint32 flags; // Flags field 339 uint32 buffer_physical; // Physical buffer pointer 340 uint32 next_physical_descriptor; // Physical pointer next descriptor 341 uint32 last_physical_byte_address; // Physical pointer to buffer end 342 // Software part 343 uint32 physical_address; // Physical address of this descriptor 344 size_t buffer_size; // Size of the buffer 345 void *buffer_logical; // Logical pointer to the buffer 346 void *next_logical_descriptor; // Logical pointer next descriptor 347} ohci_general_td; 348 349#define OHCI_TD_BUFFER_ROUNDING 0x00040000 350#define OHCI_TD_DIRECTION_PID_MASK 0x00180000 351#define OHCI_TD_DIRECTION_PID_SETUP 0x00000000 352#define OHCI_TD_DIRECTION_PID_OUT 0x00080000 353#define OHCI_TD_DIRECTION_PID_IN 0x00100000 354#define OHCI_TD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7) 355#define OHCI_TD_SET_DELAY_INTERRUPT(x) ((x) << 21) 356#define OHCI_TD_INTERRUPT_MASK 0x00e00000 357#define OHCI_TD_TOGGLE_CARRY 0x00000000 358#define OHCI_TD_TOGGLE_0 0x02000000 359#define OHCI_TD_TOGGLE_1 0x03000000 360#define OHCI_TD_TOGGLE_MASK 0x03000000 361#define OHCI_TD_GET_ERROR_COUNT(x) (((x) >> 26) & 3) 362#define OHCI_TD_GET_CONDITION_CODE(x) ((x) >> 28) 363#define OHCI_TD_SET_CONDITION_CODE(x) ((x) << 28) 364#define OHCI_TD_CONDITION_CODE_MASK 0xf0000000 365 366#define OHCI_TD_INTERRUPT_IMMEDIATE 0x00 367#define OHCI_TD_INTERRUPT_NONE 0x07 368 369#define OHCI_TD_CONDITION_NO_ERROR 0x00 370#define OHCI_TD_CONDITION_CRC_ERROR 0x01 371#define OHCI_TD_CONDITION_BIT_STUFFING 0x02 372#define OHCI_TD_CONDITION_TOGGLE_MISMATCH 0x03 373#define OHCI_TD_CONDITION_STALL 0x04 374#define OHCI_TD_CONDITION_NO_RESPONSE 0x05 375#define OHCI_TD_CONDITION_PID_CHECK_FAILURE 0x06 376#define OHCI_TD_CONDITION_UNEXPECTED_PID 0x07 377#define OHCI_TD_CONDITION_DATA_OVERRUN 0x08 378#define OHCI_TD_CONDITION_DATA_UNDERRUN 0x09 379#define OHCI_TD_CONDITION_BUFFER_OVERRUN 0x0c 380#define OHCI_TD_CONDITION_BUFFER_UNDERRUN 0x0d 381#define OHCI_TD_CONDITION_NOT_ACCESSED 0x0f 382 383#define OHCI_GENERAL_TD_ALIGN 16 384 385// -------------------------------- 386// Isochronous transfer descriptor structure (section 4.3.2) 387// -------------------------------- 388 389#define OHCI_ITD_NOFFSET 8 390typedef struct { 391 // Hardware part 32 byte 392 uint32 flags; 393 uint32 buffer_page_byte_0; // Physical page number of byte 0 394 uint32 next_physical_descriptor; // Next isochronous transfer descriptor 395 uint32 last_byte_address; // Physical buffer end 396 uint16 offset[OHCI_ITD_NOFFSET]; // Buffer offsets 397 // Software part 398 uint32 physical_address; // Physical address of this descriptor 399 void *next_logical_descriptor; // Logical pointer next descriptor 400 void *next_done_descriptor; // Used for collision in the hash table 401} ohci_isochronous_td; 402 403#define OHCI_ITD_GET_STARTING_FRAME(x) ((x) & 0x0000ffff) 404#define OHCI_ITD_SET_STARTING_FRAME(x) ((x) & 0xffff) 405#define OHCI_ITD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7) 406#define OHCI_ITD_SET_DELAY_INTERRUPT(x) ((x) << 21) 407#define OHCI_ITD_NO_INTERRUPT 0x00e00000 408#define OHCI_ITD_GET_FRAME_COUNT(x) ((((x) >> 24) & 7) + 1) 409#define OHCI_ITD_SET_FRAME_COUNT(x) (((x) - 1) << 24) 410#define OHCI_ITD_GET_CONDITION_CODE(x) ((x) >> 28) 411#define OHCI_ITD_NO_CONDITION_CODE 0xf0000000 412 413// TO FIX 414#define itd_pswn itd_offset // Packet Status Word 415#define OHCI_ITD_PAGE_SELECT 0x00001000 416#define OHCI_ITD_MK_OFFS(len) (0xe000 | ((len) & 0x1fff)) 417#define OHCI_ITD_GET_BUFFER_LENGTH(x) ((x) & 0xfff) 418#define OHCI_ITD_GET_BUFFER_CONDITION_CODE(x) ((x) >> 12) 419 420#define OHCI_ISOCHRONOUS_TD_ALIGN 32 421 422// -------------------------------- 423// Completion Codes (section 4.3.3) 424// -------------------------------- 425 426#define OHCI_NO_ERROR 0 427#define OHCI_CRC 1 428#define OHCI_BIT_STUFFING 2 429#define OHCI_DATA_TOGGLE_MISMATCH 3 430#define OHCI_STALL 4 431#define OHCI_DEVICE_NOT_RESPONDING 5 432#define OHCI_PID_CHECK_FAILURE 6 433#define OHCI_UNEXPECTED_PID 7 434#define OHCI_DATA_OVERRUN 8 435#define OHCI_DATA_UNDERRUN 9 436#define OHCI_BUFFER_OVERRUN 12 437#define OHCI_BUFFER_UNDERRUN 13 438#define OHCI_NOT_ACCESSED 15 439 440// -------------------------------- 441// Some delay needed when changing 442// certain registers. 443// -------------------------------- 444 445#define OHCI_ENABLE_POWER_DELAY 5000 446#define OHCI_READ_DESC_DELAY 5000 447 448// Maximum port count set by OHCI 449#define OHCI_MAX_PORT_COUNT 15 450 451#endif // OHCI_HARDWARE_H 452