1/* 2** $Id: buslogic.h,v 1.2 1998/04/21 00:51:57 swetland Exp $ 3** 4** Constants and Structures for BusLogic MultiMaster Controllers 5** Copyright 1998, Brian J. Swetland <swetland@frotz.net> 6** 7** This file may be used under the terms of the Be Sample Code License. 8*/ 9 10#define PCI_VENDOR_BUSLOGIC 0x104b 11#define PCI_DEVICE_MULTIMASTER 0x1040 12 13 14/* BusLogic MultiMaster Register Definitions 15** cf. Technical Reference Manual, pp. 1-10 - 1-17 16*/ 17#define BL_CONTROL_REG (bl->iobase) 18#define BL_CONTROL_RHARD 0x80 /* Controller Hard Reset */ 19#define BL_CONTROL_RSOFT 0x40 /* Controller Soft Reset */ 20#define BL_CONTROL_RINT 0x20 /* Reset (Acknowledge) Interrupts */ 21#define BL_CONTROL_RSBUS 0x10 /* Reset SCSI Bus */ 22 23#define BL_STATUS_REG (bl->iobase) 24#define BL_STATUS_DACT 0x80 /* Diagnostic Active */ 25#define BL_STATUS_DFAIL 0x40 /* Diagnostic Failure */ 26#define BL_STATUS_INREQ 0x20 /* Initialization Required */ 27#define BL_STATUS_HARDY 0x10 /* Host Adapter Ready */ 28#define BL_STATUS_CPRBSY 0x08 /* Command/Param Out Register Busy */ 29#define BL_STATUS_DIRRDY 0x04 /* Data In Register Ready */ 30#define BL_STATUS_CMDINV 0x01 /* Command Invalid */ 31 32#define BL_COMMAND_REG (bl->iobase + 1) 33#define BL_DATA_REG (bl->iobase + 1) 34 35#define BL_INT_REG (bl->iobase + 2) 36#define BL_INT_INTV 0x80 /* Interrupt Valid */ 37#define BL_INT_RSTS 0x08 /* SCSI Reset State */ 38#define BL_INT_CMDC 0x04 /* Command Complete */ 39#define BL_INT_MBOR 0x02 /* Mailbox Out Ready */ 40#define BL_INT_IMBL 0x01 /* Incoming Mailbox Loaded */ 41 42 43#define MAX_SCATTER 130 44 45typedef struct _bl_ccb32 46{ 47 /* buslogic ccb structure */ 48 uchar opcode; /* operation code - see CCB_OP_* below */ 49 uchar direction; /* data direction control - see CCB_DIR_* */ 50 uchar length_cdb; /* length of the cdb */ 51 uchar length_sense; /* length of sense data block */ 52 uint32 length_data; /* length of data block */ 53 uint32 data; /* 32bit physical pointer to data or s/g table */ 54 uchar _reserved1; /* set to zero */ 55 uchar _reserved2; /* set to zero */ 56 uchar btstat; /* Host Adapter Status Return */ 57 uchar sdstat; /* SCSI Device Status Return */ 58 uchar target_id; /* Target SCSI ID */ 59 uchar lun_tag; /* bits 0-2 = LUN, | with CCB_TAG_* */ 60 uchar cdb[12]; /* SCSI CDB area */ 61 uchar ccb_control; /* controle bits - see CCB_CONTROL_* */ 62 uchar link_id; /* id number for linked CCB's */ 63 uint32 link; /* 32bit physical pointer to a linked CCB */ 64 uint32 sense; /* 32bit physical pointer to the sense datablk */ 65 66 /* used by the driver */ 67 68 sem_id done; /* used by ISR for completion notification */ 69 int completion_code; /* completion code storage from mailbox */ 70 struct _bl_ccb32 *next; /* chain pointer for CCB32 freelist */ 71 uint _reserved[3]; /* padding */ 72} BL_CCB32; 73 74typedef struct 75{ 76 /* used by the driver */ 77 uchar sensedata[256]; /* data area for sense data return */ 78 79 struct { 80 uint length; /* length of this SG segment (bytes) */ 81 uint phys; /* physical address of this SG segment */ 82 } sg[MAX_SCATTER]; /* scatter/gather table */ 83} BL_PRIV; 84 85#define BL_CCB_TAG_SIMPLE 0x20 86#define BL_CCB_TAG_HEAD 0x60 87#define BL_CCB_TAG_ORDERED 0xA0 88 89#define BL_CCB_OP_INITIATE 0x00 90#define BL_CCB_OP_INITIATE_SG 0x02 91 92/* returns dif between req/actual xmit bytecount */ 93#define BL_CCB_OP_INITIATE_RETLEN 0x03 94#define BL_CCB_OP_INITIATE_RETLEN_SG 0x04 95#define BL_CCB_OP_SCSI_BUS_RESET 0x81 96 97#define BL_CCB_DIR_DEFAULT 0x00 /* transfer in direction native to scsi */ 98#define BL_CCB_DIR_INBOUND 0x08 99#define BL_CCB_DIR_OUTBOUND 0x10 100#define BL_CCB_DIR_NO_XFER 0x18 101 102typedef struct 103{ 104 uint32 ccb_phys; 105 uchar _reserved1; 106 uchar _reserved2; 107 uchar _reserved3; 108 uchar action_code; 109} BL_Out_Mailbox32; 110 111#define BL_ActionCode_NotInUse 0x00 112#define BL_ActionCode_Start 0x01 113#define BL_ActionCode_Abort 0x02 114 115 116 117typedef struct 118{ 119 uint32 ccb_phys; 120 uchar btstat; 121 uchar sdstat; 122 uchar _reserved1; 123 uchar completion_code; 124} BL_In_Mailbox32; 125 126#define BL_CompletionCode_NotInUse 0x00 127#define BL_CompletionCode_NoError 0x01 128#define BL_CompletionCode_HostAbort 0x02 129#define BL_CompletionCode_NotFound 0x03 130#define BL_CompletionCode_Error 0x04 131 132#define MAX_CCB_COUNT 32 133 134/* Host Adapter State Structure 135** 136*/ 137typedef struct 138{ 139 int id; /* board id 0, 1, ... */ 140 int done; /* command complete from ISR */ 141 int irq; /* board's irq */ 142 int iobase; /* base io address */ 143 int scsi_id; /* board's SCSI id */ 144 int wide; /* wide target id's allowed */ 145 long reqid; /* request counter for debugging */ 146 147 char productname[16]; 148 149 uint32 phys_to_virt; /* adjustment for mapping BL_CCB32's */ 150 uint32 virt_to_phys; /* between virt and phys addrs */ 151 152 uint32 phys_mailboxes; /* phys addr of mailboxes */ 153 154 sem_id hw_lock; /* lock for hardware and outbox access */ 155 sem_id ccb_lock; /* lock protecting the ccb chain */ 156 sem_id ccb_count; /* counting sem protecting the ccb chain */ 157 158 int box_count; 159 int out_nextbox; 160 int in_nextbox; 161 BL_Out_Mailbox32 *out_boxes; 162 BL_In_Mailbox32 *in_boxes; 163 164 BL_CCB32 *ccb; /* table of MAX_CCB_COUNT CCB's */ 165 BL_CCB32 *first_ccb; /* head of ccb freelist */ 166} BusLogic; 167 168