1
2Copyright (C) 1999-2002 VMware, Inc.
3All Rights Reserved
4
5The code here may be used/distributed under the terms of the standard
6XFree86 license.
7
8
9 VMware SVGA Device Interface and Programming Model
10 --------------------------------------------------
11
12
13Include Files
14-------------
15
16svga_reg.h
17 SVGA register definitions, SVGA capabilities, and FIFO command definitions.
18
19svga_limits.h
20 Included by svga_reg.h, defines maximum frame buffer and memory region
21 sizes.
22
23guest_os.h
24 Values for the GUEST_ID register.
25
26vm_basic_types.h
27 Common type definitions.
28
29vm_device_version.h
30 PCI vendor ID's and related information.
31
32
33Programming the VMware SVGA Device
34----------------------------------
35
361. Reading/writing a register:
37
38 The SVGA registers are addressed by an index/value pair of 32 bit
39 registers in the IO address space.
40
41 The 0710 VMware SVGA chipset (PCI device ID PCI_DEVICE_ID_VMWARE_SVGA) has
42 its index and value ports hardcoded at:
43
44 index: SVGA_LEGACY_BASE_PORT + 4 * SVGA_INDEX_PORT
45 value: SVGA_LEGACY_BASE_PORT + 4 * SVGA_VALUE_PORT
46
47 The 0405 VMware SVGA chipset (PCI device ID PCI_DEVICE_ID_VMWARE_SVGA2)
48 determines its index and value ports as a function of the first base
49 address register in its PCI configuration space as:
50
51 index: <Base Address Register 0> + SVGA_INDEX_PORT
52 value: <Base Address Register 0> + SVGA_VALUE_PORT
53
54 To read a register:
55 Set the index port to the index of the register, using a dword OUT
56 Do a dword IN from the value port
57
58 To write a register:
59 Set the index port to the index of the register, using a dword OUT
60 Do a dword OUT to the value port
61
62 Example, setting the width to 1024:
63
64 mov eax, SVGA_REG_WIDTH
65 mov edx, <SVGA Address Port>
66 out dx, eax
67 mov eax, 1024
68 mov edx, <SVGA Value Port>
69 out dx, eax
70
712. Initialization
72 Check the version number
73 loop:
74 Write into SVGA_REG_ID the maximum SVGA_ID_* the driver supports.
75 Read from SVGA_REG_ID.
76 Check if it is the value you wrote.
77 If yes, VMware SVGA device supports it
78 If no, decrement SVGA_ID_* and goto loop
79 This algorithm converges.
80
81 Map the frame buffer and the command FIFO
82 Read SVGA_REG_FB_START, SVGA_REG_FB_SIZE, SVGA_REG_MEM_START,
83 SVGA_REG_MEM_SIZE.
84 Map the frame buffer (FB) and the FIFO memory (MEM)
85
86 Get the device capabilities and frame buffer dimensions
87 Read SVGA_REG_CAPABILITIES, SVGA_REG_MAX_WIDTH, SVGA_REG_MAX_HEIGHT,
88 and SVGA_REG_HOST_BITS_PER_PIXEL / SVGA_REG_BITS_PER_PIXEL.
89
90 Note: The capabilities can and do change without the PCI device ID
91 changing or the SVGA_REG_ID changing. A driver should always check
92 the capabilities register when loading before expecting any
93 capabilities-determined feature to be available. See below for a list
94 of capabilities as of this writing.
95
96 Note: If SVGA_CAP_8BIT_EMULATION is not set, then it is possible that
97 SVGA_REG_HOST_BITS_PER_PIXEL does not exist and
98 SVGA_REG_BITS_PER_PIXEL should be read instead.
99
100 Report the Guest Operating System
101 Write SVGA_REG_GUEST_ID with the appropriate value from <guest_os.h>.
102 While not required in any way, this is useful information for the
103 virtual machine to have available for reporting and sanity checking
104 purposes.
105
106 SetMode
107 Set SVGA_REG_WIDTH, SVGA_REG_HEIGHT, SVGA_REG_BITS_PER_PIXEL
108 Read SVGA_REG_FB_OFFSET
109 (SVGA_REG_FB_OFFSET is the offset from SVGA_REG_FB_START of the
110 visible portion of the frame buffer)
111 Read SVGA_REG_BYTES_PER_LINE, SVGA_REG_DEPTH, SVGA_REG_PSEUDOCOLOR,
112 SVGA_REG_RED_MASK, SVGA_REG_GREEN_MASK, SVGA_REG_BLUE_MASK
113
114 Note: SVGA_REG_BITS_PER_PIXEL is readonly if
115 SVGA_CAP_8BIT_EMULATION is not set in the capabilities register. Even
116 if it is set, values other than 8 and SVGA_REG_HOST_BITS_PER_PIXEL
117 will be ignored.
118
119 Enable SVGA
120 Set SVGA_REG_ENABLE to 1
121 (to disable SVGA, set SVGA_REG_ENABLE to 0. Setting SVGA_REG_ENABLE
122 to 0 also enables VGA.)
123
124 Initialize the command FIFO
125 The FIFO is exclusively dword (32-bit) aligned. The first four
126 dwords define the portion of the MEM area that is used for the
127 command FIFO. These are values are all in byte offsets from the
128 start of the MEM area.
129
130 A minimum sized FIFO would have these values:
131 mem[SVGA_FIFO_MIN] = 16;
132 mem[SVGA_FIFO_MAX] = 16 + (10 * 1024);
133 mem[SVGA_FIFO_NEXT_CMD] = 16;
134 mem[SVGA_FIFO_STOP] = 16;
135
136 Set SVGA_REG_CONFIG_DONE to 1 after these values have been set.
137
138 Note: Setting SVGA_REG_CONFIG_DONE to 0 will stop the device from
139 reading the FIFO until it is reinitialized and SVGA_REG_CONFIG_DONE is
140 set to 1 again.
141
1423. SVGA command FIFO protocol
143 The FIFO is empty when SVGA_FIFO_NEXT_CMD == SVGA_FIFO_STOP. The
144 driver writes commands to the FIFO starting at the offset specified
145 by SVGA_FIFO_NEXT_CMD, and then increments SVGA_FIFO_NEXT_CMD.
146
147 The FIFO is full when SVGA_FIFO_NEXT_CMD is one word before SVGA_FIFO_STOP.
148
149 When the FIFO becomes full, the FIFO should be sync'd
150
151 To sync the FIFO
152 Write SVGA_REG_SYNC
153 Read SVGA_REG_BUSY
154 Wait for the value in SVGA_REG_BUSY to be 0
155
156 The FIFO should be sync'd before the driver touches the frame buffer, to
157 guarantee that any outstanding BLT's are completed.
158
1594. Cursor
160 When SVGA_CAP_CURSOR is set, hardware cursor support is available. In
161 practice, SVGA_CAP_CURSOR will only be set when SVGA_CAP_CURSOR_BYPASS is
162 also set and drivers supporting a hardware cursor should only worry about
163 SVGA_CAP_CURSOR_BYPASS and only use the FIFO to define the cursor. See
164 below for more information.
165
1665. Pseudocolor
167 When the read-only register SVGA_REG_PSEUDOCOLOR is 1, the device is in a
168 colormapped mode whose index width and color width are both SVGA_REG_DEPTH.
169 Thus far, 8 is the only depth at which pseudocolor is ever used.
170
171 In pseudocolor, the colormap is programmed by writing to the SVGA palette
172 registers. These start at SVGA_PALETTE_BASE and are interpreted as
173 follows:
174
175 SVGA_PALETTE_BASE + 3*n - The nth red component
176 SVGA_PALETTE_BASE + 3*n + 1 - The nth green component
177 SVGA_PALETTE_BASE + 3*n + 2 - The nth blue component
178
179 And n ranges from 0 to ((1<<SVGA_REG_DEPTH) - 1).
180
181
182Drawing to the Screen
183---------------------
184
185After initialization, the driver can write directly to the frame buffer. The
186updated frame buffer is not displayed immediately, but only when an update
187command is sent. The update command (SVGA_CMD_UPDATE) defines the rectangle
188in the frame buffer that has been modified by the driver, and causes that
189rectangle to be updated on the screen.
190
191A complete driver can be developed this way. For increased performance,
192additional commands are available to accelerate common operations. The two
193most useful are SVGA_CMD_RECT_FILL and SVGA_CMD_RECT_COPY.
194
195After issuing an accelerated command, the FIFO should be sync'd, as described
196above, before writing to the frame buffer.
197
198Addendum on 7/11/2000
199---------------------
200
201SVGA_REG_FB_OFFSET and SVGA_REG_BYTES_PER_LINE may change after SVGA_REG_WIDTH
202or SVGA_REG_HEIGHT is set. Also the VGA registers must be written to after
203setting SVGA_REG_ENABLE to 0 to change the display to a VGA mode.
204
205Addendum on 11/29/2001
206---------------------
207
208Actually, after changing any of SVGA_REG_WIDTH, SVGA_REG_HEIGHT, and
209SVGA_REG_BITS_PER_PIXEL, all of the registers listed in the 'SetMode'
210initialization section above should be reread. Additionally, when changing
211modes, it can be convenient to set SVGA_REG_ENABLE to 0, change
212SVGA_REG_WIDTH, SVGA_REG_HEIGHT, and SVGA_REG_BITS_PER_PIXEL (if available),
213and then set SVGA_REG_ENABLE to 1 again.
214
215
216Capabilities
217------------
218
219The capabilities register (SVGA_REG_CAPABILITIES) is an array of bits that
220indicates the capabilities of the SVGA emulation. A driver should check
221SVGA_REG_CAPABILITIES every time it loads before relying on any feature that
222is only optionally available.
223
224Some of the capabilities determine which FIFO commands are available. This
225table shows which capability indicates support for which command.
226
227 FIFO Command Capability
228 ------------ ----------
229
230 SVGA_CMD_RECT_FILL SVGA_CAP_RECT_FILL
231 SVGA_CMD_RECT_COPY SVGA_CAP_RECT_COPY
232 SVGA_CMD_DEFINE_BITMAP SVGA_CAP_OFFSCREEN
233 SVGA_CMD_DEFINE_BITMAP_SCANLINE SVGA_CAP_OFFSCREEN
234 SVGA_CMD_DEFINE_PIXMAP SVGA_CAP_OFFSCREEN
235 SVGA_CMD_DEFINE_PIXMAP_SCANLINE SVGA_CAP_OFFSCREEN
236 SVGA_CMD_RECT_BITMAP_FILL SVGA_CAP_RECT_PAT_FILL
237 SVGA_CMD_RECT_PIXMAP_FILL SVGA_CAP_RECT_PAT_FILL
238 SVGA_CMD_RECT_BITMAP_COPY SVGA_CAP_RECT_PAT_FILL
239 SVGA_CMD_RECT_PIXMAP_COPY SVGA_CAP_RECT_PAT_FILL
240 SVGA_CMD_FREE_OBJECT SVGA_CAP_OFFSCREEN
241 SVGA_CMD_RECT_ROP_FILL SVGA_CAP_RECT_FILL +
242 SVGA_CAP_RASTER_OP
243 SVGA_CMD_RECT_ROP_COPY SVGA_CAP_RECT_COPY +
244 SVGA_CAP_RASTER_OP
245 SVGA_CMD_RECT_ROP_BITMAP_FILL SVGA_CAP_RECT_PAT_FILL +
246 SVGA_CAP_RASTER_OP
247 SVGA_CMD_RECT_ROP_PIXMAP_FILL SVGA_CAP_RECT_PAT_FILL +
248 SVGA_CAP_RASTER_OP
249 SVGA_CMD_RECT_ROP_BITMAP_COPY SVGA_CAP_RECT_PAT_FILL +
250 SVGA_CAP_RASTER_OP
251 SVGA_CMD_RECT_ROP_PIXMAP_COPY SVGA_CAP_RECT_PAT_FILL +
252 SVGA_CAP_RASTER_OP
253 SVGA_CMD_DEFINE_CURSOR SVGA_CAP_CURSOR
254 SVGA_CMD_DISPLAY_CURSOR SVGA_CAP_CURSOR
255 SVGA_CMD_MOVE_CURSOR SVGA_CAP_CURSOR
256 SVGA_CMD_DEFINE_ALPHA_CURSOR SVGA_CAP_ALPHA_CURSOR
257 SVGA_CMD_DRAW_GLYPH SVGA_CAP_GLYPH
258 SVGA_CMD_DRAW_GLYPH_CLIPPED SVGA_CAP_GLYPH_CLIPPING
259
260Note: SVGA_CMD_DISPLAY_CURSOR and SVGA_CMD_MOVE_CURSOR should not be used.
261Drivers wishing hardware cursor support should use cursor bypass (see below).
262
263Other capabilities indicate other functionality as described below:
264
265 SVGA_CAP_CURSOR_BYPASS
266 The hardware cursor can be drawn via SVGA Registers (without requiring
267 the FIFO be synchronized and will be drawn potentially before any
268 outstanding unprocessed FIFO commands).
269
270 Note: Without SVGA_CAP_CURSOR_BYPASS_2, cursors drawn this way still
271 appear in the guest's framebuffer and need to be turned off before any
272 save under / overlapping drawing and turned back on after. This can
273 cause very noticeable cursor flicker.
274
275 SVGA_CAP_CURSOR_BYPASS_2
276 Instead of turning the cursor off and back on around any overlapping
277 drawing, the driver can write SVGA_CURSOR_ON_REMOVE_FROM_FB and
278 SVGA_CURSOR_ON_RESTORE_TO_FB to SVGA_REG_CURSOR_ON. In almost all
279 cases these are NOPs and the cursor will be remain visible without
280 appearing in the guest framebuffer. In 'direct graphics' modes like
281 Linux host fullscreen local displays, however, the cursor will still
282 be drawn in the framebuffer, still flicker, and be drawn incorrectly
283 if a driver does not use SVGA_CURSOR_ON_REMOVE_FROM_FB / RESTORE_TO_FB.
284
285 SVGA_CAP_8BIT_EMULATION
286 SVGA_REG_BITS_PER_PIXEL is writable and can be set to either 8 or
287 SVGA_REG_HOST_BITS_PER_PIXEL. Otherwise the only SVGA modes available
288 inside a virtual machine must match the host's bits per pixel.
289
290 Note: Some versions which lack SVGA_CAP_8BIT_EMULATION also lack the
291 SVGA_REG_HOST_BITS_PER_PIXEL and a driver should assume
292 SVGA_REG_BITS_PER_PIXEL is both read-only and initialized to the only
293 available value if SVGA_CAP_8BIT_EMULATION is not set.
294
295 SVGA_CAP_OFFSCREEN_1
296 SVGA_CMD_RECT_FILL, SVGA_CMD_RECT_COPY, SVGA_CMD_RECT_ROP_FILL,
297 SVGA_CMD_RECT_ROP_COPY can operate with a source or destination (or
298 both) in offscreen memory.
299
300 Usable offscreen memory is a rectangle located below the last scanline
301 of the visible memory:
302 x1 = 0
303 y1 = (SVGA_REG_FB_SIZE + SVGA_REG_BYTES_PER_LINE - 1) /
304 SVGA_REG_BYTES_PER_LINE
305 x2 = SVGA_REG_BYTES_PER_LINE / SVGA_REG_DEPTH
306 y2 = SVGA_REG_VRAM_SIZE / SVGA_REG_BYTES_PER_LINE
307
308
309Cursor Handling
310---------------
311
312Starting with GSX Server Beta 3 (after 11/15/2000), hardware cursor support
313was added. Actually, both a hardware cursor via the FIFO (SVGA_CAP_CURSOR)
314and a hardware cursor via the SVGA registers (SVGA_CAP_CURSOR_BYPASS) were
315added. SVGA_CAP_CURSOR was never available without SVGA_CAP_CURSOR_BYPASS and
316the FIFO hardware cursor should never be used and may be removed without
317warning in the future.
318
319Cursor bypass is programmed using the two FIFO commands SVGA_CMD_DEFINE_CURSOR
320and SVGA_CMD_DEFINE_ALPHA_CURSOR in conjunction with the SVGA registers
321SVGA_REG_CURSOR_ID, SVGA_REG_CURSOR_X, SVGA_REG_CURSOR_Y, and
322SVGA_REG_CURSOR_ON.
323
324A driver defines an AND/XOR hardware cursor using SVGA_CMD_DEFINE_CURSOR to
325assign an ID and establish the AND and XOR masks with the hardware. A driver
326uses SVGA_CMD_DEFINE_ALPHA_CURSOR to define a 32 bit mask whose top 8 bits are
327used to blend the cursor image with the pixels it covers. Alpha cursor
328support is only available when SVGA_CAP_ALPHA_CURSOR is set.
329
330Once a cursor is defined, a driver can draw it to the screen at any time by
331writing the SVGA_REG_CURSOR_ID register with the ID used when the cursor was
332defined, writing SVGA_REG_CURSOR_X and SVGA_REG_CURSOR_Y with the location of
333the cursor, and SVGA_CURSOR_ON_SHOW to SVGA_REG_CURSOR_ON. The drawing occurs
334when SVGA_REG_CURSOR_ON is written.
335
336Writing SVGA_CURSOR_ON_HIDE to SVGA_REG_CURSOR_ON will turn the cursor off and
337make it vanish from the display and, if present, from the framebuffer.
338SVGA_CURSOR_ON_REMOVE_FROM_FB will ensure the cursor is not in the
339framebuffer, but will only turn it off if there's no other way to remove it.
340SVGA_CURSOR_ON_RESTORE_TO_FB is the complement to
341SVGA_CURSOR_ON_REMOVE_FROM_FB. Whenever possible, the device will not put the
342cursor in the framebuffer and Remove From / Restore To will be NOPs.
343
344Note: The cursor must be out of the frame buffer before the driver (or any
345agent in the virtual machine) touches an overlapping portion of the frame
346buffer, because it is actually drawn into the frame buffer memory in the
347case of direct graphics mode (e.g. full screen mode on Linux). The cursor
348does not have to be touched before issuing an accelerated command via the
349command FIFO, this case is handled by the SVGA device.
350
351Note: If SVGA_CAP_CURSOR_BYPASS2 is not present, the driver must use
352SVGA_CURSOR_ON_HIDE and SVGA_CURSOR_ON_HIDE to be certain the cursor is out of
353the framebuffer.
354
355
356Driver Version Numbers
357----------------------
358
359The SVGA drivers use the following convention for their version numbers:
360
361Version 10.0 - The first version that uses the FIFO
362Version 10.1 - The version that uses the hardware cursor emulation via the FIFO
363Version 10.2 - The version that uses the cursor that bypasses the FIFO
364Version 10.3 - The version that can also support the 0405 chipset
365Version 10.4 - The version that knows about SVGA_CAP_CURSOR_BYPASS2
366Version 10.5 - [Never released or well defined]
367Version 10.6 - The version that knows about SVGA_CAP_8BIT_EMULATION
368Version 10.7 - The version that knows about SVGA_CAP_ALPHA_CURSOR
369Version 10.8 - The version that knows about SVGA_CAP_GLYPH
370Version 10.9 - The version that knows about SVGA_CAP_OFFSCREEN_1
371
372Note that this is merely the convention used by SVGA drivers written and
373maintained by VMware, Inc. and describes the capabilities of the driver, not
374the virtual hardware. An SVGA driver can only use the intersection of the
375functionality it supports and the functionality available in the virtual SVGA
376hardware.
377
378
379Frequently Asked Questions
380--------------------------
381
3821. My driver doesn't display anything, what's going on?
383
384First check if you are issuing an SVGA_CMD_UPDATE after drawing to
385the screen. Another check you can do is to run your driver in full
386screen mode on a Linux host. In this case you are drawing directly
387on the frame buffer, so what you draw to the screen will be immediately
388visible. If nothing is visible in this case, then most likely your
389driver hasn't mapped the frame buffer correctly.
390
391A discrepancy between what you get in full screen mode and what you
392get in window mode indicates that you have a missing or incorrect
393update command.
394
395
3962. What's the difference between bitmaps and pixmaps?
397
398Pixmaps have the same depth as the screen, while bitmaps have depth one.
399When a bitmap is drawn, the command also takes two colors, foreground and
400background. The set bits in the bitmap are replaced with the foreground
401color, and the unset bits are replaced with the background color.
402
403Pixmaps, on the other hand, can be directly copied to the screen.
404
405
4063. What's the significance of the ROP in the commands SVGA_CMD_RECT_ROP_FILL,
407SVGA_CMD_RECT_ROP_BITMAP_COPY, etc. ?
408
409The ROP in the ...ROP... commands is a raster operation. It has the same
410significance (and encoding) as it does in X. The ROP value SVGA_ROP_COPY
411means the source is copied to the destination, which makes these commands the
412same as their non-ROP counterparts. The most commonly used raster operation
413other than copy is probably SVGA_ROP_XOR, which combines the source and
414destination using exclusive-or.
415
416
4174. Tell me more about bitmaps and pixmaps. For example, the macro
418SVGA_CMD_DEFINE_BITMAP has a field <scanlines>. What should this be
419set to? Likewise with SVGA_CMD_DEFINE_PIXMAP. And when should the
420SCANLINE macros be used?
421
422OK, I'll use pixmaps as an example. First you have to define the pixmap:
423
424#define SVGA_CMD_DEFINE_PIXMAP 6
425 /* FIFO layout:
426 Pixmap ID, Width, Height, Depth, <scanlines> */
427
428The ID is something you choose, which you subsequently use to refer to
429this pixmap. It must be an integer between 0 and SVGA_MAX_ID.
430
431The width and height and depth are the dimensions of the pixmap. For now,
432the depth of the pixmap has to match the depth of the screen.
433
434The scanlines are the pixels that make up the pixmap, arranged one row
435at a time. Each row is required to be 32-bit aligned. The macros
436SVGA_PIXMAP_SCANLINE_SIZE and SVGA_PIXMAP_SIZE give the size of a
437single scanline, and the size of the entire pixmap, respectively, in
43832-bit words.
439
440The second step is to use it:
441
442#define SVGA_CMD_RECT_PIXMAP_FILL 9
443 /* FIFO layout:
444 Pixmap ID, X, Y, Width, Height */
445
446The ID here is the one you chose when defining the pixmap. X, Y,
447Width, and Height define a rectangle on the screen that is to be filled
448with the pixmap. The pixmap is screen aligned, which means that the
449coordinates in the pixmap are defined by the screen coordinates modulo
450the pixmap dimensions.
451
452If you want a different alignment between the screen and the pixmap,
453then you can use this command, which allows the pixmap coordinates to
454be defined:
455
456#define SVGA_CMD_RECT_PIXMAP_COPY 11
457 /* FIFO layout:
458 Pixmap ID, Source X, Source Y, Dest X, Dest Y, Width,
459 Height */
460
461The Source X and Source Y are pixmap coordinates, and the Dest X and
462Dest Y are screen coordinates.
463
464
4655. OK, now it works briefly, then stops displaying anything. Also,
466my log file is filled with lines like:
467 Unknown Command 0xff in SVGA command FIFO
468What's happening?
469
470The most common problem at this point is that the FIFO gets out
471of sync. This can happen if the amount of data in the FIFO doesn't
472match what the VMware SVGA device expects. To track this down, try
473to isolate the particular command which causes the problem.
474
475Another way this can happen is if the wraparound in the FIFO isn't
476done correctly. Here is some example code for writing to the FIFO
477(mem is an array of 32-bit integers that points to the FIFO memory
478region):
479
480while (TRUE) {
481 fifo_min = mem[SVGA_FIFO_MIN] / 4;
482 fifo_max = mem[SVGA_FIFO_MAX] / 4;
483 fifo_next = mem[SVGA_FIFO_NEXT_CMD] / 4;
484 fifo_stop = mem[SVGA_FIFO_STOP] / 4;
485
486 tmp_next = fifo_next+1;
487 if (tmp_next == fifo_max)
488 tmp_next = fifo_min; // Wraparound
489
490 if (tmp_next == fifo_stop) {
491 sync_fifo(); // FIFO full
492 continue; // retry
493 }
494
495 mem[fifo_next] = item;
496 mem[SVGA_FIFO_NEXT_CMD] = tmp_next * 4;
497 break;
498}
499
500This isn't the most efficient code, but it should work. It's important
501to do the increment with wraparound before the FIFO full check, and to
502check FIFO full before updating the next command pointer.
503
504
5056. My driver tries to switch modes and either nothing happens or the
506display becomes completely garbled. What's going on?
507
508When you change modes, make very sure you reread all of the registers listed
509above under SetMode. Getting the pitch (SVGA_REG_BYTES_PER_LINE) incorrect
510will cause a heavily garbled display. Also, if you change
511SVGA_REG_BITS_PER_PIXEL, make certain that SVGA_CAP_8BIT_EMULATION is present
512in the SVGA_REG_CAPABILITIES register. Also, even with 8 bit emulation, the
513driver must still use either 8 bpp or SVGA_REG_HOST_BITS_PER_PIXEL bpp,
514nothing else.
515
516
5177. Why does my driver's hardware cursor work when my virtual machine is in
518window mode, but draw/erase incorrectly or in garbled locations in fullscreen
519mode?
520
521You need to make sure you use SVGA_CURSOR_ON_REMOVE_FROM_FB and
522SVGA_CURSOR_ON_RESTORE_TO_FB _every_ time your driver or the virtual machine
523touches a region of the framebuffer that overlaps the cursor. If you forget
524to remove it then it can show up when doing save-under operations or get mixed
525in with other drawing. If you forget to restore it then can disappear. You
526also need to make sure SVGA_CAP_CURSOR_BYPASS2 is available, or else you will
527have to use SVGA_CURSOR_ON_SHOW and SVGA_CURSOR_ON_HIDE (which will flicker,
528even in window mode), or else a software cursor. Newer version of the virtual
529SVGA hardware will never put the hardware cursor in the framebuffer while in
530window mode, so everything will appear to work correctly there.
531
532
5338. Why do my accelerated glyphs look funny? OR Why does the fifo complain
534about invalid commands when I draw accelerated glyphs?
535
536The bitmap data passed to SVGA_CMD_DRAW_GLYPH_* must not have any per-scanline
537alignment. If there are any remaining bits left in the last byte of a scanline,
538the first bits of the next scanline should use them.
539
540The bitmap data as a whole must be 4 byte aligned.
541
542