127837Sdavidn/* 266830Sobrien * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 366830Sobrien * Distributed under the terms of the MIT License. 466830Sobrien * 566830Sobrien * Authors: 666830Sobrien * Alexander von Gluck, kallisti5@unixzen.com 766830Sobrien */ 866830Sobrien#ifndef RADEON_HD_GPU_H 966830Sobrien#define RADEON_HD_GPU_H 1066830Sobrien 1166830Sobrien 1266830Sobrien#include "accelerant.h" 1366830Sobrien 1466830Sobrien#include <video_configuration.h> 1566830Sobrien 1666830Sobrien#include "pll.h" 1766830Sobrien 1866830Sobrien 1966830Sobrien// GPU Control registers. These are combined as 2066830Sobrien// the registers exist on all models, some flags 2166830Sobrien// are different though and are commented as such 2266830Sobrien#define CP_ME_CNTL 0x86D8 2366830Sobrien#define CP_ME_HALT (1 << 28) 2466830Sobrien#define CP_PFP_HALT (1 << 26) 2566830Sobrien#define CP_ME_RAM_DATA 0xC160 2666830Sobrien#define CP_ME_RAM_RADDR 0xC158 2750472Speter#define CP_ME_RAM_WADDR 0xC15C 2866830Sobrien#define CP_MEQ_THRESHOLDS 0x8764 2927837Sdavidn#define STQ_SPLIT(x) ((x) << 0) 3051231Ssheldonh#define CP_PERFMON_CNTL 0x87FC 3127837Sdavidn#define CP_PFP_UCODE_ADDR 0xC150 3227837Sdavidn#define CP_PFP_UCODE_DATA 0xC154 3327837Sdavidn#define CP_QUEUE_THRESHOLDS 0x8760 3427837Sdavidn#define ROQ_IB1_START(x) ((x) << 0) 3527837Sdavidn#define ROQ_IB2_START(x) ((x) << 8) 3627837Sdavidn#define CP_RB_BASE 0xC100 3727837Sdavidn#define CP_RB_CNTL 0xC104 3827837Sdavidn#define RB_BUFSZ(x) ((x) << 0) 3927837Sdavidn#define RB_BLKSZ(x) ((x) << 8) 4027837Sdavidn#define RB_NO_UPDATE (1 << 27) 4127837Sdavidn#define RB_RPTR_WR_ENA (1 << 31) 4251231Ssheldonh#define BUF_SWAP_32BIT (2 << 16) 4327837Sdavidn#define CP_RB_RPTR 0x8700 4451231Ssheldonh#define CP_RB_RPTR_ADDR 0xC10C 4527837Sdavidn#define RB_RPTR_SWAP(x) ((x) << 0) 4662640Stg#define CP_RB_RPTR_ADDR_HI 0xC110 4798189Sgordon#define CP_RB_RPTR_WR 0xC108 4862640Stg#define CP_RB_WPTR 0xC114 4962640Stg#define CP_RB_WPTR_ADDR 0xC118 5062640Stg#define CP_RB_WPTR_ADDR_HI 0xC11C 5162640Stg#define CP_RB_WPTR_DELAY 0x8704 5262640Stg#define CP_SEM_WAIT_TIMER 0x85BC 5362640Stg#define CP_DEBUG 0xC1FC 5462640Stg 5562640Stg#define NI_GRBM_CNTL 0x8000 5698189Sgordon#define GRBM_READ_TIMEOUT(x) ((x) << 0) 5798189Sgordon#define GRBM_STATUS 0x8010 5898189Sgordon#define CMDFIFO_AVAIL_MASK 0x0000000F 5998189Sgordon#define RING2_RQ_PENDING (1 << 4) 6098189Sgordon#define SRBM_RQ_PENDING (1 << 5) 6198189Sgordon#define RING1_RQ_PENDING (1 << 6) 6298189Sgordon#define CF_RQ_PENDING (1 << 7) 6398189Sgordon#define PF_RQ_PENDING (1 << 8) 6498189Sgordon#define GDS_DMA_RQ_PENDING (1 << 9) 6598189Sgordon#define GRBM_EE_BUSY (1 << 10) 6698189Sgordon#define SX_CLEAN (1 << 11) // ni 6798189Sgordon#define VC_BUSY (1 << 11) // r600 6898189Sgordon#define DB_CLEAN (1 << 12) 6998189Sgordon#define CB_CLEAN (1 << 13) 7098189Sgordon#define TA_BUSY (1 << 14) 7198189Sgordon#define GDS_BUSY (1 << 15) 7298189Sgordon#define VGT_BUSY_NO_DMA (1 << 16) 7398189Sgordon#define VGT_BUSY (1 << 17) 7498189Sgordon#define IA_BUSY_NO_DMA (1 << 18) // ni 7598189Sgordon#define TA03_BUSY (1 << 18) // r600 7698189Sgordon#define IA_BUSY (1 << 19) // ni 7798189Sgordon#define TC_BUSY (1 << 19) // r600 7898189Sgordon#define SX_BUSY (1 << 20) 7998189Sgordon#define SH_BUSY (1 << 21) 8098189Sgordon#define SPI_BUSY (1 << 22) // AKA SPI03_BUSY r600 8198189Sgordon#define SMX_BUSY (1 << 23) 8298189Sgordon#define SC_BUSY (1 << 24) 8398189Sgordon#define PA_BUSY (1 << 25) 8498189Sgordon#define DB_BUSY (1 << 26) // AKA DB03_BUSY r600 8598189Sgordon#define CR_BUSY (1 << 27) 8698189Sgordon#define CP_COHERENCY_BUSY (1 << 28) 8798189Sgordon#define CP_BUSY (1 << 29) 8898189Sgordon#define CB_BUSY (1 << 30) 8998189Sgordon#define GUI_ACTIVE (1 << 31) 9098189Sgordon#define GRBM_STATUS2 0x8014 // AKA GRBM_STATUS_SE0 ON NI 9198189Sgordon#define CR_CLEAN (1 << 0) 9298189Sgordon#define SMX_CLEAN (1 << 1) 9398189Sgordon#define SPI0_BUSY (1 << 8) 9498189Sgordon#define SPI1_BUSY (1 << 9) 9598189Sgordon#define SPI2_BUSY (1 << 10) 9698189Sgordon#define SPI3_BUSY (1 << 11) 9798189Sgordon#define TA0_BUSY (1 << 12) 9898189Sgordon#define TA1_BUSY (1 << 13) 9998189Sgordon#define TA2_BUSY (1 << 14) 10098189Sgordon#define TA3_BUSY (1 << 15) 10198189Sgordon#define DB0_BUSY (1 << 16) 10298189Sgordon#define DB1_BUSY (1 << 17) 10398189Sgordon#define DB2_BUSY (1 << 18) 10498189Sgordon#define DB3_BUSY (1 << 19) 10598189Sgordon#define CB0_BUSY (1 << 20) 10696830Sgordon#define CB1_BUSY (1 << 21) 10796830Sgordon#define CB2_BUSY (1 << 22) 10896830Sgordon#define CB3_BUSY (1 << 23) 10996830Sgordon#define NI_GRBM_STATUS_SE1 0x8018 11096830Sgordon#define SE_SX_CLEAN (1 << 0) 11196830Sgordon#define SE_DB_CLEAN (1 << 1) 11296830Sgordon#define SE_CB_CLEAN (1 << 2) 11396830Sgordon#define SE_VGT_BUSY (1 << 23) 11496830Sgordon#define SE_PA_BUSY (1 << 24) 11596830Sgordon#define SE_TA_BUSY (1 << 25) 11696830Sgordon#define SE_SX_BUSY (1 << 26) 11796830Sgordon#define SE_SPI_BUSY (1 << 27) 11863307Smarkm#define SE_SH_BUSY (1 << 28) 11963307Smarkm#define SE_SC_BUSY (1 << 29) 12063307Smarkm#define SE_DB_BUSY (1 << 30) 12163307Smarkm#define SE_CB_BUSY (1 << 31) 12263307Smarkm#define GRBM_SOFT_RESET 0x8020 12363307Smarkm#define SRBM_STATUS 0x0E50 12470108Sdougb#define RLC_RQ_PENDING (1 << 3) 12563311Ssheldonh#define RCU_RQ_PENDING (1 << 4) 12663801Ssheldonh#define GRBM_RQ_PENDING (1 << 5) 12763801Ssheldonh#define HI_RQ_PENDING (1 << 6) 12867179Sjwd#define IO_EXTERN_SIGNAL (1 << 7) 12967179Sjwd#define VMC_BUSY (1 << 8) 13067179Sjwd#define MCB_BUSY (1 << 9) 13167179Sjwd#define MCDZ_BUSY (1 << 10) 13267179Sjwd#define MCDY_BUSY (1 << 11) 13367179Sjwd#define MCDX_BUSY (1 << 12) 13467179Sjwd#define MCDW_BUSY (1 << 13) 13567179Sjwd#define SEM_BUSY (1 << 14) 13667179Sjwd#define SRBM_STATUS__RLC_BUSY (1 << 15) 13767179Sjwd#define PDMA_BUSY (1 << 16) 13867179Sjwd#define IH_BUSY (1 << 17) 13967179Sjwd#define CSC_BUSY (1 << 20) 14070108Sdougb#define CMC7_BUSY (1 << 21) 14167179Sjwd#define CMC6_BUSY (1 << 22) 14267179Sjwd#define CMC5_BUSY (1 << 23) 14367179Sjwd#define CMC4_BUSY (1 << 24) 14467397Sache#define CMC3_BUSY (1 << 25) 14570108Sdougb#define CMC2_BUSY (1 << 26) 14667179Sjwd#define CMC1_BUSY (1 << 27) 14767179Sjwd#define CMC0_BUSY (1 << 28) 14863801Ssheldonh#define BIF_BUSY (1 << 29) 14963307Smarkm#define IDCT_BUSY (1 << 30) 15063307Smarkm#define SRBM_SOFT_RESET 0x0E60 15163307Smarkm#define SOFT_RESET_CP (1 << 0) 15253550Sdillon#define SOFT_RESET_CB (1 << 1) 15353550Sdillon#define SOFT_RESET_CR (1 << 2) 15453550Sdillon#define SOFT_RESET_DB (1 << 3) 15553550Sdillon#define SOFT_RESET_GDS (1 << 4) 15653550Sdillon#define SOFT_RESET_PA (1 << 5) 15753550Sdillon#define SOFT_RESET_SC (1 << 6) 15853550Sdillon#define SOFT_RESET_SMX (1 << 7) 15953550Sdillon#define SOFT_RESET_SPI (1 << 8) 16053550Sdillon#define SOFT_RESET_SH (1 << 9) 16170108Sdougb#define SOFT_RESET_SX (1 << 10) 16227837Sdavidn#define SOFT_RESET_TC (1 << 11) 16362640Stg#define SOFT_RESET_TA (1 << 12) 16462640Stg#define SOFT_RESET_VC (1 << 13) 16562640Stg#define SOFT_RESET_VGT (1 << 14) 16662640Stg#define SOFT_RESET_IA (1 << 15) 16762640Stg 16879825Sroam 16987728Sroamstatus_t radeon_gpu_probe(); 17087728Sroamstatus_t radeon_gpu_reset(); 17187728Sroamvoid radeon_gpu_mc_halt(struct gpu_state *gpuState); 17262640Stgvoid radeon_gpu_mc_resume(struct gpu_state *gpuState); 17362640Stgstatus_t radeon_gpu_mc_idlewait(); 17462640Stgstatus_t radeon_gpu_mc_setup(); 17596830Sgordonstatus_t radeon_gpu_ring_setup(); 17662640Stgstatus_t radeon_gpu_ring_boot(uint32 ringType); 17762640Stgstatus_t radeon_gpu_ss_control(pll_info* pll, bool enable); 17862640Stg 17979825Sroam 18079825Sroam 18196830Sgordon#endif 18279825Sroam