1/* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Alexander von Gluck, kallisti5@unixzen.com 7 */ 8#ifndef RADEON_HD_GPU_H 9#define RADEON_HD_GPU_H 10 11 12#include "accelerant.h" 13 14#include <video_configuration.h> 15 16#include "pll.h" 17 18 19// GPU Control registers. These are combined as 20// the registers exist on all models, some flags 21// are different though and are commented as such 22#define CP_ME_CNTL 0x86D8 23#define CP_ME_HALT (1 << 28) 24#define CP_PFP_HALT (1 << 26) 25#define CP_ME_RAM_DATA 0xC160 26#define CP_ME_RAM_RADDR 0xC158 27#define CP_ME_RAM_WADDR 0xC15C 28#define CP_MEQ_THRESHOLDS 0x8764 29#define STQ_SPLIT(x) ((x) << 0) 30#define CP_PERFMON_CNTL 0x87FC 31#define CP_PFP_UCODE_ADDR 0xC150 32#define CP_PFP_UCODE_DATA 0xC154 33#define CP_QUEUE_THRESHOLDS 0x8760 34#define ROQ_IB1_START(x) ((x) << 0) 35#define ROQ_IB2_START(x) ((x) << 8) 36#define CP_RB_BASE 0xC100 37#define CP_RB_CNTL 0xC104 38#define RB_BUFSZ(x) ((x) << 0) 39#define RB_BLKSZ(x) ((x) << 8) 40#define RB_NO_UPDATE (1 << 27) 41#define RB_RPTR_WR_ENA (1 << 31) 42#define BUF_SWAP_32BIT (2 << 16) 43#define CP_RB_RPTR 0x8700 44#define CP_RB_RPTR_ADDR 0xC10C 45#define RB_RPTR_SWAP(x) ((x) << 0) 46#define CP_RB_RPTR_ADDR_HI 0xC110 47#define CP_RB_RPTR_WR 0xC108 48#define CP_RB_WPTR 0xC114 49#define CP_RB_WPTR_ADDR 0xC118 50#define CP_RB_WPTR_ADDR_HI 0xC11C 51#define CP_RB_WPTR_DELAY 0x8704 52#define CP_SEM_WAIT_TIMER 0x85BC 53#define CP_DEBUG 0xC1FC 54 55#define NI_GRBM_CNTL 0x8000 56#define GRBM_READ_TIMEOUT(x) ((x) << 0) 57#define GRBM_STATUS 0x8010 58#define CMDFIFO_AVAIL_MASK 0x0000000F 59#define RING2_RQ_PENDING (1 << 4) 60#define SRBM_RQ_PENDING (1 << 5) 61#define RING1_RQ_PENDING (1 << 6) 62#define CF_RQ_PENDING (1 << 7) 63#define PF_RQ_PENDING (1 << 8) 64#define GDS_DMA_RQ_PENDING (1 << 9) 65#define GRBM_EE_BUSY (1 << 10) 66#define SX_CLEAN (1 << 11) // ni 67#define VC_BUSY (1 << 11) // r600 68#define DB_CLEAN (1 << 12) 69#define CB_CLEAN (1 << 13) 70#define TA_BUSY (1 << 14) 71#define GDS_BUSY (1 << 15) 72#define VGT_BUSY_NO_DMA (1 << 16) 73#define VGT_BUSY (1 << 17) 74#define IA_BUSY_NO_DMA (1 << 18) // ni 75#define TA03_BUSY (1 << 18) // r600 76#define IA_BUSY (1 << 19) // ni 77#define TC_BUSY (1 << 19) // r600 78#define SX_BUSY (1 << 20) 79#define SH_BUSY (1 << 21) 80#define SPI_BUSY (1 << 22) // AKA SPI03_BUSY r600 81#define SMX_BUSY (1 << 23) 82#define SC_BUSY (1 << 24) 83#define PA_BUSY (1 << 25) 84#define DB_BUSY (1 << 26) // AKA DB03_BUSY r600 85#define CR_BUSY (1 << 27) 86#define CP_COHERENCY_BUSY (1 << 28) 87#define CP_BUSY (1 << 29) 88#define CB_BUSY (1 << 30) 89#define GUI_ACTIVE (1 << 31) 90#define GRBM_STATUS2 0x8014 // AKA GRBM_STATUS_SE0 ON NI 91#define CR_CLEAN (1 << 0) 92#define SMX_CLEAN (1 << 1) 93#define SPI0_BUSY (1 << 8) 94#define SPI1_BUSY (1 << 9) 95#define SPI2_BUSY (1 << 10) 96#define SPI3_BUSY (1 << 11) 97#define TA0_BUSY (1 << 12) 98#define TA1_BUSY (1 << 13) 99#define TA2_BUSY (1 << 14) 100#define TA3_BUSY (1 << 15) 101#define DB0_BUSY (1 << 16) 102#define DB1_BUSY (1 << 17) 103#define DB2_BUSY (1 << 18) 104#define DB3_BUSY (1 << 19) 105#define CB0_BUSY (1 << 20) 106#define CB1_BUSY (1 << 21) 107#define CB2_BUSY (1 << 22) 108#define CB3_BUSY (1 << 23) 109#define NI_GRBM_STATUS_SE1 0x8018 110#define SE_SX_CLEAN (1 << 0) 111#define SE_DB_CLEAN (1 << 1) 112#define SE_CB_CLEAN (1 << 2) 113#define SE_VGT_BUSY (1 << 23) 114#define SE_PA_BUSY (1 << 24) 115#define SE_TA_BUSY (1 << 25) 116#define SE_SX_BUSY (1 << 26) 117#define SE_SPI_BUSY (1 << 27) 118#define SE_SH_BUSY (1 << 28) 119#define SE_SC_BUSY (1 << 29) 120#define SE_DB_BUSY (1 << 30) 121#define SE_CB_BUSY (1 << 31) 122#define GRBM_SOFT_RESET 0x8020 123#define SRBM_STATUS 0x0E50 124#define RLC_RQ_PENDING (1 << 3) 125#define RCU_RQ_PENDING (1 << 4) 126#define GRBM_RQ_PENDING (1 << 5) 127#define HI_RQ_PENDING (1 << 6) 128#define IO_EXTERN_SIGNAL (1 << 7) 129#define VMC_BUSY (1 << 8) 130#define MCB_BUSY (1 << 9) 131#define MCDZ_BUSY (1 << 10) 132#define MCDY_BUSY (1 << 11) 133#define MCDX_BUSY (1 << 12) 134#define MCDW_BUSY (1 << 13) 135#define SEM_BUSY (1 << 14) 136#define SRBM_STATUS__RLC_BUSY (1 << 15) 137#define PDMA_BUSY (1 << 16) 138#define IH_BUSY (1 << 17) 139#define CSC_BUSY (1 << 20) 140#define CMC7_BUSY (1 << 21) 141#define CMC6_BUSY (1 << 22) 142#define CMC5_BUSY (1 << 23) 143#define CMC4_BUSY (1 << 24) 144#define CMC3_BUSY (1 << 25) 145#define CMC2_BUSY (1 << 26) 146#define CMC1_BUSY (1 << 27) 147#define CMC0_BUSY (1 << 28) 148#define BIF_BUSY (1 << 29) 149#define IDCT_BUSY (1 << 30) 150#define SRBM_SOFT_RESET 0x0E60 151#define SOFT_RESET_CP (1 << 0) 152#define SOFT_RESET_CB (1 << 1) 153#define SOFT_RESET_CR (1 << 2) 154#define SOFT_RESET_DB (1 << 3) 155#define SOFT_RESET_GDS (1 << 4) 156#define SOFT_RESET_PA (1 << 5) 157#define SOFT_RESET_SC (1 << 6) 158#define SOFT_RESET_SMX (1 << 7) 159#define SOFT_RESET_SPI (1 << 8) 160#define SOFT_RESET_SH (1 << 9) 161#define SOFT_RESET_SX (1 << 10) 162#define SOFT_RESET_TC (1 << 11) 163#define SOFT_RESET_TA (1 << 12) 164#define SOFT_RESET_VC (1 << 13) 165#define SOFT_RESET_VGT (1 << 14) 166#define SOFT_RESET_IA (1 << 15) 167 168 169status_t radeon_gpu_probe(); 170status_t radeon_gpu_reset(); 171void radeon_gpu_mc_halt(struct gpu_state *gpuState); 172void radeon_gpu_mc_resume(struct gpu_state *gpuState); 173status_t radeon_gpu_mc_idlewait(); 174status_t radeon_gpu_mc_setup(); 175status_t radeon_gpu_ring_setup(); 176status_t radeon_gpu_ring_boot(uint32 ringType); 177status_t radeon_gpu_ss_control(pll_info* pll, bool enable); 178 179 180 181#endif 182