1/* 2 * Copyright 2011-2013, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Alexander von Gluck IV, kallisti5@unixzen.com 7 * Bill Randle, billr@neocat.org 8 */ 9#ifndef RADEON_HD_DISPLAYPORT_H 10#define RADEON_HD_DISPLAYPORT_H 11 12 13#include <create_display_modes.h> 14#include <stdint.h> 15#include <SupportDefs.h> 16 17#include "accelerant.h" 18#include "dp.h" 19 20 21// Radeon HD specific DisplayPort Configuration Data 22#define DP_TRAINING_AUX_RD_INTERVAL 0x000e 23#define DP_TPS3_SUPPORTED (1 << 6) // Stored within MAX_LANE_COUNT 24 25 26uint8 dpcd_reg_read(uint32 hwPin, uint16 address); 27void dpcd_reg_write(uint32 hwPin, uint16 address, uint8 value); 28 29int dp_aux_write(uint32 hwPin, uint16 address, uint8* send, 30 uint8 sendBytes, uint8 delay); 31int dp_aux_read(uint32 hwPin, uint16 address, uint8* recv, 32 int recvBytes, uint8 delay); 33status_t dp_aux_set_i2c_byte(uint32 hwPin, uint16 address, 34 uint8* data, bool start, bool stop); 35status_t dp_aux_get_i2c_byte(uint32 hwPin, uint16 address, 36 uint8* data, bool start, bool stop); 37 38uint32 dp_get_link_rate(uint32 connectorIndex, display_mode* mode); 39uint32 dp_get_lane_count(uint32 connectorIndex, display_mode* mode); 40 41void dp_setup_connectors(); 42 43status_t dp_link_train(uint8 crtcID); 44status_t dp_link_train_cr(uint32 connectorIndex); 45status_t dp_link_train_ce(uint32 connectorIndex); 46 47void debug_dp_info(); 48 49status_t dp_get_pixel_size_for(color_space space, size_t *pixelChunk, 50 size_t *rowAlignment, size_t *pixelsPerChunk); 51 52bool ddc2_dp_read_edid1(uint32 connectorIndex, edid1_info *edid); 53 54 55#endif /* RADEON_HD_DISPLAYPORT_H */ 56