radeon_hd: Fix DisplayPort link training

* Original changes by Bill Randle
* Includes a large number of modifications
and cleanups.
* Add a "currentMode" to the gDisplay to
enable easier checking of intended changes.
(we pass the display_mode around quite a
bit, adding a "currentMode" allows code
to know the intended display mode being set
without passing the mode pointer around as
much)

radeon_hd: Improve displayport support

* Modified patch submitted by Bill Randle.
* DisplayPort aux communications now working.
* DP Link Training still not functioning properly.
* The DP edid data isn't used yet as we still use
the vesa edid during the mode setting.

radeon_hd: enable non-dp code to execute dpcd queries

* Check DPCD to properly choose TRAVIS DP panel mode

radeon_hd: add DisplayPort debugging

* Commented out by default
* Shows DisplayPort status info for each
connector post-mode change (as DP properies
are configured on mode change once we know
the pixel clock)

radeon_hd: display port improvements

* Remove non-generic radeon dp_get_lane_count
* Set lane count and link rate at set_display_mode
* Pass entire mode to pll_set vs only pixel clock for DP code
* Add helpers for DP config data to common code
* Obtain more correct link rate

radeon_hd: Add DP link_train_ce

* First attempts at DisplayPort link training
clock equalization.
* Add DP define to detect equalization state
* Working towards resolving #8626

radeon_hd: Move out some DisplayPort common code

* General DisplayPort functions in common dp.cpp
* DP port information struct in common header
* Please don't use this private accelerant common DP
code just yet as it is very early.

radeon_hd: Complete move to common DisplayPort header

* Non-spec DP stuff in accelerant displayport.h
* Common DisplayPort header still has TODO's however

dp_raw: Continued cleanup of DisplayPort common header

* Reduce number of common DP registers in radeon_hd
* Move to bitwise shifts as they will make more
sense to more people in the long-run

radeon_hd: Start work on proper DP link training

* The AtomBIOS timeout fix has made my DP bridge
stop working
* The current DisplayPort code is a little lacking
on DP link training... I think thats the cause.
* This puts the first steps towards DP training
in place.
* I plan on trying to make some of this DP stuff
common accelerant stuff after it works.

DisplayPort call organization and cleanup

* Add color space to BPP function
* Pass display_mode to DP lane count function
* Get BPP in DP lane count
* Move some DPInfo population out of DP link training
as other things need them sooner.
* Fill out DP code in external encoder setup

Working towards DP connector support

* Lots of new DisplayPort functions
* Call DP link training during mode set
* Rename dp_info variables to be less redundant
* Make encoder_pick_dig accept connector ID and
then check parent display
* Encode/Decode DP link speed functions
* Calculate DP lanes
* Rewrite encoder_dig_setup
* Correct bitsPerChannel to bitsPerColor
* My TRAVIS DisplayPort -> LVDS bridge now works

Begin work powering up the DisplayPort connector

* Add new struct to store DP connector information
* DisplayPort Configuration Data is populated by setup function

GPIO info struct style cleanup, (hopefully) no functional change

Add complete set of DRM DisplayPort defines into radeon_hd

* I'd rather this be common code, but I don't have access
to the DisplayPort specifications. If I added it as common
code I would want to be 100% it was complete and variables
were named properly.
* For now putting in radeon_hd private headers

Introduce new displayport source file

* Move existing displayport functions to new source file
* Move was done due to large amount of DP code
* Style fixes
* Stub out new DP link training function

radeon_hd: enable non-dp code to execute dpcd queries

* Check DPCD to properly choose TRAVIS DP panel mode

radeon_hd: add DisplayPort debugging

* Commented out by default
* Shows DisplayPort status info for each
connector post-mode change (as DP properies
are configured on mode change once we know
the pixel clock)

radeon_hd: display port improvements

* Remove non-generic radeon dp_get_lane_count
* Set lane count and link rate at set_display_mode
* Pass entire mode to pll_set vs only pixel clock for DP code
* Add helpers for DP config data to common code
* Obtain more correct link rate

radeon_hd: Add DP link_train_ce

* First attempts at DisplayPort link training
clock equalization.
* Add DP define to detect equalization state
* Working towards resolving #8626

radeon_hd: Move out some DisplayPort common code

* General DisplayPort functions in common dp.cpp
* DP port information struct in common header
* Please don't use this private accelerant common DP
code just yet as it is very early.

radeon_hd: Complete move to common DisplayPort header

* Non-spec DP stuff in accelerant displayport.h
* Common DisplayPort header still has TODO's however

dp_raw: Continued cleanup of DisplayPort common header

* Reduce number of common DP registers in radeon_hd
* Move to bitwise shifts as they will make more
sense to more people in the long-run

radeon_hd: Start work on proper DP link training

* The AtomBIOS timeout fix has made my DP bridge
stop working
* The current DisplayPort code is a little lacking
on DP link training... I think thats the cause.
* This puts the first steps towards DP training
in place.
* I plan on trying to make some of this DP stuff
common accelerant stuff after it works.

DisplayPort call organization and cleanup

* Add color space to BPP function
* Pass display_mode to DP lane count function
* Get BPP in DP lane count
* Move some DPInfo population out of DP link training
as other things need them sooner.
* Fill out DP code in external encoder setup

Working towards DP connector support

* Lots of new DisplayPort functions
* Call DP link training during mode set
* Rename dp_info variables to be less redundant
* Make encoder_pick_dig accept connector ID and
then check parent display
* Encode/Decode DP link speed functions
* Calculate DP lanes
* Rewrite encoder_dig_setup
* Correct bitsPerChannel to bitsPerColor
* My TRAVIS DisplayPort -> LVDS bridge now works

Begin work powering up the DisplayPort connector

* Add new struct to store DP connector information
* DisplayPort Configuration Data is populated by setup function

GPIO info struct style cleanup, (hopefully) no functional change

Add complete set of DRM DisplayPort defines into radeon_hd

* I'd rather this be common code, but I don't have access
to the DisplayPort specifications. If I added it as common
code I would want to be 100% it was complete and variables
were named properly.
* For now putting in radeon_hd private headers

Introduce new displayport source file

* Move existing displayport functions to new source file
* Move was done due to large amount of DP code
* Style fixes
* Stub out new DP link training function