1/* program the DAC */ 2/* Author: 3 Rudolf Cornelissen 12/2003-6/2008 4*/ 5 6#define MODULE_BIT 0x00010000 7 8#include "nv_std.h" 9 10static status_t nv4_nv10_nv20_dac_pix_pll_find( 11 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test); 12 13/* see if an analog VGA monitor is connected to connector #1 */ 14bool nv_dac_crt_connected(void) 15{ 16 uint32 output, dac; 17 bool present; 18 19 /* save output connector setting */ 20 output = DACR(OUTPUT); 21 /* save DAC state */ 22 dac = DACR(TSTCTRL); 23 24 /* turn on DAC */ 25 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeffff)); 26 if (si->ps.secondary_head) 27 { 28 /* select primary CRTC (head) and turn off CRT (and DVI?) outputs */ 29 DACW(OUTPUT, (output & 0x0000feee)); 30 } 31 else 32 { 33 /* turn off CRT (and DVI?) outputs */ 34 /* note: 35 * Don't touch the CRTC (head) assignment bit, as that would have undefined 36 * results. Confirmed NV15 cards getting into lasting RAM access trouble 37 * otherwise!! (goes for both system gfx RAM access and CRTC/DAC RAM access.) */ 38 DACW(OUTPUT, (output & 0x0000ffee)); 39 } 40 /* wait for signal lines to stabilize */ 41 snooze(1000); 42 /* re-enable CRT output */ 43 DACW(OUTPUT, (DACR(OUTPUT) | 0x00000001)); 44 45 /* setup RGB test signal levels to approx 30% of DAC range and enable them */ 46 DACW(TSTDATA, ((0x2 << 30) | (0x140 << 20) | (0x140 << 10) | (0x140 << 0))); 47 /* route test signals to output */ 48 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 49 /* wait for signal lines to stabilize */ 50 snooze(1000); 51 52 /* do actual detection: all signals paths high == CRT connected */ 53 if (DACR(TSTCTRL) & 0x10000000) 54 { 55 present = true; 56 LOG(4,("DAC: CRT detected on connector #1\n")); 57 } 58 else 59 { 60 present = false; 61 LOG(4,("DAC: no CRT detected on connector #1\n")); 62 } 63 64 /* kill test signal routing */ 65 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff)); 66 67 /* restore output connector setting */ 68 DACW(OUTPUT, output); 69 /* restore DAC state */ 70 DACW(TSTCTRL, dac); 71 72 return present; 73} 74 75/*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/ 76status_t nv_dac_mode(int mode,float brightness) 77{ 78 uint8 *r,*g,*b; 79 int i, ri; 80 81 /*set colour arrays to point to space reserved in shared info*/ 82 r = si->color_data; 83 g = r + 256; 84 b = g + 256; 85 86 LOG(4,("DAC: Setting screen mode %d brightness %f\n", mode, brightness)); 87 /* init the palette for brightness specified */ 88 /* (Nvidia cards always use MSbits from screenbuffer as index for PAL) */ 89 for (i = 0; i < 256; i++) 90 { 91 ri = i * brightness; 92 if (ri > 255) ri = 255; 93 b[i] = g[i] = r[i] = ri; 94 } 95 96 if (nv_dac_palette(r,g,b) != B_OK) return B_ERROR; 97 98 /* disable palette RAM adressing mask */ 99 NV_REG8(NV8_PALMASK) = 0xff; 100 LOG(2,("DAC: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PALMASK))); 101 102 return B_OK; 103} 104 105/*program the DAC palette using the given r,g,b values*/ 106status_t nv_dac_palette(uint8 r[256],uint8 g[256],uint8 b[256]) 107{ 108 int i; 109 110 LOG(4,("DAC: setting palette\n")); 111 112 /* select first PAL adress before starting programming */ 113 NV_REG8(NV8_PALINDW) = 0x00; 114 115 /* loop through all 256 to program DAC */ 116 for (i = 0; i < 256; i++) 117 { 118 /* the 6 implemented bits are on b0-b5 of the bus */ 119 NV_REG8(NV8_PALDATA) = r[i]; 120 NV_REG8(NV8_PALDATA) = g[i]; 121 NV_REG8(NV8_PALDATA) = b[i]; 122 } 123 if (NV_REG8(NV8_PALINDW) != 0x00) 124 { 125 LOG(8,("DAC: PAL write index incorrect after programming\n")); 126 return B_ERROR; 127 } 128if (1) 129 {//reread LUT 130 uint8 R, G, B; 131 132 /* select first PAL adress to read (modulo 3 counter) */ 133 NV_REG8(NV8_PALINDR) = 0x00; 134 for (i = 0; i < 256; i++) 135 { 136 R = NV_REG8(NV8_PALDATA); 137 G = NV_REG8(NV8_PALDATA); 138 B = NV_REG8(NV8_PALDATA); 139 if ((r[i] != R) || (g[i] != G) || (b[i] != B)) 140 LOG(1,("DAC palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed 141 } 142 } 143 144 return B_OK; 145} 146 147/*program the pixpll - frequency in kHz*/ 148status_t nv_dac_set_pix_pll(display_mode target) 149{ 150 uint8 m=0,n=0,p=0; 151// uint time = 0; 152 153 float pix_setting, req_pclk; 154 status_t result; 155 156 /* we offer this option because some panels have very tight restrictions, 157 * and there's no overlapping settings range that makes them all work. 158 * note: 159 * this assumes the cards BIOS correctly programmed the panel (is likely) */ 160 //fixme: when VESA DDC EDID stuff is implemented, this option can be deleted... 161 if (si->ps.tmds1_active && !si->settings.pgm_panel) 162 { 163 LOG(4,("DAC: Not programming DFP refresh (specified in nv.settings)\n")); 164 return B_OK; 165 } 166 167 /* fix a DVI or laptop flatpanel to 60Hz refresh! */ 168 /* Note: 169 * The pixelclock drives the flatpanel modeline, not the CRTC modeline. */ 170 if (si->ps.tmds1_active) 171 { 172 LOG(4,("DAC: Fixing DFP refresh to 60Hz!\n")); 173 174 /* use the panel's modeline to determine the needed pixelclock */ 175 target.timing.pixel_clock = si->ps.p1_timing.pixel_clock; 176 } 177 178 req_pclk = (target.timing.pixel_clock)/1000.0; 179 LOG(4,("DAC: Setting PIX PLL for pixelclock %f\n", req_pclk)); 180 181 /* signal that we actually want to set the mode */ 182 result = nv_dac_pix_pll_find(target,&pix_setting,&m,&n,&p, 1); 183 if (result != B_OK) 184 { 185 return result; 186 } 187 188 /*reprogram (disable,select,wait for stability,enable)*/ 189// DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0F)|0x04); /*disable the PIXPLL*/ 190// DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01); /*select the PIXPLL*/ 191 192 /* program new frequency */ 193 DACW(PIXPLLC, ((p << 16) | (n << 8) | m)); 194 195 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 196 if (si->ps.ext_pll) DACW(PIXPLLC2, 0x80000401); 197 198 /* Wait for the PIXPLL frequency to lock until timeout occurs */ 199//fixme: do NV cards have a LOCK indication bit?? 200/* while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000)) 201 { 202 time++; 203 snooze(1); 204 } 205 206 if (time > 2000) 207 LOG(2,("DAC: PIX PLL frequency not locked!\n")); 208 else 209 LOG(2,("DAC: PIX PLL frequency locked\n")); 210 DXIW(PIXCLKCTRL,DXIR(PIXCLKCTRL)&0x0B); //enable the PIXPLL 211*/ 212 213//for now: 214 /* Give the PIXPLL frequency some time to lock... */ 215 snooze(1000); 216 LOG(2,("DAC: PIX PLL frequency should be locked now...\n")); 217 218 return B_OK; 219} 220 221/* find nearest valid pix pll */ 222status_t nv_dac_pix_pll_find 223 (display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 224{ 225 switch (si->ps.card_type) { 226 default: return nv4_nv10_nv20_dac_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test); 227 } 228 return B_ERROR; 229} 230 231/* find nearest valid pixel PLL setting */ 232static status_t nv4_nv10_nv20_dac_pix_pll_find( 233 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 234{ 235 int m = 0, n = 0, p = 0/*, m_max*/; 236 float error, error_best = 999999999; 237 int best[3]; 238 float f_vco, max_pclk; 239 float req_pclk = target.timing.pixel_clock/1000.0; 240 241 /* determine the max. reference-frequency postscaler setting for the 242 * current card (see G100, G200 and G400 specs). */ 243/* switch(si->ps.card_type) 244 { 245 case G100: 246 LOG(4,("DAC: G100 restrictions apply\n")); 247 m_max = 7; 248 break; 249 case G200: 250 LOG(4,("DAC: G200 restrictions apply\n")); 251 m_max = 7; 252 break; 253 default: 254 LOG(4,("DAC: G400/G400MAX restrictions apply\n")); 255 m_max = 32; 256 break; 257 } 258*/ 259 LOG(4,("DAC: NV4/NV10/NV20 restrictions apply\n")); 260 261 /* determine the max. pixelclock for the current videomode */ 262 switch (target.space) 263 { 264 case B_CMAP8: 265 max_pclk = si->ps.max_dac1_clock_8; 266 break; 267 case B_RGB15_LITTLE: 268 case B_RGB16_LITTLE: 269 max_pclk = si->ps.max_dac1_clock_16; 270 break; 271 case B_RGB24_LITTLE: 272 max_pclk = si->ps.max_dac1_clock_24; 273 break; 274 case B_RGB32_LITTLE: 275 max_pclk = si->ps.max_dac1_clock_32; 276 break; 277 default: 278 /* use fail-safe value */ 279 max_pclk = si->ps.max_dac1_clock_32; 280 break; 281 } 282 /* if some dualhead mode is active, an extra restriction might apply */ 283 if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE)) 284 max_pclk = si->ps.max_dac1_clock_32dh; 285 286 /* Make sure the requested pixelclock is within the PLL's operational limits */ 287 /* lower limit is min_pixel_vco divided by highest postscaler-factor */ 288 if (req_pclk < (si->ps.min_pixel_vco / 16.0)) 289 { 290 LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n", 291 req_pclk, (float)(si->ps.min_pixel_vco / 16.0))); 292 req_pclk = (si->ps.min_pixel_vco / 16.0); 293 } 294 /* upper limit is given by pins in combination with current active mode */ 295 if (req_pclk > max_pclk) 296 { 297 LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n", 298 req_pclk, (float)max_pclk)); 299 req_pclk = max_pclk; 300 } 301 302 /* iterate through all valid PLL postscaler settings */ 303 for (p=0x01; p < 0x20; p = p<<1) 304 { 305 /* calculate the needed VCO frequency for this postscaler setting */ 306 f_vco = req_pclk * p; 307 308 /* check if this is within range of the VCO specs */ 309 if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco)) 310 { 311 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 312 if (si->ps.ext_pll) f_vco /= 4; 313 314 /* iterate trough all valid reference-frequency postscaler settings */ 315 for (m = 7; m <= 14; m++) 316 { 317 /* check if phase-discriminator will be within operational limits */ 318 if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue; 319 320 /* calculate VCO postscaler setting for current setup.. */ 321 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); 322 323 /* ..and check for validity */ 324 if ((n < 1) || (n > 255)) continue; 325 326 /* find error in frequency this setting gives */ 327 if (si->ps.ext_pll) 328 { 329 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 330 error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p)); 331 } 332 else 333 error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p)); 334 335 /* note the setting if best yet */ 336 if (error < error_best) 337 { 338 error_best = error; 339 best[0]=m; 340 best[1]=n; 341 best[2]=p; 342 } 343 } 344 } 345 } 346 347 /* setup the scalers programming values for found optimum setting */ 348 m = best[0]; 349 n = best[1]; 350 p = best[2]; 351 352 /* log the VCO frequency found */ 353 f_vco = ((si->ps.f_ref / m) * n); 354 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 355 if (si->ps.ext_pll) f_vco *= 4; 356 357 LOG(2,("DAC: pix VCO frequency found %fMhz\n", f_vco)); 358 359 /* return the results */ 360 *calc_pclk = (f_vco / p); 361 *m_result = m; 362 *n_result = n; 363 switch(p) 364 { 365 case 1: 366 p = 0x00; 367 break; 368 case 2: 369 p = 0x01; 370 break; 371 case 4: 372 p = 0x02; 373 break; 374 case 8: 375 p = 0x03; 376 break; 377 case 16: 378 p = 0x04; 379 break; 380 } 381 *p_result = p; 382 383 /* display the found pixelclock values */ 384 LOG(2,("DAC: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", 385 req_pclk, *calc_pclk, *m_result, *n_result, *p_result)); 386 387 return B_OK; 388} 389 390/* find nearest valid system PLL setting */ 391status_t nv_dac_sys_pll_find( 392 float req_sclk, float* calc_sclk, uint8* m_result, uint8* n_result, uint8* p_result, uint8 test) 393{ 394 int m = 0, n = 0, p = 0, m_max, p_max; 395 float error, error_best = 999999999; 396 int best[3]; 397 float f_vco, discr_low, discr_high; 398 399 /* determine the max. reference-frequency postscaler setting for the 400 * current requested clock */ 401 LOG(4,("DAC: NV10/NV20/NV30 restrictions apply\n")); 402 /* set max. useable reference frequency postscaler divider factor; 403 * apparantly we would get distortions on high PLL output frequencies if 404 * we use the phase-discriminator at low frequencies */ 405 if (req_sclk > 340.0) m_max = 2; /* Fpll > 340Mhz */ 406 else if (req_sclk > 250.0) m_max = 6; /* 250Mhz < Fpll <= 340Mhz */ 407 else m_max = 14; /* Fpll < 250Mhz */ 408 409 /* set max. useable VCO output postscaler divider factor */ 410 p_max = 16; 411 /* set phase-discriminator frequency range (Mhz) (verified) */ 412 discr_low = 1.0; 413 /* (high discriminator spec is failsafe) */ 414 discr_high = 14.0; 415 416 LOG(4,("DAC: PLL reference frequency postscaler divider range is 1 - %d\n", m_max)); 417 LOG(4,("DAC: PLL VCO output postscaler divider range is 1 - %d\n", p_max)); 418 LOG(4,("DAC: PLL discriminator input frequency range is %2.2fMhz - %2.2fMhz\n", 419 discr_low, discr_high)); 420 421 /* Make sure the requested clock is within the PLL's operational limits */ 422 /* lower limit is min_system_vco divided by highest postscaler-factor */ 423 if (req_sclk < (si->ps.min_system_vco / ((float)p_max))) 424 { 425 LOG(4,("DAC: clamping sysclock: requested %fMHz, set to %fMHz\n", 426 req_sclk, (si->ps.min_system_vco / ((float)p_max)))); 427 req_sclk = (si->ps.min_system_vco / ((float)p_max)); 428 } 429 /* upper limit is given by pins */ 430 if (req_sclk > si->ps.max_system_vco) 431 { 432 LOG(4,("DAC: clamping sysclock: requested %fMHz, set to %fMHz\n", 433 req_sclk, (float)si->ps.max_system_vco)); 434 req_sclk = si->ps.max_system_vco; 435 } 436 437 /* iterate through all valid PLL postscaler settings */ 438 for (p=0x01; p <= p_max; p = p<<1) 439 { 440 /* calculate the needed VCO frequency for this postscaler setting */ 441 f_vco = req_sclk * p; 442 443 /* check if this is within range of the VCO specs */ 444 if ((f_vco >= si->ps.min_system_vco) && (f_vco <= si->ps.max_system_vco)) 445 { 446 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 447 if (si->ps.ext_pll) f_vco /= 4; 448 449 /* iterate trough all valid reference-frequency postscaler settings */ 450 for (m = 1; m <= m_max; m++) 451 { 452 /* check if phase-discriminator will be within operational limits */ 453 if (((si->ps.f_ref / m) < discr_low) || ((si->ps.f_ref / m) > discr_high)) 454 continue; 455 456 /* calculate VCO postscaler setting for current setup.. */ 457 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); 458 459 /* ..and check for validity */ 460 if ((n < 1) || (n > 255)) continue; 461 462 /* find error in frequency this setting gives */ 463 if (si->ps.ext_pll) 464 { 465 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 466 error = fabs((req_sclk / 4) - (((si->ps.f_ref / m) * n) / p)); 467 } 468 else 469 error = fabs(req_sclk - (((si->ps.f_ref / m) * n) / p)); 470 471 /* note the setting if best yet */ 472 if (error < error_best) 473 { 474 error_best = error; 475 best[0]=m; 476 best[1]=n; 477 best[2]=p; 478 } 479 } 480 } 481 } 482 483 /* setup the scalers programming values for found optimum setting */ 484 m = best[0]; 485 n = best[1]; 486 p = best[2]; 487 488 /* log the VCO frequency found */ 489 f_vco = ((si->ps.f_ref / m) * n); 490 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 491 if (si->ps.ext_pll) f_vco *= 4; 492 493 LOG(2,("DAC: sys VCO frequency found %fMhz\n", f_vco)); 494 495 /* return the results */ 496 *calc_sclk = (f_vco / p); 497 *m_result = m; 498 *n_result = n; 499 switch(p) 500 { 501 case 1: 502 p = 0x00; 503 break; 504 case 2: 505 p = 0x01; 506 break; 507 case 4: 508 p = 0x02; 509 break; 510 case 8: 511 p = 0x03; 512 break; 513 case 16: 514 p = 0x04; 515 break; 516 case 32: 517 p = 0x05; 518 break; 519 } 520 *p_result = p; 521 522 /* display the found pixelclock values */ 523 LOG(2,("DAC: sys PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", 524 req_sclk, *calc_sclk, *m_result, *n_result, *p_result)); 525 526 return B_OK; 527} 528