1/* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9#ifndef RADEON_HD_H 10#define RADEON_HD_H 11 12 13#include "lock.h" 14 15#include "radeon_reg.h" 16 17//#include "r500_reg.h" // Not used atm 18#include "avivo_reg.h" 19#include "r600_reg.h" 20#include "r700_reg.h" 21#include "evergreen_reg.h" 22#include "si_reg.h" 23#include "ni_reg.h" 24 25#include <Accelerant.h> 26#include <Drivers.h> 27#include <edid.h> 28#include <PCI.h> 29 30 31#define VENDOR_ID_ATI 0x1002 32 33// Card chipset flags 34#define CHIP_STD (1 << 0) // Standard chipset 35#define CHIP_IGP (1 << 1) // IGP chipset 36#define CHIP_MOBILE (1 << 2) // Mobile chipset 37#define CHIP_DISCREET (1 << 3) // Discreet chipset 38#define CHIP_APU (1 << 4) // APU chipset 39 40#define DEVICE_NAME "radeon_hd" 41#define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" 42 43// Used to collect EDID from boot loader 44#define EDID_BOOT_INFO "vesa_edid/v1" 45#define MODES_BOOT_INFO "vesa_modes/v1" 46 47#define RHD_POWER_ON 0 48#define RHD_POWER_RESET 1 /* off temporarily */ 49#define RHD_POWER_SHUTDOWN 2 /* long term shutdown */ 50#define RHD_POWER_UNKNOWN 3 /* initial state */ 51 52 53// Radeon Chipsets 54enum radeon_chipset { 55 RADEON_R420 = 0, //r400, Radeon X700-X850 56 RADEON_R423, 57 RADEON_RV410, 58 RADEON_RS400, 59 RADEON_RS480, 60 RADEON_RS600, 61 RADEON_RS690, 62 RADEON_RS740, 63 RADEON_RV515, 64 RADEON_R520, //r500, Radeon X1300-X1950 65 RADEON_RV530, 66 RADEON_RV560, 67 RADEON_RV570, 68 RADEON_R580, 69 RADEON_R600, //r600, Radeon HD 2000, 3000 70 RADEON_RV610, 71 RADEON_RV630, 72 RADEON_RV670, 73 RADEON_RV620, 74 RADEON_RV635, 75 RADEON_RS780, 76 RADEON_RS880, 77 RADEON_RV770, //r700, Radeon HD 4000 78 RADEON_RV730, 79 RADEON_RV710, 80 RADEON_RV740, 81 RADEON_CEDAR, //Evergreen, Radeon HD 5000 82 RADEON_REDWOOD, 83 RADEON_JUNIPER, 84 RADEON_CYPRESS, 85 RADEON_HEMLOCK, 86 RADEON_PALM, //Fusion APU (NI), Radeon HD 6000 87 RADEON_SUMO, 88 RADEON_SUMO2, 89 RADEON_CAICOS, //Nothern Islands, Radeon HD 6000 90 RADEON_TURKS, 91 RADEON_BARTS, 92 RADEON_CAYMAN, 93 RADEON_ANTILLES, 94 RADEON_LOMBOK, //Southern Islands, Radeon HD 7000 95 RADEON_CAPEVERDE, 96 RADEON_PITCAIRN, 97 RADEON_TAHITI, 98 RADEON_NEWZEALAND 99}; 100 101 102struct ring_buffer { 103 struct lock lock; 104 uint32 register_base; 105 uint32 offset; 106 uint32 size; 107 uint32 position; 108 uint32 space_left; 109 uint8* base; 110}; 111 112 113struct overlay_registers; 114 115 116struct radeon_shared_info { 117 uint32 deviceIndex; // accelerant index 118 uint32 pciID; // device pciid 119 area_id mode_list_area; // area containing display mode list 120 uint32 mode_count; 121 122 bool has_rom; // was rom mapped? 123 area_id rom_area; // area of mapped rom 124 uint32 rom_phys; // rom base location 125 uint32 rom_size; // rom size 126 uint8* rom; // cloned, memory mapped PCI ROM 127 128 display_mode current_mode; 129 uint32 bytes_per_row; 130 uint32 bits_per_pixel; 131 uint32 dpms_mode; 132 133 area_id registers_area; // area of memory mapped registers 134 uint8* status_page; 135 addr_t physical_status_page; 136 uint32 graphics_memory_size; 137 138 uint8* frame_buffer; // virtual memory mapped FB 139 area_id frame_buffer_area; // area of memory mapped FB 140 addr_t frame_buffer_phys; // card PCI BAR address of FB 141 uint32 frame_buffer_size; // FB size mapped 142 143 bool has_edid; 144 edid1_info edid_info; 145 146 struct lock accelerant_lock; 147 struct lock engine_lock; 148 149 ring_buffer primary_ring_buffer; 150 151 int32 overlay_channel_used; 152 bool overlay_active; 153 uint32 overlay_token; 154 addr_t physical_overlay_registers; 155 uint32 overlay_offset; 156 157 bool hardware_cursor_enabled; 158 sem_id vblank_sem; 159 160 uint8* cursor_memory; 161 addr_t physical_cursor_memory; 162 uint32 cursor_buffer_offset; 163 uint32 cursor_format; 164 bool cursor_visible; 165 uint16 cursor_hot_x; 166 uint16 cursor_hot_y; 167 168 char deviceName[32]; 169 uint16 chipsetID; 170 char chipsetName[16]; 171 uint32 chipsetFlags; 172 uint8 dceMajor; 173 uint8 dceMinor; 174 175 uint16 color_data[3 * 256]; // colour lookup table 176}; 177 178//----------------- ioctl() interface ---------------- 179 180// magic code for ioctls 181#define RADEON_PRIVATE_DATA_MAGIC 'rdhd' 182 183// list ioctls 184enum { 185 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 186 187 RADEON_GET_DEVICE_NAME, 188 RADEON_ALLOCATE_GRAPHICS_MEMORY, 189 RADEON_FREE_GRAPHICS_MEMORY 190}; 191 192// retrieve the area_id of the kernel/accelerant shared info 193struct radeon_get_private_data { 194 uint32 magic; // magic number 195 area_id shared_info_area; 196}; 197 198// allocate graphics memory 199struct radeon_allocate_graphics_memory { 200 uint32 magic; 201 uint32 size; 202 uint32 alignment; 203 uint32 flags; 204 uint32 buffer_base; 205}; 206 207// free graphics memory 208struct radeon_free_graphics_memory { 209 uint32 magic; 210 uint32 buffer_base; 211}; 212 213// registers 214#define R6XX_CONFIG_APER_SIZE 0x5430 // r600> 215#define OLD_CONFIG_APER_SIZE 0x0108 // <r600 216#define CONFIG_MEMSIZE 0x5428 // r600> 217 218// PCI bridge memory management 219 220// overlay 221 222#define RADEON_OVERLAY_UPDATE 0x30000 223#define RADEON_OVERLAY_TEST 0x30004 224#define RADEON_OVERLAY_STATUS 0x30008 225#define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c 226#define RADEON_OVERLAY_GAMMA_5 0x30010 227#define RADEON_OVERLAY_GAMMA_4 0x30014 228#define RADEON_OVERLAY_GAMMA_3 0x30018 229#define RADEON_OVERLAY_GAMMA_2 0x3001c 230#define RADEON_OVERLAY_GAMMA_1 0x30020 231#define RADEON_OVERLAY_GAMMA_0 0x30024 232 233struct overlay_scale { 234 uint32 _reserved0 : 3; 235 uint32 horizontal_scale_fraction : 12; 236 uint32 _reserved1 : 1; 237 uint32 horizontal_downscale_factor : 3; 238 uint32 _reserved2 : 1; 239 uint32 vertical_scale_fraction : 12; 240}; 241 242#define OVERLAY_FORMAT_RGB15 0x2 243#define OVERLAY_FORMAT_RGB16 0x3 244#define OVERLAY_FORMAT_RGB32 0x1 245#define OVERLAY_FORMAT_YCbCr422 0x8 246#define OVERLAY_FORMAT_YCbCr411 0x9 247#define OVERLAY_FORMAT_YCbCr420 0xc 248 249#define OVERLAY_MIRROR_NORMAL 0x0 250#define OVERLAY_MIRROR_HORIZONTAL 0x1 251#define OVERLAY_MIRROR_VERTICAL 0x2 252 253// The real overlay registers are written to using an update buffer 254 255struct overlay_registers { 256 uint32 buffer_rgb0; 257 uint32 buffer_rgb1; 258 uint32 buffer_u0; 259 uint32 buffer_v0; 260 uint32 buffer_u1; 261 uint32 buffer_v1; 262 // (0x18) OSTRIDE - overlay stride 263 uint16 stride_rgb; 264 uint16 stride_uv; 265 // (0x1c) YRGB_VPH - Y/RGB vertical phase 266 uint16 vertical_phase0_rgb; 267 uint16 vertical_phase1_rgb; 268 // (0x20) UV_VPH - UV vertical phase 269 uint16 vertical_phase0_uv; 270 uint16 vertical_phase1_uv; 271 // (0x24) HORZ_PH - horizontal phase 272 uint16 horizontal_phase_rgb; 273 uint16 horizontal_phase_uv; 274 // (0x28) INIT_PHS - initial phase shift 275 uint32 initial_vertical_phase0_shift_rgb0 : 4; 276 uint32 initial_vertical_phase1_shift_rgb0 : 4; 277 uint32 initial_horizontal_phase_shift_rgb0 : 4; 278 uint32 initial_vertical_phase0_shift_uv : 4; 279 uint32 initial_vertical_phase1_shift_uv : 4; 280 uint32 initial_horizontal_phase_shift_uv : 4; 281 uint32 _reserved0 : 8; 282 // (0x2c) DWINPOS - destination window position 283 uint16 window_left; 284 uint16 window_top; 285 // (0x30) DWINSZ - destination window size 286 uint16 window_width; 287 uint16 window_height; 288 // (0x34) SWIDTH - source width 289 uint16 source_width_rgb; 290 uint16 source_width_uv; 291 // (0x38) SWITDHSW - source width in 8 byte steps 292 uint16 source_bytes_per_row_rgb; 293 uint16 source_bytes_per_row_uv; 294 uint16 source_height_rgb; 295 uint16 source_height_uv; 296 overlay_scale scale_rgb; 297 overlay_scale scale_uv; 298 // (0x48) OCLRC0 - overlay color correction 0 299 uint32 brightness_correction : 8; // signed, -128 to 127 300 uint32 _reserved1 : 10; 301 uint32 contrast_correction : 9; // fixed point: 3.6 bits 302 uint32 _reserved2 : 5; 303 // (0x4c) OCLRC1 - overlay color correction 1 304 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 305 uint32 _reserved3 : 6; 306 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 307 uint32 _reserved4 : 5; 308 // (0x50) DCLRKV - destination color key value 309 uint32 color_key_blue : 8; 310 uint32 color_key_green : 8; 311 uint32 color_key_red : 8; 312 uint32 _reserved5 : 8; 313 // (0x54) DCLRKM - destination color key mask 314 uint32 color_key_mask_blue : 8; 315 uint32 color_key_mask_green : 8; 316 uint32 color_key_mask_red : 8; 317 uint32 _reserved6 : 7; 318 uint32 color_key_enabled : 1; 319 // (0x58) SCHRKVH - source chroma key high value 320 uint32 source_chroma_key_high_red : 8; 321 uint32 source_chroma_key_high_blue : 8; 322 uint32 source_chroma_key_high_green : 8; 323 uint32 _reserved7 : 8; 324 // (0x5c) SCHRKVL - source chroma key low value 325 uint32 source_chroma_key_low_red : 8; 326 uint32 source_chroma_key_low_blue : 8; 327 uint32 source_chroma_key_low_green : 8; 328 uint32 _reserved8 : 8; 329 // (0x60) SCHRKEN - source chroma key enable 330 uint32 _reserved9 : 24; 331 uint32 source_chroma_key_red_enabled : 1; 332 uint32 source_chroma_key_blue_enabled : 1; 333 uint32 source_chroma_key_green_enabled : 1; 334 uint32 _reserved10 : 5; 335 // (0x64) OCONFIG - overlay configuration 336 uint32 _reserved11 : 3; 337 uint32 color_control_output_mode : 1; 338 uint32 yuv_to_rgb_bypass : 1; 339 uint32 _reserved12 : 11; 340 uint32 gamma2_enabled : 1; 341 uint32 _reserved13 : 1; 342 uint32 select_pipe : 1; 343 uint32 slot_time : 8; 344 uint32 _reserved14 : 5; 345 // (0x68) OCOMD - overlay command 346 uint32 overlay_enabled : 1; 347 uint32 active_field : 1; 348 uint32 active_buffer : 2; 349 uint32 test_mode : 1; 350 uint32 buffer_field_mode : 1; 351 uint32 _reserved15 : 1; 352 uint32 tv_flip_field_enabled : 1; 353 uint32 _reserved16 : 1; 354 uint32 tv_flip_field_parity : 1; 355 uint32 source_format : 4; 356 uint32 ycbcr422_order : 2; 357 uint32 _reserved18 : 1; 358 uint32 mirroring_mode : 2; 359 uint32 _reserved19 : 13; 360 361 uint32 _reserved20; 362 363 uint32 start_0y; 364 uint32 start_1y; 365 uint32 start_0u; 366 uint32 start_0v; 367 uint32 start_1u; 368 uint32 start_1v; 369 uint32 _reserved21[6]; 370#if 0 371 // (0x70) AWINPOS - alpha blend window position 372 uint32 awinpos; 373 // (0x74) AWINSZ - alpha blend window size 374 uint32 awinsz; 375 376 uint32 _reserved21[10]; 377#endif 378 379 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 380 // the next two registers switch the usual Y/RGB vs. UV order) 381 uint16 horizontal_scale_uv; 382 uint16 horizontal_scale_rgb; 383 // (0xa4) UVSCALEV - vertical downscale 384 uint16 vertical_scale_uv; 385 uint16 vertical_scale_rgb; 386 387 uint32 _reserved22[86]; 388 389 // (0x200) polyphase filter coefficients 390 uint16 vertical_coefficients_rgb[128]; 391 uint16 horizontal_coefficients_rgb[128]; 392 393 uint32 _reserved23[64]; 394 395 // (0x500) 396 uint16 vertical_coefficients_uv[128]; 397 uint16 horizontal_coefficients_uv[128]; 398}; 399 400 401struct hardware_status { 402 uint32 interrupt_status_register; 403 uint32 _reserved0[3]; 404 void* primary_ring_head_storage; 405 uint32 _reserved1[3]; 406 void* secondary_ring_0_head_storage; 407 void* secondary_ring_1_head_storage; 408 uint32 _reserved2[2]; 409 void* binning_head_storage; 410 uint32 _reserved3[3]; 411 uint32 store[1008]; 412}; 413 414#endif /* RADEON_HD_H */ 415