1/* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Apsed; 8 Rudolf Cornelissen 10/2002-6/2008. 9*/ 10 11#ifndef DRIVERINTERFACE_H 12#define DRIVERINTERFACE_H 13 14#include <Accelerant.h> 15#include "video_overlay.h" 16#include <Drivers.h> 17#include <PCI.h> 18#include <OS.h> 19 20#define DRIVER_PREFIX "nvidia_gpgpu" 21#define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x" 22 23/* 24 Internal driver state (also for sharing info between driver and accelerant) 25*/ 26#if defined(__cplusplus) 27extern "C" { 28#endif 29 30typedef struct { 31 sem_id sem; 32 int32 ben; 33} benaphore; 34 35#define INIT_BEN(x) x.sem = create_sem(0, "NV_GPGPU "#x" benaphore"); x.ben = 0; 36#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 37#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 38#define DELETE_BEN(x) delete_sem(x.sem); 39 40 41#define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ 42 43/* dualhead extensions to flags */ 44#define DUALHEAD_OFF (0<<6) 45#define DUALHEAD_CLONE (1<<6) 46#define DUALHEAD_ON (2<<6) 47#define DUALHEAD_SWITCH (3<<6) 48#define DUALHEAD_BITS (3<<6) 49#define DUALHEAD_CAPABLE (1<<8) 50#define TV_BITS (3<<9) 51#define TV_MON (0<<9 52#define TV_PAL (1<<9) 53#define TV_NTSC (2<<9) 54#define TV_CAPABLE (1<<11) 55#define TV_VIDEO (1<<12) 56#define TV_PRIMARY (1<<13) 57 58#define SKD_MOVE_CURSOR 0x00000001 59#define SKD_PROGRAM_CLUT 0x00000002 60#define SKD_SET_START_ADDR 0x00000004 61#define SKD_SET_CURSOR 0x00000008 62#define SKD_HANDLER_INSTALLED 0x80000000 63 64enum { 65 NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 66 NV_GET_PCI, 67 NV_SET_PCI, 68 NV_DEVICE_NAME, 69 NV_RUN_INTERRUPTS, 70 NV_ISA_OUT, 71 NV_ISA_IN 72}; 73 74/* card_type in order of date of NV chip design */ 75enum { 76 NV40 = 0, 77 NV41, 78 NV43, 79 NV44, 80 NV45, 81 G70, 82 G71, 83 G72, 84 G73, 85 G80, 86 G84, 87 G86 88}; 89 90/* card_arch in order of date of NV chip design */ 91enum { 92 NV40A = 0, 93 NV50A 94}; 95 96/* handles to pre-defined engine commands */ 97#define NV_ROP5_SOLID 0x00000000 /* 2D */ 98#define NV_IMAGE_BLACK_RECTANGLE 0x00000001 /* 2D/3D */ 99#define NV_IMAGE_PATTERN 0x00000002 /* 2D */ 100#define NV_SCALED_IMAGE_FROM_MEMORY 0x00000003 /* 2D */ 101#define NV_TCL_PRIMITIVE_3D 0x00000004 /* 3D */ //2007 102#define NV4_SURFACE 0x00000010 /* 2D */ 103#define NV10_CONTEXT_SURFACES_2D 0x00000010 /* 2D */ 104#define NV_IMAGE_BLIT 0x00000011 /* 2D */ 105#define NV12_IMAGE_BLIT 0x00000011 /* 2D */ 106/* fixme: 107 * never use NV3_GDI_RECTANGLE_TEXT for DMA acceleration: 108 * There's a hardware fault in the input->output colorspace conversion here. 109 * Besides, in NV40 and up this command nolonger exists. Both 'facts' are confirmed 110 * by testing. 111 */ 112//#define NV3_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 113#define NV4_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 114#define NV1_RENDER_SOLID_LIN 0x00000016 /* 2D: unused */ 115 116//----------------------------------------------------------------------------------- 117/* safety byte-offset from end of cardRAM for preventing acceleration engine crashes 118 * caused by the existance of DMA engine command buffers in cardRAM and/or fifo 119 * channel engine command re-assigning on-the-fly */ 120 121/* NV40 and higher notes: 122 * - we need at least 416kB distance from the DMA command buffer: 123 * If you get too close to the DMA command buffer on NV40 and NV43 at least (both 124 * confirmed), the source DMA instance will mess-up for at least engine command 125 * NV_IMAGE_BLIT and NV12_IMAGE_BLIT; 126 * - we need at least ???kB distance from the end of RAM for fifo-reassigning 'bug' 127 * (fixme: unknown yet because fifo assignment switching isn't used here atm); 128 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 129#define NV40_PLUS_OFFSET 512 * 1024 130 131/* fifo re-assigning bug definition: 132 * if the fifo assignment is changed while at the same time card memory in the 133 * dangerous region is being accessed by some application, the engine will crash. 134 * This bug applies for both PIO and DMA mode acceleration! */ 135 136/* source-DMA instance bug definition: 137 * if card memory in the dangerous region is being accessed by some application while 138 * a DMA command buffer exists in the same memory (though in a different place), 139 * the engine will crash. */ 140//----------------------------------------------------------------------------------- 141 142/* internal used info on overlay buffers */ 143typedef struct { 144 uint16 slopspace; 145 uint32 size; 146} int_buf_info; 147 148typedef struct { // apsed, see comments in nv.settings 149 // for driver 150 char accelerant[B_FILE_NAME_LENGTH]; 151 char primary[B_FILE_NAME_LENGTH]; 152 bool dumprom; 153 // for accelerant 154 uint32 logmask; 155 uint32 memory; 156 bool usebios; 157 bool hardcursor; 158 bool switchhead; 159 bool pgm_panel; 160 bool force_sync; 161 bool force_ws; 162 uint32 gpu_clk; 163 uint32 ram_clk; 164} nv_settings; 165 166/* shared info */ 167typedef struct { 168 /* a few ID things */ 169 uint16 vendor_id; /* PCI vendor ID, from pci_info */ 170 uint16 device_id; /* PCI device ID, from pci_info */ 171 uint8 revision; /* PCI device revsion, from pci_info */ 172 uint8 bus; /* PCI bus number, from pci_info */ 173 uint8 device; /* PCI device number on bus, from pci_info */ 174 uint8 function; /* PCI function number in device, from pci_info */ 175 176 /* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */ 177 bool accelerant_in_use; 178 179 /* bug workaround for 4.5.0 */ 180 uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ 181 uint32 * clone_bugfix_regs; 182 183 /*memory mappings*/ 184 area_id regs_area; /* Kernel's area_id for the memory mapped registers. 185 It will be cloned into the accelerant's address 186 space. */ 187 188 area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ 189 area_id unaligned_dma_area; /* Area assigned for DMA. It will be (partially) mapped to an 190 aligned area using MTRR-WC. */ 191 area_id dma_area; /* Aligned area assigned for DMA. The addresses are shared with all teams. */ 192 193 void *framebuffer; /* As viewed from virtual memory */ 194 void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ 195 void *dma_buffer; /* As viewed from virtual memory */ 196 void *dma_buffer_pci; /* As viewed from the PCI bus (for DMA) */ 197 198 /*screenmode list*/ 199 area_id mode_area; /* Contains the list of display modes the driver supports */ 200 uint32 mode_count; /* Number of display modes in the list */ 201 202 /*flags - used by driver*/ 203 uint32 flags; 204 205 /*vblank semaphore*/ 206 sem_id vblank; /* The vertical blank semaphore. Ownership will be 207 transfered to the team opening the device first */ 208 /*cursor information*/ 209 struct { 210 uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ 211 uint16 hot_y; /* is 0,0 */ 212 uint16 x; /* The location of the cursor hot spot on the */ 213 uint16 y; /* desktop */ 214 uint16 width; /* Width and height of the cursor shape (always 16!) */ 215 uint16 height; 216 bool is_visible; /* Is the cursor currently displayed? */ 217 bool dh_right; /* Is cursor on right side of stretched screen? */ 218 } cursor; 219 220 /*colour lookup table*/ 221 uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ 222 223 /*more display mode stuff*/ 224 display_mode dm; /* current display mode configuration: head1 */ 225 uint32 dpms_flags; /* current DPMS mode */ 226 bool acc_mode; /* signals (non)accelerated mode */ 227 bool crtc_switch_mode; /* signals dualhead switch mode if panels are used */ 228 229 /*frame buffer config - for BDirectScreen*/ 230 frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ 231 accelerant_device_info adi; /* as returned by hook GET_ACCELERANT_DEVICE_INFO */ 232 233 /*acceleration engine*/ 234 struct { 235 uint32 count; /* last dwgsync slot used */ 236 uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ 237 benaphore lock; /* for serializing access to the acc engine */ 238 struct { 239 uint32 handle[0x08]; /* FIFO channel's cmd handle for the owning cmd */ 240 uint32 ch_ptr[0x20]; /* cmd handle's ptr to it's assigned FIFO ch (if any) */ 241 } fifo; 242 struct { 243 uint32 put; /* last 32-bit-word adress given to engine to exec. to */ 244 uint32 current; /* first free 32-bit-word adress in buffer */ 245 uint32 free; /* nr. of useable free 32-bit words remaining in buffer */ 246 uint32 max; /* command buffer's useable size in 32-bit words */ 247 } dma; 248 struct { 249 uint32 clones; /* clone 'number' (mask, slot) (one bit per clone) */ 250 uint32 reload; /* reload state and surfaces (one bit per clone) */ 251 uint32 newmode; /* re-allocate all buffers (one bit per clone) */ 252 //fixme: memory stuff needs to be expanded (shared texture allocation?) 253 uint32 mem_low; /* ptr to first free mem adress: cardmem local offset */ 254 uint32 mem_high; /* ptr to last free mem adress: cardmem local offset */ 255 bool mode_changing; /* a mode-change is in progress (set/clear by 2D drv) */ 256 } threeD; 257 } engine; 258 259 struct 260 { 261 /* specialised registers for card initialisation read from NV BIOS (pins) */ 262 263 /* general card information */ 264 uint32 card_type; /* see card_type enum above */ 265 uint32 card_arch; /* see card_arch enum above */ 266 bool laptop; /* mobile chipset or not ('internal' flatpanel!) */ 267 bool slaved_tmds1; /* external TMDS encoder active on CRTC1 */ 268 bool slaved_tmds2; /* external TMDS encoder active on CRTC2 */ 269 bool master_tmds1; /* on die TMDS encoder active on CRTC1 */ 270 bool master_tmds2; /* on die TMDS encoder active on CRTC2 */ 271 bool tmds1_active; /* found panel on CRTC1 that is active */ 272 bool tmds2_active; /* found panel on CRTC2 that is active */ 273 display_timing p1_timing; /* 'modeline' fetched for panel 1 */ 274 display_timing p2_timing; /* 'modeline' fetched for panel 2 */ 275 float panel1_aspect; /* panel's aspect ratio */ 276 float panel2_aspect; /* panel's aspect ratio */ 277 bool crtc2_prim; /* using CRTC2 as primary CRTC */ 278 bool i2c_bus0; /* we have a wired I2C bus 0 on board */ 279 bool i2c_bus1; /* we have a wired I2C bus 1 on board */ 280 bool i2c_bus2; /* we have a wired I2C bus 2 on board */ 281 bool i2c_bus3; /* we have a wired I2C bus 3 on board */ 282 uint8 monitors; /* output devices connection matrix */ 283 bool int_assigned; /* card has a useable INT assigned to it */ 284 status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ 285 286 /* PINS */ 287 float f_ref; /* PLL reference-oscillator frequency (Mhz) */ 288 bool ext_pll; /* the extended PLL contains more dividers */ 289 uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ 290 uint32 min_system_vco; 291 uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ 292 uint32 min_pixel_vco; 293 uint32 max_video_vco; /* dac2 PLL VCO limits (Mhz) */ 294 uint32 min_video_vco; 295 uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ 296 uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */ 297 uint32 max_dac1_clock; /* dac1 limits (Mhz) */ 298 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ 299 uint32 max_dac1_clock_16; 300 uint32 max_dac1_clock_24; 301 uint32 max_dac1_clock_32; 302 uint32 max_dac1_clock_32dh; 303 uint32 max_dac2_clock; /* dac2 limits (Mhz) */ 304 uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ 305 uint32 max_dac2_clock_16; 306 uint32 max_dac2_clock_24; 307 uint32 max_dac2_clock_32; 308 uint32 max_dac2_clock_32dh; 309 bool secondary_head; /* presence of functions */ 310 bool primary_dvi; 311 bool secondary_dvi; 312 uint32 memory_size; /* memory (in bytes) */ 313 } ps; 314 315 /* mirror of the ROM (copied in driver, because may not be mapped permanently) */ 316 uint8 rom_mirror[65536]; 317 318 /* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */ 319 nv_settings settings; 320 321} shared_info; 322 323/* Read or write a value in PCI configuration space */ 324typedef struct { 325 uint32 magic; /* magic number to make sure the caller groks us */ 326 uint32 offset; /* Offset to read/write */ 327 uint32 size; /* Number of bytes to transfer */ 328 uint32 value; /* The value read or written */ 329} nv_get_set_pci; 330 331/* Enable or Disable CRTC (1,2) interrupts */ 332typedef struct { 333 uint32 magic; /* magic number to make sure the caller groks us */ 334 bool crtc; /* adressed CRTC */ 335 bool do_it; /* state to set */ 336} nv_set_vblank_int; 337 338/* Retrieve the area_id of the kernel/accelerant shared info */ 339typedef struct { 340 uint32 magic; /* magic number to make sure the caller groks us */ 341 area_id shared_info_area; /* area_id containing the shared information */ 342} nv_get_private_data; 343 344/* Retrieve the device name. Usefull for when we have a file handle, but want 345to know the device name (like when we are cloning the accelerant) */ 346typedef struct { 347 uint32 magic; /* magic number to make sure the caller groks us */ 348 char *name; /* The name of the device, less the /dev root */ 349} nv_device_name; 350 351/* Read or write a value in ISA I/O space */ 352typedef struct { 353 uint32 magic; /* magic number to make sure the caller groks us */ 354 uint16 adress; /* Offset to read/write */ 355 uint8 size; /* Number of bytes to transfer */ 356 uint16 data; /* The value read or written */ 357} nv_in_out_isa; 358 359enum { 360 361 _WAIT_FOR_VBLANK = (1 << 0) 362}; 363 364#if defined(__cplusplus) 365} 366#endif 367 368 369#endif 370