1/*
2 * Copyright 2003, Thomas Kurschel. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Copyright 2006-2013 Haiku, Inc. All rights reserved.
6 * Distributed under the terms of the MIT License.
7 *
8 * Authors:
9 *	Thomas Kurschel
10 *	Bill Randle, billr@neocat.org
11 */
12#ifndef _EDID_RAW_H
13#define _EDID_RAW_H
14
15
16#include "bendian_bitfield.h"
17
18
19/*!	Raw EDID data block.
20
21	Raw data are packed in a really weird way. Never even
22	think about using it directly, instead translate it via decode_edid()
23	first.
24*/
25
26#define EDID1_NUM_DETAILED_MONITOR_DESC 4
27#define EDID1_NUM_STD_TIMING 8
28#define EDID1_NUM_EXTRA_STD_TIMING 6
29#define EDID1_EXTRA_STRING_LEN 13
30#define EDID1_NUM_EXTRA_WHITEPOINTS 2
31
32
33// header
34typedef struct _PACKED {
35	int8 pad[8];		// contains 0, -1, -1, -1, -1, -1, -1, 0
36} edid1_header_raw;
37
38
39// vendor info
40typedef struct _PACKED {
41	BBITFIELD8_3 (		// manufacturer
42		pad : 1,
43		c1 : 5,			// add '@' to get ascii
44		c2_high : 2
45	);
46	BBITFIELD8_2 (
47		c2_low : 3,
48		c3 : 5
49	);
50	uint16 prod_id;
51	uint32 serial;
52	uint8 week;
53	uint8 year;			// x+1990
54} edid1_vendor_raw;
55
56
57// version info
58typedef struct _PACKED {
59	uint8 version;
60	uint8 revision;
61} edid1_version_raw;
62
63
64// display info
65typedef struct _PACKED {
66	BBITFIELD8_7 (
67		input_type : 1,		// 1 : digital
68		input_voltage : 2,	// 0=0.7V/0.3V, 1=0.714V/0.286,
69							// 2=1V/0.4V, 3=0.7V/0V
70		setup : 1,			// true if voltage configurable
71		sep_sync : 1,
72		comp_sync : 1,
73		sync_on_green : 1,
74		sync_serr : 1
75	);
76	uint8 h_size;
77	uint8 v_size;
78	uint8 gamma;	// (x+100)/100
79	BBITFIELD8_7 (
80		dpms_standby : 1,
81		dpms_suspend : 1,
82		dpms_off : 1,
83		display_type : 2,	// 0=mono, 1=rgb, 2=multicolour
84		// since EDID version 1.1
85		std_colour_space : 1,
86		preferred_timing_mode : 1,
87		gtf_supported : 1
88	);
89	BBITFIELD8_4 (		// low bits of red_x etc.
90		red_x_low : 2,
91		red_y_low : 2,
92		green_x_low : 2,
93		green_y_low : 2
94	);
95	BBITFIELD8_4 (
96		blue_x_low : 2,
97		blue_y_low : 2,
98		white_x_low : 2,
99		white_y_low : 2
100	);
101	uint8 red_x;		// all colours are 0.10 fixed point
102	uint8 red_y;
103	uint8 green_x;
104	uint8 green_y;
105	uint8 blue_x;
106	uint8 blue_y;
107	uint8 white_x;
108	uint8 white_y;
109} edid1_display_raw;
110
111
112// raw standard timing data
113typedef union _PACKED {
114	struct _PACKED {
115		uint8 h_size;		// (x+31)*8
116		BBITFIELD8_2 (
117			ratio : 2,		// 0=1:1, 1=3/4, 2=4/5, 3=9/16
118			refresh : 6		// (x+60)
119		);
120	} timing;
121	uint16 id;
122} edid1_std_timing_raw;
123
124
125// list of supported fixed timings
126typedef struct _PACKED {
127	BBITFIELD8_8 (
128		res_720x400x70 : 1,
129		res_720x400x88 : 1,
130		res_640x480x60 : 1,
131		res_640x480x67 : 1,
132		res_640x480x72 : 1,
133		res_640x480x75 : 1,
134		res_800x600x56 : 1,
135		res_800x600x60 : 1
136	);
137	BBITFIELD8_8 (
138		res_800x600x72 : 1,
139		res_800x600x75 : 1,
140		res_832x624x75 : 1,
141		res_1024x768x87i : 1,
142		res_1024x768x60 : 1,
143		res_1024x768x70 : 1,
144		res_1024x768x75 : 1,
145		res_1280x1024x75 : 1
146	);
147	BBITFIELD8_2 (
148		res_1152x870x75 : 1,
149		pad : 7
150	);
151} edid1_established_timing;
152
153
154// types of detailed monitor description
155enum {
156	EDID1_SERIAL_NUMBER = 0xff,
157	EDID1_ASCII_DATA = 0xfe,
158	EDID1_MONITOR_RANGES = 0xfd,
159	EDID1_MONITOR_NAME = 0xfc,
160	EDID1_ADD_COLOUR_POINTER = 0xfb,
161	EDID1_ADD_STD_TIMING = 0xfa,
162	EDID1_IS_DETAILED_TIMING = 1
163};
164
165
166// monitor frequency range
167typedef struct _PACKED {
168	uint8 min_v;
169	uint8 max_v;
170	uint8 min_h;
171	uint8 max_h;
172	uint8 max_clock;	// in 10 MHz (!)
173} edid1_monitor_range;
174
175
176// additional whitepoint
177typedef struct _PACKED {
178	uint8 index1;
179	BBITFIELD8_3 (
180		pad1 : 4,
181		white_x1_low : 2,
182		white_y1_low : 2
183	);
184	uint8 white_x1;
185	uint8 white_y1;
186	uint8 gamma1;	// (x+100)/100
187	uint8 index2;
188	BBITFIELD8_3 (
189		pad2 : 4,
190		white_x2_low : 2,
191		white_y2_low : 2
192	);
193	uint8 white_x2;
194	uint8 white_y2;
195	uint8 gamma2;	// (x+100)/100
196} edid1_whitepoint_raw;
197
198
199// detailed timing description
200typedef struct _PACKED {
201	uint16 pixel_clock; // in 10 kHz (!)
202	uint8 h_active;
203	uint8 h_blank;
204	BBITFIELD8_2 (
205		h_active_high : 4,
206		h_blank_high : 4
207	);
208	uint8 v_active;
209	uint8 v_blank;
210	BBITFIELD8_2 (
211		v_active_high : 4,
212		v_blank_high : 4
213	);
214	uint8 h_sync_off;
215	uint8 h_sync_width;
216	BBITFIELD8_2 (
217		v_sync_off : 4,
218		v_sync_width : 4
219	);
220	BBITFIELD8_4 (
221		h_sync_off_high : 2,
222		h_sync_width_high : 2,
223		v_sync_off_high : 2,
224		v_sync_width_high : 2
225	);
226	uint8 h_size;
227	uint8 v_size;
228	BBITFIELD8_2 (
229		h_size_high : 4,
230		v_size_high : 4
231	);
232	uint8 h_border;
233	uint8 v_border;
234	BBITFIELD8_5 (
235		interlaced : 1,
236		stereo : 2,		// upper bit set - left on sync
237						// lower bit set - right on sync
238		sync : 2,
239		misc : 2,
240		stereo_il : 1
241	);
242} edid1_detailed_timing_raw;
243
244
245// detailed monitor description
246typedef union _PACKED {
247	edid1_detailed_timing_raw detailed_timing;
248	struct _PACKED {
249		uint8 zero_0[3];
250		uint8 monitor_desc_type;
251		uint8 zero_4;
252		union _PACKED {
253			uint8 serial_number[EDID1_EXTRA_STRING_LEN];
254			uint8 ascii_data[EDID1_EXTRA_STRING_LEN];
255			uint8 monitor_name[EDID1_EXTRA_STRING_LEN];
256			edid1_monitor_range monitor_range;
257			edid1_whitepoint_raw whitepoint;
258			edid1_std_timing_raw std_timing[EDID1_NUM_EXTRA_STD_TIMING];
259		} data;
260	} extra;
261} edid1_detailed_monitor_raw;
262
263
264// raw EDID data
265// everything is packed data, mixture of little endian and big endian
266// and a bit brain dead overall - nothing your dad would be proud of
267typedef struct _PACKED {
268	edid1_header_raw header; 						// 8 bytes
269	edid1_vendor_raw vendor;						// 10 bytes
270	edid1_version_raw version;						// 2 bytes
271	edid1_display_raw display;						// 15 bytes
272	edid1_established_timing established_timing;	// 3 bytes
273	edid1_std_timing_raw std_timing[EDID1_NUM_STD_TIMING];
274													// 8 a 2 bytes -> 16 bytes
275
276	// since EDID version 1.2
277	edid1_detailed_monitor_raw detailed_monitor[EDID1_NUM_DETAILED_MONITOR_DESC];
278													// 4 a 18 bytes -> 72 bytes
279
280	uint8 num_sections; 							// 1 byte
281	uint8 check_sum;								// 1 byte
282} edid1_raw;										// total: 128 bytes
283
284#endif
285