1/* 2 * Copyright 2005-2007, Axel Dörfler, axeld@pinc-software.de. All rights reserved. 3 * Copyright 2002-04, Thomas Kurschel. All rights reserved. 4 * 5 * Distributed under the terms of the MIT License. 6 */ 7#ifndef _IDE_PCI_H 8#define _IDE_PCI_H 9 10/* 11 IDE adapter library 12 13 Module to simplify writing an IDE adapter driver. 14 15 The interface is not very abstract, i.e. the actual driver is 16 free to access any controller or channel data of this library. 17*/ 18 19 20#include <bus/PCI.h> 21#include <bus/IDE.h> 22#include <ide_types.h> 23#include <device_manager.h> 24 25 26// one Physical Region Descriptor (PRD) 27// (one region must not cross 64K boundary; 28// the PRD table must not cross a 64K boundary) 29typedef struct prd_entry { 30 uint32 address; // physical address of block (must be even) 31 uint16 count; // size of block, 0 stands for 65536 (must be even) 32 uint8 res6; 33 LBITFIELD8_2( 34 res7_0 : 7, 35 EOT : 1 // 1 for last entry 36 ); 37} prd_entry; 38 39// IDE bus master command register 40#define IDE_BM_COMMAND_START_STOP 0x01 41#define IDE_BM_COMMAND_READ_FROM_DEVICE 0x08 42 43// IDE bus master status register 44#define IDE_BM_STATUS_ACTIVE 0x01 45#define IDE_BM_STATUS_ERROR 0x02 46#define IDE_BM_STATUS_INTERRUPT 0x04 47#define IDE_BM_STATUS_MASTER_DMA 0x20 48#define IDE_BM_STATUS_SLAVE_DMA 0x40 49#define IDE_BM_STATUS_SIMPLEX_DMA 0x80 50 51// offset of bus master registers 52enum { 53 IDE_BM_COMMAND_REG = 0, 54 IDE_BM_STATUS_REG = 2, 55 IDE_BM_PRDT_ADDRESS = 4 56 // offset of PRDT register; content must be dword-aligned 57}; 58 59// bit mask in class_api of PCI configuration 60// (for adapters that can run in compatability mode) 61enum { 62 IDE_API_PRIMARY_NATIVE = 1, // primary channel is in native mode 63 IDE_API_PRIMARY_FIXED = 2, // primary channel can be switched to native mode 64 IDE_API_SECONDARY_NATIVE = 4, // secondary channel is in native mode 65 IDE_API_SECONDARY_FIXED = 8 // secondary channel can be switched to native mode 66}; 67 68 69// (maximum) size of S/G table 70// there are so many restrictions that we want to keep it inside one page 71// to be sure that we fulfill them all 72#define IDE_ADAPTER_MAX_SG_COUNT (B_PAGE_SIZE / sizeof( prd_entry )) 73 74 75// channel node items 76// io address of command block (uint16) 77#define IDE_ADAPTER_COMMAND_BLOCK_BASE "ide_adapter/command_block_base" 78// io address of control block (uint16) 79#define IDE_ADAPTER_CONTROL_BLOCK_BASE "ide_adapter/control_block_base" 80// interrupt number (uint8) 81// can also be defined in controller node if both channels use same IRQ! 82#define IDE_ADAPTER_INTNUM "ide_adapter/irq" 83// 0 if primary channel, 1 if secondary channel, 2 if tertiary, ... (uint8) 84#define IDE_ADAPTER_CHANNEL_INDEX "ide_adapter/channel_index" 85 86// controller node items 87// io address of bus master registers (uint16) 88#define IDE_ADAPTER_BUS_MASTER_BASE "ide_adapter/bus_master_base" 89 90 91// info about one channel 92typedef struct ide_adapter_channel_info { 93 pci_device_module_info *pci; 94 pci_device *device; 95 96 uint16 command_block_base; // io address command block 97 uint16 control_block_base; // io address control block 98 uint16 bus_master_base; 99 int intnum; // interrupt number 100 101 uint32 lost; // != 0 if device got removed, i.e. if it must not 102 // be accessed anymore 103 104 ide_channel ideChannel; 105 device_node *node; 106 107 int32 (*inthand)( void *arg ); 108 109 area_id prd_area; 110 prd_entry *prdt; 111 uint32 prdt_phys; 112 uint32 dmaing; 113} ide_adapter_channel_info; 114 115 116// info about controller 117typedef struct ide_adapter_controller_info { 118 pci_device_module_info *pci; 119 pci_device *device; 120 121 uint16 bus_master_base; 122 123 uint32 lost; // != 0 if device got removed, i.e. if it must not 124 // be accessed anymore 125 126 device_node *node; 127} ide_adapter_controller_info; 128 129 130// interface of IDE adapter library 131typedef struct { 132 module_info info; 133 134 void (*set_channel)(ide_adapter_channel_info *channel, 135 ide_channel ideChannel); 136 137 // function calls that can be forwarded from actual driver 138 status_t (*write_command_block_regs)(ide_adapter_channel_info *channel, 139 ide_task_file *tf, ide_reg_mask mask); 140 status_t (*read_command_block_regs)(ide_adapter_channel_info *channel, 141 ide_task_file *tf, ide_reg_mask mask); 142 143 uint8 (*get_altstatus) (ide_adapter_channel_info *channel); 144 status_t (*write_device_control) (ide_adapter_channel_info *channel, uint8 val); 145 146 status_t (*write_pio)(ide_adapter_channel_info *channel, uint16 *data, int count, bool force_16bit); 147 status_t (*read_pio)(ide_adapter_channel_info *channel, uint16 *data, int count, bool force_16bit); 148 149 status_t (*prepare_dma)(ide_adapter_channel_info *channel, const physical_entry *sg_list, 150 size_t sg_list_count, bool to_device); 151 status_t (*start_dma)(ide_adapter_channel_info *channel); 152 status_t (*finish_dma)(ide_adapter_channel_info *channel); 153 154 // default functions that should be replaced by a more specific version 155 // (copy them from source code of this library and modify them at will) 156 int32 (*inthand)(void *arg); 157 158 // functions that must be called by init/uninit etc. of channel driver 159 status_t (*init_channel)(device_node *node, 160 ide_adapter_channel_info **cookie, size_t total_data_size, 161 int32 (*inthand)(void *arg)); 162 void (*uninit_channel)(ide_adapter_channel_info *channel); 163 void (*channel_removed)(ide_adapter_channel_info *channel); 164 165 // publish channel node 166 status_t (*publish_channel)(device_node *controller_node, 167 const char *channel_module_name, uint16 command_block_base, 168 uint16 control_block_base, uint8 intnum, bool can_dma, 169 uint8 channel_index, const char *name, 170 const io_resource *resources, device_node **node); 171 // verify channel configuration and publish node on success 172 status_t (*detect_channel)(pci_device_module_info *pci, pci_device *pciDevice, 173 device_node *controller_node, const char *channel_module_name, 174 bool controller_can_dma, uint16 command_block_base, 175 uint16 control_block_base, uint16 bus_master_base, 176 uint8 intnum, uint8 channel_index, const char *name, 177 device_node **node, bool supports_compatibility_mode); 178 179 // functions that must be called by init/uninit etc. of controller driver 180 status_t (*init_controller)(device_node *node, 181 ide_adapter_controller_info **cookie, size_t total_data_size); 182 void (*uninit_controller)(ide_adapter_controller_info *controller); 183 void (*controller_removed)(ide_adapter_controller_info *controller); 184 185 // publish controller node 186 status_t (*publish_controller)(device_node *parent, uint16 bus_master_base, 187 io_resource *resources, const char *controller_driver, 188 const char *controller_driver_type, const char *controller_name, 189 bool can_dma, bool can_cq, uint32 dma_alignment, uint32 dma_boundary, 190 uint32 max_sg_block_size, device_node **node); 191 // verify controller configuration and publish node on success 192 status_t (*detect_controller)(pci_device_module_info *pci, pci_device *pciDevice, 193 device_node *parent, uint16 bus_master_base, 194 const char *controller_driver, const char *controller_driver_type, 195 const char *controller_name, bool can_dma, bool can_cq, 196 uint32 dma_alignment, uint32 dma_boundary, uint32 max_sg_block_size, 197 device_node **node); 198 // standard master probe for controller that registers controller and channel nodes 199 status_t (*probe_controller)(device_node *parent, const char *controller_driver, 200 const char *controller_driver_type, const char *controller_name, 201 const char *channel_module_name, bool can_dma, bool can_cq, 202 uint32 dma_alignment, uint32 dma_boundary, uint32 max_sg_block_size, 203 bool supports_compatibility_mode); 204} ide_adapter_interface; 205 206 207#define IDE_ADAPTER_MODULE_NAME "generic/ide_adapter/v1" 208 209#endif /* _IDE_PCI_H */ 210