1/* Allocate registers within a basic block, for GNU compiler. 2 Copyright (C) 1987, 88, 91, 93-98, 1999 Free Software Foundation, Inc. 3 4This file is part of GNU CC. 5 6GNU CC is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 2, or (at your option) 9any later version. 10 11GNU CC is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16You should have received a copy of the GNU General Public License 17along with GNU CC; see the file COPYING. If not, write to 18the Free Software Foundation, 59 Temple Place - Suite 330, 19Boston, MA 02111-1307, USA. */ 20 21 22/* Allocation of hard register numbers to pseudo registers is done in 23 two passes. In this pass we consider only regs that are born and 24 die once within one basic block. We do this one basic block at a 25 time. Then the next pass allocates the registers that remain. 26 Two passes are used because this pass uses methods that work only 27 on linear code, but that do a better job than the general methods 28 used in global_alloc, and more quickly too. 29 30 The assignments made are recorded in the vector reg_renumber 31 whose space is allocated here. The rtl code itself is not altered. 32 33 We assign each instruction in the basic block a number 34 which is its order from the beginning of the block. 35 Then we can represent the lifetime of a pseudo register with 36 a pair of numbers, and check for conflicts easily. 37 We can record the availability of hard registers with a 38 HARD_REG_SET for each instruction. The HARD_REG_SET 39 contains 0 or 1 for each hard reg. 40 41 To avoid register shuffling, we tie registers together when one 42 dies by being copied into another, or dies in an instruction that 43 does arithmetic to produce another. The tied registers are 44 allocated as one. Registers with different reg class preferences 45 can never be tied unless the class preferred by one is a subclass 46 of the one preferred by the other. 47 48 Tying is represented with "quantity numbers". 49 A non-tied register is given a new quantity number. 50 Tied registers have the same quantity number. 51 52 We have provision to exempt registers, even when they are contained 53 within the block, that can be tied to others that are not contained in it. 54 This is so that global_alloc could process them both and tie them then. 55 But this is currently disabled since tying in global_alloc is not 56 yet implemented. */ 57 58/* Pseudos allocated here can be reallocated by global.c if the hard register 59 is used as a spill register. Currently we don't allocate such pseudos 60 here if their preferred class is likely to be used by spills. */ 61 62#include "config.h" 63#include "system.h" 64#include "rtl.h" 65#include "flags.h" 66#include "basic-block.h" 67#include "regs.h" 68#include "hard-reg-set.h" 69#include "insn-config.h" 70#include "insn-attr.h" 71#include "recog.h" 72#include "output.h" 73#include "toplev.h" 74 75/* Next quantity number available for allocation. */ 76 77static int next_qty; 78 79/* In all the following vectors indexed by quantity number. */ 80 81/* Element Q is the hard reg number chosen for quantity Q, 82 or -1 if none was found. */ 83 84static short *qty_phys_reg; 85 86/* We maintain two hard register sets that indicate suggested hard registers 87 for each quantity. The first, qty_phys_copy_sugg, contains hard registers 88 that are tied to the quantity by a simple copy. The second contains all 89 hard registers that are tied to the quantity via an arithmetic operation. 90 91 The former register set is given priority for allocation. This tends to 92 eliminate copy insns. */ 93 94/* Element Q is a set of hard registers that are suggested for quantity Q by 95 copy insns. */ 96 97static HARD_REG_SET *qty_phys_copy_sugg; 98 99/* Element Q is a set of hard registers that are suggested for quantity Q by 100 arithmetic insns. */ 101 102static HARD_REG_SET *qty_phys_sugg; 103 104/* Element Q is the number of suggested registers in qty_phys_copy_sugg. */ 105 106static short *qty_phys_num_copy_sugg; 107 108/* Element Q is the number of suggested registers in qty_phys_sugg. */ 109 110static short *qty_phys_num_sugg; 111 112/* Element Q is the number of refs to quantity Q. */ 113 114static int *qty_n_refs; 115 116/* Element Q is a reg class contained in (smaller than) the 117 preferred classes of all the pseudo regs that are tied in quantity Q. 118 This is the preferred class for allocating that quantity. */ 119 120static enum reg_class *qty_min_class; 121 122/* Insn number (counting from head of basic block) 123 where quantity Q was born. -1 if birth has not been recorded. */ 124 125static int *qty_birth; 126 127/* Insn number (counting from head of basic block) 128 where quantity Q died. Due to the way tying is done, 129 and the fact that we consider in this pass only regs that die but once, 130 a quantity can die only once. Each quantity's life span 131 is a set of consecutive insns. -1 if death has not been recorded. */ 132 133static int *qty_death; 134 135/* Number of words needed to hold the data in quantity Q. 136 This depends on its machine mode. It is used for these purposes: 137 1. It is used in computing the relative importances of qtys, 138 which determines the order in which we look for regs for them. 139 2. It is used in rules that prevent tying several registers of 140 different sizes in a way that is geometrically impossible 141 (see combine_regs). */ 142 143static int *qty_size; 144 145/* This holds the mode of the registers that are tied to qty Q, 146 or VOIDmode if registers with differing modes are tied together. */ 147 148static enum machine_mode *qty_mode; 149 150/* Number of times a reg tied to qty Q lives across a CALL_INSN. */ 151 152static int *qty_n_calls_crossed; 153 154/* Register class within which we allocate qty Q if we can't get 155 its preferred class. */ 156 157static enum reg_class *qty_alternate_class; 158 159/* Element Q is nonzero if this quantity has been used in a SUBREG 160 that changes its size. */ 161 162static char *qty_changes_size; 163 164/* Element Q is the register number of one pseudo register whose 165 reg_qty value is Q. This register should be the head of the chain 166 maintained in reg_next_in_qty. */ 167 168static int *qty_first_reg; 169 170/* If (REG N) has been assigned a quantity number, is a register number 171 of another register assigned the same quantity number, or -1 for the 172 end of the chain. qty_first_reg point to the head of this chain. */ 173 174static int *reg_next_in_qty; 175 176/* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg 177 if it is >= 0, 178 of -1 if this register cannot be allocated by local-alloc, 179 or -2 if not known yet. 180 181 Note that if we see a use or death of pseudo register N with 182 reg_qty[N] == -2, register N must be local to the current block. If 183 it were used in more than one block, we would have reg_qty[N] == -1. 184 This relies on the fact that if reg_basic_block[N] is >= 0, register N 185 will not appear in any other block. We save a considerable number of 186 tests by exploiting this. 187 188 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not 189 be referenced. */ 190 191static int *reg_qty; 192 193/* The offset (in words) of register N within its quantity. 194 This can be nonzero if register N is SImode, and has been tied 195 to a subreg of a DImode register. */ 196 197static char *reg_offset; 198 199/* Vector of substitutions of register numbers, 200 used to map pseudo regs into hardware regs. 201 This is set up as a result of register allocation. 202 Element N is the hard reg assigned to pseudo reg N, 203 or is -1 if no hard reg was assigned. 204 If N is a hard reg number, element N is N. */ 205 206short *reg_renumber; 207 208/* Set of hard registers live at the current point in the scan 209 of the instructions in a basic block. */ 210 211static HARD_REG_SET regs_live; 212 213/* Each set of hard registers indicates registers live at a particular 214 point in the basic block. For N even, regs_live_at[N] says which 215 hard registers are needed *after* insn N/2 (i.e., they may not 216 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1. 217 218 If an object is to conflict with the inputs of insn J but not the 219 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly, 220 if it is to conflict with the outputs of insn J but not the inputs of 221 insn J + 1, it is said to die at index J*2 + 1. */ 222 223static HARD_REG_SET *regs_live_at; 224 225/* Communicate local vars `insn_number' and `insn' 226 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */ 227static int this_insn_number; 228static rtx this_insn; 229 230/* Used to communicate changes made by update_equiv_regs to 231 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note 232 found or created, so that we can keep track of what memory accesses might 233 be created later, e.g. by reload. */ 234 235static rtx *reg_equiv_replacement; 236 237/* Used for communication between update_equiv_regs and no_equiv. */ 238static rtx *reg_equiv_init_insns; 239 240/* Nonzero if we recorded an equivalence for a LABEL_REF. */ 241static int recorded_label_ref; 242 243static void alloc_qty PROTO((int, enum machine_mode, int, int)); 244static void validate_equiv_mem_from_store PROTO((rtx, rtx)); 245static int validate_equiv_mem PROTO((rtx, rtx, rtx)); 246static int contains_replace_regs PROTO((rtx, char *)); 247static int memref_referenced_p PROTO((rtx, rtx)); 248static int memref_used_between_p PROTO((rtx, rtx, rtx)); 249static void update_equiv_regs PROTO((void)); 250static void no_equiv PROTO((rtx, rtx)); 251static void block_alloc PROTO((int)); 252static int qty_sugg_compare PROTO((int, int)); 253static int qty_sugg_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR)); 254static int qty_compare PROTO((int, int)); 255static int qty_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR)); 256static int combine_regs PROTO((rtx, rtx, int, int, rtx, int)); 257static int reg_meets_class_p PROTO((int, enum reg_class)); 258static void update_qty_class PROTO((int, int)); 259static void reg_is_set PROTO((rtx, rtx)); 260static void reg_is_born PROTO((rtx, int)); 261static void wipe_dead_reg PROTO((rtx, int)); 262static int find_free_reg PROTO((enum reg_class, enum machine_mode, 263 int, int, int, int, int)); 264static void mark_life PROTO((int, enum machine_mode, int)); 265static void post_mark_life PROTO((int, enum machine_mode, int, int, int)); 266static int no_conflict_p PROTO((rtx, rtx, rtx)); 267static int requires_inout PROTO((const char *)); 268 269/* Allocate a new quantity (new within current basic block) 270 for register number REGNO which is born at index BIRTH 271 within the block. MODE and SIZE are info on reg REGNO. */ 272 273static void 274alloc_qty (regno, mode, size, birth) 275 int regno; 276 enum machine_mode mode; 277 int size, birth; 278{ 279 register int qty = next_qty++; 280 281 reg_qty[regno] = qty; 282 reg_offset[regno] = 0; 283 reg_next_in_qty[regno] = -1; 284 285 qty_first_reg[qty] = regno; 286 qty_size[qty] = size; 287 qty_mode[qty] = mode; 288 qty_birth[qty] = birth; 289 qty_n_calls_crossed[qty] = REG_N_CALLS_CROSSED (regno); 290 qty_min_class[qty] = reg_preferred_class (regno); 291 qty_alternate_class[qty] = reg_alternate_class (regno); 292 qty_n_refs[qty] = REG_N_REFS (regno); 293 qty_changes_size[qty] = REG_CHANGES_SIZE (regno); 294} 295 296/* Main entry point of this file. */ 297 298int 299local_alloc () 300{ 301 register int b, i; 302 int max_qty; 303 304 /* We need to keep track of whether or not we recorded a LABEL_REF so 305 that we know if the jump optimizer needs to be rerun. */ 306 recorded_label_ref = 0; 307 308 /* Leaf functions and non-leaf functions have different needs. 309 If defined, let the machine say what kind of ordering we 310 should use. */ 311#ifdef ORDER_REGS_FOR_LOCAL_ALLOC 312 ORDER_REGS_FOR_LOCAL_ALLOC; 313#endif 314 315 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected 316 registers. */ 317 update_equiv_regs (); 318 319 /* This sets the maximum number of quantities we can have. Quantity 320 numbers start at zero and we can have one for each pseudo. */ 321 max_qty = (max_regno - FIRST_PSEUDO_REGISTER); 322 323 /* Allocate vectors of temporary data. 324 See the declarations of these variables, above, 325 for what they mean. */ 326 327 qty_phys_reg = (short *) alloca (max_qty * sizeof (short)); 328 qty_phys_copy_sugg 329 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET)); 330 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short)); 331 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET)); 332 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short)); 333 qty_birth = (int *) alloca (max_qty * sizeof (int)); 334 qty_death = (int *) alloca (max_qty * sizeof (int)); 335 qty_first_reg = (int *) alloca (max_qty * sizeof (int)); 336 qty_size = (int *) alloca (max_qty * sizeof (int)); 337 qty_mode 338 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode)); 339 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int)); 340 qty_min_class 341 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class)); 342 qty_alternate_class 343 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class)); 344 qty_n_refs = (int *) alloca (max_qty * sizeof (int)); 345 qty_changes_size = (char *) alloca (max_qty * sizeof (char)); 346 347 reg_qty = (int *) xmalloc (max_regno * sizeof (int)); 348 reg_offset = (char *) xmalloc (max_regno * sizeof (char)); 349 reg_next_in_qty = (int *) xmalloc(max_regno * sizeof (int)); 350 351 /* Allocate the reg_renumber array */ 352 allocate_reg_info (max_regno, FALSE, TRUE); 353 354 /* Determine which pseudo-registers can be allocated by local-alloc. 355 In general, these are the registers used only in a single block and 356 which only die once. However, if a register's preferred class has only 357 a few entries, don't allocate this register here unless it is preferred 358 or nothing since retry_global_alloc won't be able to move it to 359 GENERAL_REGS if a reload register of this class is needed. 360 361 We need not be concerned with which block actually uses the register 362 since we will never see it outside that block. */ 363 364 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 365 { 366 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1 367 && (reg_alternate_class (i) == NO_REGS 368 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i)))) 369 reg_qty[i] = -2; 370 else 371 reg_qty[i] = -1; 372 } 373 374 /* Force loop below to initialize entire quantity array. */ 375 next_qty = max_qty; 376 377 /* Allocate each block's local registers, block by block. */ 378 379 for (b = 0; b < n_basic_blocks; b++) 380 { 381 /* NEXT_QTY indicates which elements of the `qty_...' 382 vectors might need to be initialized because they were used 383 for the previous block; it is set to the entire array before 384 block 0. Initialize those, with explicit loop if there are few, 385 else with bzero and bcopy. Do not initialize vectors that are 386 explicit set by `alloc_qty'. */ 387 388 if (next_qty < 6) 389 { 390 for (i = 0; i < next_qty; i++) 391 { 392 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]); 393 qty_phys_num_copy_sugg[i] = 0; 394 CLEAR_HARD_REG_SET (qty_phys_sugg[i]); 395 qty_phys_num_sugg[i] = 0; 396 } 397 } 398 else 399 { 400#define CLEAR(vector) \ 401 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty); 402 403 CLEAR (qty_phys_copy_sugg); 404 CLEAR (qty_phys_num_copy_sugg); 405 CLEAR (qty_phys_sugg); 406 CLEAR (qty_phys_num_sugg); 407 } 408 409 next_qty = 0; 410 411 block_alloc (b); 412#ifdef USE_C_ALLOCA 413 alloca (0); 414#endif 415 } 416 417 free (reg_qty); 418 free (reg_offset); 419 free (reg_next_in_qty); 420 return recorded_label_ref; 421} 422 423/* Depth of loops we are in while in update_equiv_regs. */ 424static int loop_depth; 425 426/* Used for communication between the following two functions: contains 427 a MEM that we wish to ensure remains unchanged. */ 428static rtx equiv_mem; 429 430/* Set nonzero if EQUIV_MEM is modified. */ 431static int equiv_mem_modified; 432 433/* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. 434 Called via note_stores. */ 435 436static void 437validate_equiv_mem_from_store (dest, set) 438 rtx dest; 439 rtx set ATTRIBUTE_UNUSED; 440{ 441 if ((GET_CODE (dest) == REG 442 && reg_overlap_mentioned_p (dest, equiv_mem)) 443 || (GET_CODE (dest) == MEM 444 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p))) 445 equiv_mem_modified = 1; 446} 447 448/* Verify that no store between START and the death of REG invalidates 449 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, 450 by storing into an overlapping memory location, or with a non-const 451 CALL_INSN. 452 453 Return 1 if MEMREF remains valid. */ 454 455static int 456validate_equiv_mem (start, reg, memref) 457 rtx start; 458 rtx reg; 459 rtx memref; 460{ 461 rtx insn; 462 rtx note; 463 464 equiv_mem = memref; 465 equiv_mem_modified = 0; 466 467 /* If the memory reference has side effects or is volatile, it isn't a 468 valid equivalence. */ 469 if (side_effects_p (memref)) 470 return 0; 471 472 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) 473 { 474 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') 475 continue; 476 477 if (find_reg_note (insn, REG_DEAD, reg)) 478 return 1; 479 480 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref) 481 && ! CONST_CALL_P (insn)) 482 return 0; 483 484 note_stores (PATTERN (insn), validate_equiv_mem_from_store); 485 486 /* If a register mentioned in MEMREF is modified via an 487 auto-increment, we lose the equivalence. Do the same if one 488 dies; although we could extend the life, it doesn't seem worth 489 the trouble. */ 490 491 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) 492 if ((REG_NOTE_KIND (note) == REG_INC 493 || REG_NOTE_KIND (note) == REG_DEAD) 494 && GET_CODE (XEXP (note, 0)) == REG 495 && reg_overlap_mentioned_p (XEXP (note, 0), memref)) 496 return 0; 497 } 498 499 return 0; 500} 501 502/* TRUE if X uses any registers for which reg_equiv_replace is true. */ 503 504static int 505contains_replace_regs (x, reg_equiv_replace) 506 rtx x; 507 char *reg_equiv_replace; 508{ 509 int i, j; 510 char *fmt; 511 enum rtx_code code = GET_CODE (x); 512 513 switch (code) 514 { 515 case CONST_INT: 516 case CONST: 517 case LABEL_REF: 518 case SYMBOL_REF: 519 case CONST_DOUBLE: 520 case PC: 521 case CC0: 522 case HIGH: 523 case LO_SUM: 524 return 0; 525 526 case REG: 527 return reg_equiv_replace[REGNO (x)]; 528 529 default: 530 break; 531 } 532 533 fmt = GET_RTX_FORMAT (code); 534 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 535 switch (fmt[i]) 536 { 537 case 'e': 538 if (contains_replace_regs (XEXP (x, i), reg_equiv_replace)) 539 return 1; 540 break; 541 case 'E': 542 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 543 if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace)) 544 return 1; 545 break; 546 } 547 548 return 0; 549} 550 551/* TRUE if X references a memory location that would be affected by a store 552 to MEMREF. */ 553 554static int 555memref_referenced_p (memref, x) 556 rtx x; 557 rtx memref; 558{ 559 int i, j; 560 char *fmt; 561 enum rtx_code code = GET_CODE (x); 562 563 switch (code) 564 { 565 case CONST_INT: 566 case CONST: 567 case LABEL_REF: 568 case SYMBOL_REF: 569 case CONST_DOUBLE: 570 case PC: 571 case CC0: 572 case HIGH: 573 case LO_SUM: 574 return 0; 575 576 case REG: 577 return (reg_equiv_replacement[REGNO (x)] 578 && memref_referenced_p (memref, 579 reg_equiv_replacement[REGNO (x)])); 580 581 case MEM: 582 if (true_dependence (memref, VOIDmode, x, rtx_varies_p)) 583 return 1; 584 break; 585 586 case SET: 587 /* If we are setting a MEM, it doesn't count (its address does), but any 588 other SET_DEST that has a MEM in it is referencing the MEM. */ 589 if (GET_CODE (SET_DEST (x)) == MEM) 590 { 591 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) 592 return 1; 593 } 594 else if (memref_referenced_p (memref, SET_DEST (x))) 595 return 1; 596 597 return memref_referenced_p (memref, SET_SRC (x)); 598 599 default: 600 break; 601 } 602 603 fmt = GET_RTX_FORMAT (code); 604 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 605 switch (fmt[i]) 606 { 607 case 'e': 608 if (memref_referenced_p (memref, XEXP (x, i))) 609 return 1; 610 break; 611 case 'E': 612 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 613 if (memref_referenced_p (memref, XVECEXP (x, i, j))) 614 return 1; 615 break; 616 } 617 618 return 0; 619} 620 621/* TRUE if some insn in the range (START, END] references a memory location 622 that would be affected by a store to MEMREF. */ 623 624static int 625memref_used_between_p (memref, start, end) 626 rtx memref; 627 rtx start; 628 rtx end; 629{ 630 rtx insn; 631 632 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); 633 insn = NEXT_INSN (insn)) 634 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' 635 && memref_referenced_p (memref, PATTERN (insn))) 636 return 1; 637 638 return 0; 639} 640 641/* Return nonzero if the rtx X is invariant over the current function. */ 642int 643function_invariant_p (x) 644 rtx x; 645{ 646 if (CONSTANT_P (x)) 647 return 1; 648 if (x == frame_pointer_rtx || x == arg_pointer_rtx) 649 return 1; 650 if (GET_CODE (x) == PLUS 651 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx) 652 && CONSTANT_P (XEXP (x, 1))) 653 return 1; 654 return 0; 655} 656 657/* Find registers that are equivalent to a single value throughout the 658 compilation (either because they can be referenced in memory or are set once 659 from a single constant). Lower their priority for a register. 660 661 If such a register is only referenced once, try substituting its value 662 into the using insn. If it succeeds, we can eliminate the register 663 completely. */ 664 665static void 666update_equiv_regs () 667{ 668 /* Set when an attempt should be made to replace a register with the 669 associated reg_equiv_replacement entry at the end of this function. */ 670 char *reg_equiv_replace 671 = (char *) alloca (max_regno * sizeof *reg_equiv_replace); 672 rtx insn; 673 int block, depth; 674 675 reg_equiv_init_insns = (rtx *) alloca (max_regno * sizeof (rtx)); 676 reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx)); 677 678 bzero ((char *) reg_equiv_init_insns, max_regno * sizeof (rtx)); 679 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx)); 680 bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace); 681 682 init_alias_analysis (); 683 684 loop_depth = 1; 685 686 /* Scan the insns and find which registers have equivalences. Do this 687 in a separate scan of the insns because (due to -fcse-follow-jumps) 688 a register can be set below its use. */ 689 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 690 { 691 rtx note; 692 rtx set; 693 rtx dest, src; 694 int regno; 695 696 if (GET_CODE (insn) == NOTE) 697 { 698 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) 699 loop_depth++; 700 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) 701 loop_depth--; 702 } 703 704 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') 705 continue; 706 707 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) 708 if (REG_NOTE_KIND (note) == REG_INC) 709 no_equiv (XEXP (note, 0), note); 710 711 set = single_set (insn); 712 713 /* If this insn contains more (or less) than a single SET, 714 only mark all destinations as having no known equivalence. */ 715 if (set == 0) 716 { 717 note_stores (PATTERN (insn), no_equiv); 718 continue; 719 } 720 else if (GET_CODE (PATTERN (insn)) == PARALLEL) 721 { 722 int i; 723 724 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) 725 { 726 rtx part = XVECEXP (PATTERN (insn), 0, i); 727 if (part != set) 728 note_stores (part, no_equiv); 729 } 730 } 731 732 dest = SET_DEST (set); 733 src = SET_SRC (set); 734 735 /* If this sets a MEM to the contents of a REG that is only used 736 in a single basic block, see if the register is always equivalent 737 to that memory location and if moving the store from INSN to the 738 insn that set REG is safe. If so, put a REG_EQUIV note on the 739 initializing insn. 740 741 Don't add a REG_EQUIV note if the insn already has one. The existing 742 REG_EQUIV is likely more useful than the one we are adding. 743 744 If one of the regs in the address is marked as reg_equiv_replace, 745 then we can't add this REG_EQUIV note. The reg_equiv_replace 746 optimization may move the set of this register immediately before 747 insn, which puts it after reg_equiv_init_insns[regno], and hence 748 the mention in the REG_EQUIV note would be to an uninitialized 749 pseudo. */ 750 /* ????? This test isn't good enough; we might see a MEM with a use of 751 a pseudo register before we see its setting insn that will cause 752 reg_equiv_replace for that pseudo to be set. 753 Equivalences to MEMs should be made in another pass, after the 754 reg_equiv_replace information has been gathered. */ 755 756 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG 757 && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER 758 && REG_BASIC_BLOCK (regno) >= 0 759 && REG_N_SETS (regno) == 1 760 && reg_equiv_init_insns[regno] != 0 761 && reg_equiv_init_insns[regno] != const0_rtx 762 && ! find_reg_note (XEXP (reg_equiv_init_insns[regno], 0), 763 REG_EQUIV, NULL_RTX) 764 && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace)) 765 { 766 rtx init_insn = XEXP (reg_equiv_init_insns[regno], 0); 767 if (validate_equiv_mem (init_insn, src, dest) 768 && ! memref_used_between_p (dest, init_insn, insn)) 769 REG_NOTES (init_insn) 770 = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn)); 771 } 772 773 /* We only handle the case of a pseudo register being set 774 once, or always to the same value. */ 775 /* ??? The mn10200 port breaks if we add equivalences for 776 values that need an ADDRESS_REGS register and set them equivalent 777 to a MEM of a pseudo. The actual problem is in the over-conservative 778 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in 779 calculate_needs, but we traditionally work around this problem 780 here by rejecting equivalences when the destination is in a register 781 that's likely spilled. This is fragile, of course, since the 782 preferred class of a pseudo depends on all instructions that set 783 or use it. */ 784 785 if (GET_CODE (dest) != REG 786 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER 787 || reg_equiv_init_insns[regno] == const0_rtx 788 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno)) 789 && GET_CODE (src) == MEM)) 790 { 791 /* This might be seting a SUBREG of a pseudo, a pseudo that is 792 also set somewhere else to a constant. */ 793 note_stores (set, no_equiv); 794 continue; 795 } 796 /* Don't handle the equivalence if the source is in a register 797 class that's likely to be spilled. */ 798 if (GET_CODE (src) == REG 799 && REGNO (src) >= FIRST_PSEUDO_REGISTER 800 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src)))) 801 { 802 no_equiv (dest, set); 803 continue; 804 } 805 806 note = find_reg_note (insn, REG_EQUAL, NULL_RTX); 807 808 if (REG_N_SETS (regno) != 1 809 && (! note 810 || ! function_invariant_p (XEXP (note, 0)) 811 || (reg_equiv_replacement[regno] 812 && ! rtx_equal_p (XEXP (note, 0), 813 reg_equiv_replacement[regno])))) 814 { 815 no_equiv (dest, set); 816 continue; 817 } 818 /* Record this insn as initializing this register. */ 819 reg_equiv_init_insns[regno] 820 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init_insns[regno]); 821 822 /* If this register is known to be equal to a constant, record that 823 it is always equivalent to the constant. */ 824 if (note && function_invariant_p (XEXP (note, 0))) 825 PUT_MODE (note, (enum machine_mode) REG_EQUIV); 826 827 /* If this insn introduces a "constant" register, decrease the priority 828 of that register. Record this insn if the register is only used once 829 more and the equivalence value is the same as our source. 830 831 The latter condition is checked for two reasons: First, it is an 832 indication that it may be more efficient to actually emit the insn 833 as written (if no registers are available, reload will substitute 834 the equivalence). Secondly, it avoids problems with any registers 835 dying in this insn whose death notes would be missed. 836 837 If we don't have a REG_EQUIV note, see if this insn is loading 838 a register used only in one basic block from a MEM. If so, and the 839 MEM remains unchanged for the life of the register, add a REG_EQUIV 840 note. */ 841 842 note = find_reg_note (insn, REG_EQUIV, NULL_RTX); 843 844 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0 845 && GET_CODE (SET_SRC (set)) == MEM 846 && validate_equiv_mem (insn, dest, SET_SRC (set))) 847 REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set), 848 REG_NOTES (insn)); 849 850 if (note) 851 { 852 int regno = REGNO (dest); 853 854 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF. 855 We might end up substituting the LABEL_REF for uses of the 856 pseudo here or later. That kind of transformation may turn an 857 indirect jump into a direct jump, in which case we must rerun the 858 jump optimizer to ensure that the JUMP_LABEL fields are valid. */ 859 if (GET_CODE (XEXP (note, 0)) == LABEL_REF 860 || (GET_CODE (XEXP (note, 0)) == CONST 861 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS 862 && (GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) 863 == LABEL_REF))) 864 recorded_label_ref = 1; 865 866 867 reg_equiv_replacement[regno] = XEXP (note, 0); 868 869 /* Don't mess with things live during setjmp. */ 870 if (REG_LIVE_LENGTH (regno) >= 0) 871 { 872 /* Note that the statement below does not affect the priority 873 in local-alloc! */ 874 REG_LIVE_LENGTH (regno) *= 2; 875 876 877 /* If the register is referenced exactly twice, meaning it is 878 set once and used once, indicate that the reference may be 879 replaced by the equivalence we computed above. If the 880 register is only used in one basic block, this can't succeed 881 or combine would have done it. 882 883 It would be nice to use "loop_depth * 2" in the compare 884 below. Unfortunately, LOOP_DEPTH need not be constant within 885 a basic block so this would be too complicated. 886 887 This case normally occurs when a parameter is read from 888 memory and then used exactly once, not in a loop. */ 889 890 if (REG_N_REFS (regno) == 2 891 && REG_BASIC_BLOCK (regno) < 0 892 && rtx_equal_p (XEXP (note, 0), SET_SRC (set))) 893 reg_equiv_replace[regno] = 1; 894 } 895 } 896 } 897 898 /* Now scan all regs killed in an insn to see if any of them are 899 registers only used that once. If so, see if we can replace the 900 reference with the equivalent from. If we can, delete the 901 initializing reference and this register will go away. If we 902 can't replace the reference, and the instruction is not in a 903 loop, then move the register initialization just before the use, 904 so that they are in the same basic block. */ 905 block = -1; 906 depth = 0; 907 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 908 { 909 rtx link; 910 911 /* Keep track of which basic block we are in. */ 912 if (block + 1 < n_basic_blocks 913 && BLOCK_HEAD (block + 1) == insn) 914 ++block; 915 916 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') 917 { 918 if (GET_CODE (insn) == NOTE) 919 { 920 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) 921 ++depth; 922 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) 923 { 924 --depth; 925 if (depth < 0) 926 abort (); 927 } 928 } 929 930 continue; 931 } 932 933 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 934 { 935 if (REG_NOTE_KIND (link) == REG_DEAD 936 /* Make sure this insn still refers to the register. */ 937 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) 938 { 939 int regno = REGNO (XEXP (link, 0)); 940 rtx equiv_insn; 941 942 if (! reg_equiv_replace[regno]) 943 continue; 944 945 /* reg_equiv_replace[REGNO] gets set only when 946 REG_N_REFS[REGNO] is 2, i.e. the register is set 947 once and used once. (If it were only set, but not used, 948 flow would have deleted the setting insns.) Hence 949 there can only be one insn in reg_equiv_init_insns. */ 950 equiv_insn = XEXP (reg_equiv_init_insns[regno], 0); 951 952 if (validate_replace_rtx (regno_reg_rtx[regno], 953 reg_equiv_replacement[regno], insn)) 954 { 955 remove_death (regno, insn); 956 REG_N_REFS (regno) = 0; 957 PUT_CODE (equiv_insn, NOTE); 958 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; 959 NOTE_SOURCE_FILE (equiv_insn) = 0; 960 } 961 /* If we aren't in a loop, and there are no calls in 962 INSN or in the initialization of the register, then 963 move the initialization of the register to just 964 before INSN. Update the flow information. */ 965 else if (depth == 0 966 && GET_CODE (equiv_insn) == INSN 967 && GET_CODE (insn) == INSN 968 && REG_BASIC_BLOCK (regno) < 0) 969 { 970 int l; 971 972 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn); 973 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn); 974 975 PUT_CODE (equiv_insn, NOTE); 976 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; 977 NOTE_SOURCE_FILE (equiv_insn) = 0; 978 REG_NOTES (equiv_insn) = 0; 979 980 if (block < 0) 981 REG_BASIC_BLOCK (regno) = 0; 982 else 983 REG_BASIC_BLOCK (regno) = block; 984 REG_N_CALLS_CROSSED (regno) = 0; 985 REG_LIVE_LENGTH (regno) = 2; 986 987 if (block >= 0 && insn == BLOCK_HEAD (block)) 988 BLOCK_HEAD (block) = PREV_INSN (insn); 989 990 for (l = 0; l < n_basic_blocks; l++) 991 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l)->global_live_at_start, 992 regno); 993 } 994 } 995 } 996 } 997} 998 999/* Mark REG as having no known equivalence. 1000 Some instructions might have been proceessed before and furnished 1001 with REG_EQUIV notes for this register; these notes will have to be 1002 removed. 1003 STORE is the piece of RTL that does the non-constant / conflicting 1004 assignment - a SET, CLOBBER or REG_INC note. It is currently not used, 1005 but needs to be there because this function is called from note_stores. */ 1006static void 1007no_equiv (reg, store) 1008 rtx reg, store ATTRIBUTE_UNUSED; 1009{ 1010 int regno; 1011 rtx list; 1012 1013 if (GET_CODE (reg) != REG) 1014 return; 1015 regno = REGNO (reg); 1016 list = reg_equiv_init_insns[regno]; 1017 if (list == const0_rtx) 1018 return; 1019 for (; list; list = XEXP (list, 1)) 1020 { 1021 rtx insn = XEXP (list, 0); 1022 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); 1023 } 1024 reg_equiv_init_insns[regno] = const0_rtx; 1025 reg_equiv_replacement[regno] = NULL_RTX; 1026} 1027 1028/* Allocate hard regs to the pseudo regs used only within block number B. 1029 Only the pseudos that die but once can be handled. */ 1030 1031static void 1032block_alloc (b) 1033 int b; 1034{ 1035 register int i, q; 1036 register rtx insn; 1037 rtx note; 1038 int insn_number = 0; 1039 int insn_count = 0; 1040 int max_uid = get_max_uid (); 1041 int *qty_order; 1042 int no_conflict_combined_regno = -1; 1043 1044 /* Count the instructions in the basic block. */ 1045 1046 insn = BLOCK_END (b); 1047 while (1) 1048 { 1049 if (GET_CODE (insn) != NOTE) 1050 if (++insn_count > max_uid) 1051 abort (); 1052 if (insn == BLOCK_HEAD (b)) 1053 break; 1054 insn = PREV_INSN (insn); 1055 } 1056 1057 /* +2 to leave room for a post_mark_life at the last insn and for 1058 the birth of a CLOBBER in the first insn. */ 1059 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2) 1060 * sizeof (HARD_REG_SET)); 1061 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET)); 1062 1063 /* Initialize table of hardware registers currently live. */ 1064 1065 REG_SET_TO_HARD_REG_SET (regs_live, BASIC_BLOCK (b)->global_live_at_start); 1066 1067 /* This loop scans the instructions of the basic block 1068 and assigns quantities to registers. 1069 It computes which registers to tie. */ 1070 1071 insn = BLOCK_HEAD (b); 1072 while (1) 1073 { 1074 register rtx body = PATTERN (insn); 1075 1076 if (GET_CODE (insn) != NOTE) 1077 insn_number++; 1078 1079 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 1080 { 1081 register rtx link, set; 1082 register int win = 0; 1083 register rtx r0, r1; 1084 int combined_regno = -1; 1085 int i; 1086 1087 this_insn_number = insn_number; 1088 this_insn = insn; 1089 1090 extract_insn (insn); 1091 which_alternative = -1; 1092 1093 /* Is this insn suitable for tying two registers? 1094 If so, try doing that. 1095 Suitable insns are those with at least two operands and where 1096 operand 0 is an output that is a register that is not 1097 earlyclobber. 1098 1099 We can tie operand 0 with some operand that dies in this insn. 1100 First look for operands that are required to be in the same 1101 register as operand 0. If we find such, only try tying that 1102 operand or one that can be put into that operand if the 1103 operation is commutative. If we don't find an operand 1104 that is required to be in the same register as operand 0, 1105 we can tie with any operand. 1106 1107 Subregs in place of regs are also ok. 1108 1109 If tying is done, WIN is set nonzero. */ 1110 1111 if (1 1112#ifdef REGISTER_CONSTRAINTS 1113 && recog_n_operands > 1 1114 && recog_constraints[0][0] == '=' 1115 && recog_constraints[0][1] != '&' 1116#else 1117 && GET_CODE (PATTERN (insn)) == SET 1118 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0]) 1119#endif 1120 ) 1121 { 1122#ifdef REGISTER_CONSTRAINTS 1123 /* If non-negative, is an operand that must match operand 0. */ 1124 int must_match_0 = -1; 1125 /* Counts number of alternatives that require a match with 1126 operand 0. */ 1127 int n_matching_alts = 0; 1128 1129 for (i = 1; i < recog_n_operands; i++) 1130 { 1131 const char *p = recog_constraints[i]; 1132 int this_match = (requires_inout (p)); 1133 1134 n_matching_alts += this_match; 1135 if (this_match == recog_n_alternatives) 1136 must_match_0 = i; 1137 } 1138#endif 1139 1140 r0 = recog_operand[0]; 1141 for (i = 1; i < recog_n_operands; i++) 1142 { 1143#ifdef REGISTER_CONSTRAINTS 1144 /* Skip this operand if we found an operand that 1145 must match operand 0 and this operand isn't it 1146 and can't be made to be it by commutativity. */ 1147 1148 if (must_match_0 >= 0 && i != must_match_0 1149 && ! (i == must_match_0 + 1 1150 && recog_constraints[i-1][0] == '%') 1151 && ! (i == must_match_0 - 1 1152 && recog_constraints[i][0] == '%')) 1153 continue; 1154 1155 /* Likewise if each alternative has some operand that 1156 must match operand zero. In that case, skip any 1157 operand that doesn't list operand 0 since we know that 1158 the operand always conflicts with operand 0. We 1159 ignore commutatity in this case to keep things simple. */ 1160 if (n_matching_alts == recog_n_alternatives 1161 && 0 == requires_inout (recog_constraints[i])) 1162 continue; 1163#endif 1164 1165 r1 = recog_operand[i]; 1166 1167 /* If the operand is an address, find a register in it. 1168 There may be more than one register, but we only try one 1169 of them. */ 1170 if ( 1171#ifdef REGISTER_CONSTRAINTS 1172 recog_constraints[i][0] == 'p' 1173#else 1174 recog_operand_address_p[i] 1175#endif 1176 ) 1177 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT) 1178 r1 = XEXP (r1, 0); 1179 1180 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG) 1181 { 1182 /* We have two priorities for hard register preferences. 1183 If we have a move insn or an insn whose first input 1184 can only be in the same register as the output, give 1185 priority to an equivalence found from that insn. */ 1186 int may_save_copy 1187 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1) 1188#ifdef REGISTER_CONSTRAINTS 1189 || (r1 == recog_operand[i] && must_match_0 >= 0) 1190#endif 1191 ); 1192 1193 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) 1194 win = combine_regs (r1, r0, may_save_copy, 1195 insn_number, insn, 0); 1196 } 1197 if (win) 1198 break; 1199 } 1200 } 1201 1202 /* Recognize an insn sequence with an ultimate result 1203 which can safely overlap one of the inputs. 1204 The sequence begins with a CLOBBER of its result, 1205 and ends with an insn that copies the result to itself 1206 and has a REG_EQUAL note for an equivalent formula. 1207 That note indicates what the inputs are. 1208 The result and the input can overlap if each insn in 1209 the sequence either doesn't mention the input 1210 or has a REG_NO_CONFLICT note to inhibit the conflict. 1211 1212 We do the combining test at the CLOBBER so that the 1213 destination register won't have had a quantity number 1214 assigned, since that would prevent combining. */ 1215 1216 if (GET_CODE (PATTERN (insn)) == CLOBBER 1217 && (r0 = XEXP (PATTERN (insn), 0), 1218 GET_CODE (r0) == REG) 1219 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0 1220 && XEXP (link, 0) != 0 1221 && GET_CODE (XEXP (link, 0)) == INSN 1222 && (set = single_set (XEXP (link, 0))) != 0 1223 && SET_DEST (set) == r0 && SET_SRC (set) == r0 1224 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL, 1225 NULL_RTX)) != 0) 1226 { 1227 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG 1228 /* Check that we have such a sequence. */ 1229 && no_conflict_p (insn, r0, r1)) 1230 win = combine_regs (r1, r0, 1, insn_number, insn, 1); 1231 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e' 1232 && (r1 = XEXP (XEXP (note, 0), 0), 1233 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG) 1234 && no_conflict_p (insn, r0, r1)) 1235 win = combine_regs (r1, r0, 0, insn_number, insn, 1); 1236 1237 /* Here we care if the operation to be computed is 1238 commutative. */ 1239 else if ((GET_CODE (XEXP (note, 0)) == EQ 1240 || GET_CODE (XEXP (note, 0)) == NE 1241 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c') 1242 && (r1 = XEXP (XEXP (note, 0), 1), 1243 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)) 1244 && no_conflict_p (insn, r0, r1)) 1245 win = combine_regs (r1, r0, 0, insn_number, insn, 1); 1246 1247 /* If we did combine something, show the register number 1248 in question so that we know to ignore its death. */ 1249 if (win) 1250 no_conflict_combined_regno = REGNO (r1); 1251 } 1252 1253 /* If registers were just tied, set COMBINED_REGNO 1254 to the number of the register used in this insn 1255 that was tied to the register set in this insn. 1256 This register's qty should not be "killed". */ 1257 1258 if (win) 1259 { 1260 while (GET_CODE (r1) == SUBREG) 1261 r1 = SUBREG_REG (r1); 1262 combined_regno = REGNO (r1); 1263 } 1264 1265 /* Mark the death of everything that dies in this instruction, 1266 except for anything that was just combined. */ 1267 1268 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1269 if (REG_NOTE_KIND (link) == REG_DEAD 1270 && GET_CODE (XEXP (link, 0)) == REG 1271 && combined_regno != REGNO (XEXP (link, 0)) 1272 && (no_conflict_combined_regno != REGNO (XEXP (link, 0)) 1273 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0)))) 1274 wipe_dead_reg (XEXP (link, 0), 0); 1275 1276 /* Allocate qty numbers for all registers local to this block 1277 that are born (set) in this instruction. 1278 A pseudo that already has a qty is not changed. */ 1279 1280 note_stores (PATTERN (insn), reg_is_set); 1281 1282 /* If anything is set in this insn and then unused, mark it as dying 1283 after this insn, so it will conflict with our outputs. This 1284 can't match with something that combined, and it doesn't matter 1285 if it did. Do this after the calls to reg_is_set since these 1286 die after, not during, the current insn. */ 1287 1288 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1289 if (REG_NOTE_KIND (link) == REG_UNUSED 1290 && GET_CODE (XEXP (link, 0)) == REG) 1291 wipe_dead_reg (XEXP (link, 0), 1); 1292 1293 /* If this is an insn that has a REG_RETVAL note pointing at a 1294 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT 1295 block, so clear any register number that combined within it. */ 1296 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0 1297 && GET_CODE (XEXP (note, 0)) == INSN 1298 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER) 1299 no_conflict_combined_regno = -1; 1300 } 1301 1302 /* Set the registers live after INSN_NUMBER. Note that we never 1303 record the registers live before the block's first insn, since no 1304 pseudos we care about are live before that insn. */ 1305 1306 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live); 1307 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live); 1308 1309 if (insn == BLOCK_END (b)) 1310 break; 1311 1312 insn = NEXT_INSN (insn); 1313 } 1314 1315 /* Now every register that is local to this basic block 1316 should have been given a quantity, or else -1 meaning ignore it. 1317 Every quantity should have a known birth and death. 1318 1319 Order the qtys so we assign them registers in order of the 1320 number of suggested registers they need so we allocate those with 1321 the most restrictive needs first. */ 1322 1323 qty_order = (int *) alloca (next_qty * sizeof (int)); 1324 for (i = 0; i < next_qty; i++) 1325 qty_order[i] = i; 1326 1327#define EXCHANGE(I1, I2) \ 1328 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } 1329 1330 switch (next_qty) 1331 { 1332 case 3: 1333 /* Make qty_order[2] be the one to allocate last. */ 1334 if (qty_sugg_compare (0, 1) > 0) 1335 EXCHANGE (0, 1); 1336 if (qty_sugg_compare (1, 2) > 0) 1337 EXCHANGE (2, 1); 1338 1339 /* ... Fall through ... */ 1340 case 2: 1341 /* Put the best one to allocate in qty_order[0]. */ 1342 if (qty_sugg_compare (0, 1) > 0) 1343 EXCHANGE (0, 1); 1344 1345 /* ... Fall through ... */ 1346 1347 case 1: 1348 case 0: 1349 /* Nothing to do here. */ 1350 break; 1351 1352 default: 1353 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1); 1354 } 1355 1356 /* Try to put each quantity in a suggested physical register, if it has one. 1357 This may cause registers to be allocated that otherwise wouldn't be, but 1358 this seems acceptable in local allocation (unlike global allocation). */ 1359 for (i = 0; i < next_qty; i++) 1360 { 1361 q = qty_order[i]; 1362 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0) 1363 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q, 1364 0, 1, qty_birth[q], qty_death[q]); 1365 else 1366 qty_phys_reg[q] = -1; 1367 } 1368 1369 /* Order the qtys so we assign them registers in order of 1370 decreasing length of life. Normally call qsort, but if we 1371 have only a very small number of quantities, sort them ourselves. */ 1372 1373 for (i = 0; i < next_qty; i++) 1374 qty_order[i] = i; 1375 1376#define EXCHANGE(I1, I2) \ 1377 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; } 1378 1379 switch (next_qty) 1380 { 1381 case 3: 1382 /* Make qty_order[2] be the one to allocate last. */ 1383 if (qty_compare (0, 1) > 0) 1384 EXCHANGE (0, 1); 1385 if (qty_compare (1, 2) > 0) 1386 EXCHANGE (2, 1); 1387 1388 /* ... Fall through ... */ 1389 case 2: 1390 /* Put the best one to allocate in qty_order[0]. */ 1391 if (qty_compare (0, 1) > 0) 1392 EXCHANGE (0, 1); 1393 1394 /* ... Fall through ... */ 1395 1396 case 1: 1397 case 0: 1398 /* Nothing to do here. */ 1399 break; 1400 1401 default: 1402 qsort (qty_order, next_qty, sizeof (int), qty_compare_1); 1403 } 1404 1405 /* Now for each qty that is not a hardware register, 1406 look for a hardware register to put it in. 1407 First try the register class that is cheapest for this qty, 1408 if there is more than one class. */ 1409 1410 for (i = 0; i < next_qty; i++) 1411 { 1412 q = qty_order[i]; 1413 if (qty_phys_reg[q] < 0) 1414 { 1415#ifdef INSN_SCHEDULING 1416 /* These values represent the adjusted lifetime of a qty so 1417 that it conflicts with qtys which appear near the start/end 1418 of this qty's lifetime. 1419 1420 The purpose behind extending the lifetime of this qty is to 1421 discourage the register allocator from creating false 1422 dependencies. 1423 1424 The adjustment value is choosen to indicate that this qty 1425 conflicts with all the qtys in the instructions immediately 1426 before and after the lifetime of this qty. 1427 1428 Experiments have shown that higher values tend to hurt 1429 overall code performance. 1430 1431 If allocation using the extended lifetime fails we will try 1432 again with the qty's unadjusted lifetime. */ 1433 int fake_birth = MAX (0, qty_birth[q] - 2 + qty_birth[q] % 2); 1434 int fake_death = MIN (insn_number * 2 + 1, 1435 qty_death[q] + 2 - qty_death[q] % 2); 1436#endif 1437 1438 if (N_REG_CLASSES > 1) 1439 { 1440#ifdef INSN_SCHEDULING 1441 /* We try to avoid using hard registers allocated to qtys which 1442 are born immediately after this qty or die immediately before 1443 this qty. 1444 1445 This optimization is only appropriate when we will run 1446 a scheduling pass after reload and we are not optimizing 1447 for code size. */ 1448 if (flag_schedule_insns_after_reload 1449 && !optimize_size 1450 && !SMALL_REGISTER_CLASSES) 1451 { 1452 1453 qty_phys_reg[q] = find_free_reg (qty_min_class[q], 1454 qty_mode[q], q, 0, 0, 1455 fake_birth, fake_death); 1456 if (qty_phys_reg[q] >= 0) 1457 continue; 1458 } 1459#endif 1460 qty_phys_reg[q] = find_free_reg (qty_min_class[q], 1461 qty_mode[q], q, 0, 0, 1462 qty_birth[q], qty_death[q]); 1463 if (qty_phys_reg[q] >= 0) 1464 continue; 1465 } 1466 1467#ifdef INSN_SCHEDULING 1468 /* Similarly, avoid false dependencies. */ 1469 if (flag_schedule_insns_after_reload 1470 && !optimize_size 1471 && !SMALL_REGISTER_CLASSES 1472 && qty_alternate_class[q] != NO_REGS) 1473 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q], 1474 qty_mode[q], q, 0, 0, 1475 fake_birth, fake_death); 1476#endif 1477 if (qty_alternate_class[q] != NO_REGS) 1478 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q], 1479 qty_mode[q], q, 0, 0, 1480 qty_birth[q], qty_death[q]); 1481 } 1482 } 1483 1484 /* Now propagate the register assignments 1485 to the pseudo regs belonging to the qtys. */ 1486 1487 for (q = 0; q < next_qty; q++) 1488 if (qty_phys_reg[q] >= 0) 1489 { 1490 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i]) 1491 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i]; 1492 } 1493} 1494 1495/* Compare two quantities' priority for getting real registers. 1496 We give shorter-lived quantities higher priority. 1497 Quantities with more references are also preferred, as are quantities that 1498 require multiple registers. This is the identical prioritization as 1499 done by global-alloc. 1500 1501 We used to give preference to registers with *longer* lives, but using 1502 the same algorithm in both local- and global-alloc can speed up execution 1503 of some programs by as much as a factor of three! */ 1504 1505/* Note that the quotient will never be bigger than 1506 the value of floor_log2 times the maximum number of 1507 times a register can occur in one insn (surely less than 100). 1508 Multiplying this by 10000 can't overflow. 1509 QTY_CMP_PRI is also used by qty_sugg_compare. */ 1510 1511#define QTY_CMP_PRI(q) \ 1512 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \ 1513 / (qty_death[q] - qty_birth[q])) * 10000)) 1514 1515static int 1516qty_compare (q1, q2) 1517 int q1, q2; 1518{ 1519 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); 1520} 1521 1522static int 1523qty_compare_1 (q1p, q2p) 1524 const GENERIC_PTR q1p; 1525 const GENERIC_PTR q2p; 1526{ 1527 register int q1 = *(int *)q1p, q2 = *(int *)q2p; 1528 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); 1529 1530 if (tem != 0) 1531 return tem; 1532 1533 /* If qtys are equally good, sort by qty number, 1534 so that the results of qsort leave nothing to chance. */ 1535 return q1 - q2; 1536} 1537 1538/* Compare two quantities' priority for getting real registers. This version 1539 is called for quantities that have suggested hard registers. First priority 1540 goes to quantities that have copy preferences, then to those that have 1541 normal preferences. Within those groups, quantities with the lower 1542 number of preferences have the highest priority. Of those, we use the same 1543 algorithm as above. */ 1544 1545#define QTY_CMP_SUGG(q) \ 1546 (qty_phys_num_copy_sugg[q] \ 1547 ? qty_phys_num_copy_sugg[q] \ 1548 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER) 1549 1550static int 1551qty_sugg_compare (q1, q2) 1552 int q1, q2; 1553{ 1554 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2); 1555 1556 if (tem != 0) 1557 return tem; 1558 1559 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); 1560} 1561 1562static int 1563qty_sugg_compare_1 (q1p, q2p) 1564 const GENERIC_PTR q1p; 1565 const GENERIC_PTR q2p; 1566{ 1567 register int q1 = *(int *)q1p, q2 = *(int *)q2p; 1568 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2); 1569 1570 if (tem != 0) 1571 return tem; 1572 1573 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1); 1574 if (tem != 0) 1575 return tem; 1576 1577 /* If qtys are equally good, sort by qty number, 1578 so that the results of qsort leave nothing to chance. */ 1579 return q1 - q2; 1580} 1581 1582#undef QTY_CMP_SUGG 1583#undef QTY_CMP_PRI 1584 1585/* Attempt to combine the two registers (rtx's) USEDREG and SETREG. 1586 Returns 1 if have done so, or 0 if cannot. 1587 1588 Combining registers means marking them as having the same quantity 1589 and adjusting the offsets within the quantity if either of 1590 them is a SUBREG). 1591 1592 We don't actually combine a hard reg with a pseudo; instead 1593 we just record the hard reg as the suggestion for the pseudo's quantity. 1594 If we really combined them, we could lose if the pseudo lives 1595 across an insn that clobbers the hard reg (eg, movstr). 1596 1597 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though 1598 there is no REG_DEAD note on INSN. This occurs during the processing 1599 of REG_NO_CONFLICT blocks. 1600 1601 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to 1602 SETREG or if the input and output must share a register. 1603 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG. 1604 1605 There are elaborate checks for the validity of combining. */ 1606 1607 1608static int 1609combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead) 1610 rtx usedreg, setreg; 1611 int may_save_copy; 1612 int insn_number; 1613 rtx insn; 1614 int already_dead; 1615{ 1616 register int ureg, sreg; 1617 register int offset = 0; 1618 int usize, ssize; 1619 register int sqty; 1620 1621 /* Determine the numbers and sizes of registers being used. If a subreg 1622 is present that does not change the entire register, don't consider 1623 this a copy insn. */ 1624 1625 while (GET_CODE (usedreg) == SUBREG) 1626 { 1627 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD) 1628 may_save_copy = 0; 1629 offset += SUBREG_WORD (usedreg); 1630 usedreg = SUBREG_REG (usedreg); 1631 } 1632 if (GET_CODE (usedreg) != REG) 1633 return 0; 1634 ureg = REGNO (usedreg); 1635 usize = REG_SIZE (usedreg); 1636 1637 while (GET_CODE (setreg) == SUBREG) 1638 { 1639 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD) 1640 may_save_copy = 0; 1641 offset -= SUBREG_WORD (setreg); 1642 setreg = SUBREG_REG (setreg); 1643 } 1644 if (GET_CODE (setreg) != REG) 1645 return 0; 1646 sreg = REGNO (setreg); 1647 ssize = REG_SIZE (setreg); 1648 1649 /* If UREG is a pseudo-register that hasn't already been assigned a 1650 quantity number, it means that it is not local to this block or dies 1651 more than once. In either event, we can't do anything with it. */ 1652 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0) 1653 /* Do not combine registers unless one fits within the other. */ 1654 || (offset > 0 && usize + offset > ssize) 1655 || (offset < 0 && usize + offset < ssize) 1656 /* Do not combine with a smaller already-assigned object 1657 if that smaller object is already combined with something bigger. */ 1658 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER 1659 && usize < qty_size[reg_qty[ureg]]) 1660 /* Can't combine if SREG is not a register we can allocate. */ 1661 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1) 1662 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note. 1663 These have already been taken care of. This probably wouldn't 1664 combine anyway, but don't take any chances. */ 1665 || (ureg >= FIRST_PSEUDO_REGISTER 1666 && find_reg_note (insn, REG_NO_CONFLICT, usedreg)) 1667 /* Don't tie something to itself. In most cases it would make no 1668 difference, but it would screw up if the reg being tied to itself 1669 also dies in this insn. */ 1670 || ureg == sreg 1671 /* Don't try to connect two different hardware registers. */ 1672 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER) 1673 /* Don't use a hard reg that might be spilled. */ 1674 || (ureg < FIRST_PSEUDO_REGISTER 1675 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (ureg))) 1676 || (sreg < FIRST_PSEUDO_REGISTER 1677 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (sreg))) 1678 /* Don't connect two different machine modes if they have different 1679 implications as to which registers may be used. */ 1680 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg))) 1681 return 0; 1682 1683 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in 1684 qty_phys_sugg for the pseudo instead of tying them. 1685 1686 Return "failure" so that the lifespan of UREG is terminated here; 1687 that way the two lifespans will be disjoint and nothing will prevent 1688 the pseudo reg from being given this hard reg. */ 1689 1690 if (ureg < FIRST_PSEUDO_REGISTER) 1691 { 1692 /* Allocate a quantity number so we have a place to put our 1693 suggestions. */ 1694 if (reg_qty[sreg] == -2) 1695 reg_is_born (setreg, 2 * insn_number); 1696 1697 if (reg_qty[sreg] >= 0) 1698 { 1699 if (may_save_copy 1700 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg)) 1701 { 1702 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg); 1703 qty_phys_num_copy_sugg[reg_qty[sreg]]++; 1704 } 1705 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg)) 1706 { 1707 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg); 1708 qty_phys_num_sugg[reg_qty[sreg]]++; 1709 } 1710 } 1711 return 0; 1712 } 1713 1714 /* Similarly for SREG a hard register and UREG a pseudo register. */ 1715 1716 if (sreg < FIRST_PSEUDO_REGISTER) 1717 { 1718 if (may_save_copy 1719 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg)) 1720 { 1721 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg); 1722 qty_phys_num_copy_sugg[reg_qty[ureg]]++; 1723 } 1724 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg)) 1725 { 1726 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg); 1727 qty_phys_num_sugg[reg_qty[ureg]]++; 1728 } 1729 return 0; 1730 } 1731 1732 /* At this point we know that SREG and UREG are both pseudos. 1733 Do nothing if SREG already has a quantity or is a register that we 1734 don't allocate. */ 1735 if (reg_qty[sreg] >= -1 1736 /* If we are not going to let any regs live across calls, 1737 don't tie a call-crossing reg to a non-call-crossing reg. */ 1738 || (current_function_has_nonlocal_label 1739 && ((REG_N_CALLS_CROSSED (ureg) > 0) 1740 != (REG_N_CALLS_CROSSED (sreg) > 0)))) 1741 return 0; 1742 1743 /* We don't already know about SREG, so tie it to UREG 1744 if this is the last use of UREG, provided the classes they want 1745 are compatible. */ 1746 1747 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg)) 1748 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]])) 1749 { 1750 /* Add SREG to UREG's quantity. */ 1751 sqty = reg_qty[ureg]; 1752 reg_qty[sreg] = sqty; 1753 reg_offset[sreg] = reg_offset[ureg] + offset; 1754 reg_next_in_qty[sreg] = qty_first_reg[sqty]; 1755 qty_first_reg[sqty] = sreg; 1756 1757 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */ 1758 update_qty_class (sqty, sreg); 1759 1760 /* Update info about quantity SQTY. */ 1761 qty_n_calls_crossed[sqty] += REG_N_CALLS_CROSSED (sreg); 1762 qty_n_refs[sqty] += REG_N_REFS (sreg); 1763 if (usize < ssize) 1764 { 1765 register int i; 1766 1767 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i]) 1768 reg_offset[i] -= offset; 1769 1770 qty_size[sqty] = ssize; 1771 qty_mode[sqty] = GET_MODE (setreg); 1772 } 1773 } 1774 else 1775 return 0; 1776 1777 return 1; 1778} 1779 1780/* Return 1 if the preferred class of REG allows it to be tied 1781 to a quantity or register whose class is CLASS. 1782 True if REG's reg class either contains or is contained in CLASS. */ 1783 1784static int 1785reg_meets_class_p (reg, class) 1786 int reg; 1787 enum reg_class class; 1788{ 1789 register enum reg_class rclass = reg_preferred_class (reg); 1790 return (reg_class_subset_p (rclass, class) 1791 || reg_class_subset_p (class, rclass)); 1792} 1793 1794/* Update the class of QTY assuming that REG is being tied to it. */ 1795 1796static void 1797update_qty_class (qty, reg) 1798 int qty; 1799 int reg; 1800{ 1801 enum reg_class rclass = reg_preferred_class (reg); 1802 if (reg_class_subset_p (rclass, qty_min_class[qty])) 1803 qty_min_class[qty] = rclass; 1804 1805 rclass = reg_alternate_class (reg); 1806 if (reg_class_subset_p (rclass, qty_alternate_class[qty])) 1807 qty_alternate_class[qty] = rclass; 1808 1809 if (REG_CHANGES_SIZE (reg)) 1810 qty_changes_size[qty] = 1; 1811} 1812 1813/* Handle something which alters the value of an rtx REG. 1814 1815 REG is whatever is set or clobbered. SETTER is the rtx that 1816 is modifying the register. 1817 1818 If it is not really a register, we do nothing. 1819 The file-global variables `this_insn' and `this_insn_number' 1820 carry info from `block_alloc'. */ 1821 1822static void 1823reg_is_set (reg, setter) 1824 rtx reg; 1825 rtx setter; 1826{ 1827 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of 1828 a hard register. These may actually not exist any more. */ 1829 1830 if (GET_CODE (reg) != SUBREG 1831 && GET_CODE (reg) != REG) 1832 return; 1833 1834 /* Mark this register as being born. If it is used in a CLOBBER, mark 1835 it as being born halfway between the previous insn and this insn so that 1836 it conflicts with our inputs but not the outputs of the previous insn. */ 1837 1838 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER)); 1839} 1840 1841/* Handle beginning of the life of register REG. 1842 BIRTH is the index at which this is happening. */ 1843 1844static void 1845reg_is_born (reg, birth) 1846 rtx reg; 1847 int birth; 1848{ 1849 register int regno; 1850 1851 if (GET_CODE (reg) == SUBREG) 1852 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg); 1853 else 1854 regno = REGNO (reg); 1855 1856 if (regno < FIRST_PSEUDO_REGISTER) 1857 { 1858 mark_life (regno, GET_MODE (reg), 1); 1859 1860 /* If the register was to have been born earlier that the present 1861 insn, mark it as live where it is actually born. */ 1862 if (birth < 2 * this_insn_number) 1863 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number); 1864 } 1865 else 1866 { 1867 if (reg_qty[regno] == -2) 1868 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth); 1869 1870 /* If this register has a quantity number, show that it isn't dead. */ 1871 if (reg_qty[regno] >= 0) 1872 qty_death[reg_qty[regno]] = -1; 1873 } 1874} 1875 1876/* Record the death of REG in the current insn. If OUTPUT_P is non-zero, 1877 REG is an output that is dying (i.e., it is never used), otherwise it 1878 is an input (the normal case). 1879 If OUTPUT_P is 1, then we extend the life past the end of this insn. */ 1880 1881static void 1882wipe_dead_reg (reg, output_p) 1883 register rtx reg; 1884 int output_p; 1885{ 1886 register int regno = REGNO (reg); 1887 1888 /* If this insn has multiple results, 1889 and the dead reg is used in one of the results, 1890 extend its life to after this insn, 1891 so it won't get allocated together with any other result of this insn. 1892 1893 It is unsafe to use !single_set here since it will ignore an unused 1894 output. Just because an output is unused does not mean the compiler 1895 can assume the side effect will not occur. Consider if REG appears 1896 in the address of an output and we reload the output. If we allocate 1897 REG to the same hard register as an unused output we could set the hard 1898 register before the output reload insn. */ 1899 if (GET_CODE (PATTERN (this_insn)) == PARALLEL 1900 && multiple_sets (this_insn)) 1901 { 1902 int i; 1903 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--) 1904 { 1905 rtx set = XVECEXP (PATTERN (this_insn), 0, i); 1906 if (GET_CODE (set) == SET 1907 && GET_CODE (SET_DEST (set)) != REG 1908 && !rtx_equal_p (reg, SET_DEST (set)) 1909 && reg_overlap_mentioned_p (reg, SET_DEST (set))) 1910 output_p = 1; 1911 } 1912 } 1913 1914 /* If this register is used in an auto-increment address, then extend its 1915 life to after this insn, so that it won't get allocated together with 1916 the result of this insn. */ 1917 if (! output_p && find_regno_note (this_insn, REG_INC, regno)) 1918 output_p = 1; 1919 1920 if (regno < FIRST_PSEUDO_REGISTER) 1921 { 1922 mark_life (regno, GET_MODE (reg), 0); 1923 1924 /* If a hard register is dying as an output, mark it as in use at 1925 the beginning of this insn (the above statement would cause this 1926 not to happen). */ 1927 if (output_p) 1928 post_mark_life (regno, GET_MODE (reg), 1, 1929 2 * this_insn_number, 2 * this_insn_number+ 1); 1930 } 1931 1932 else if (reg_qty[regno] >= 0) 1933 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p; 1934} 1935 1936/* Find a block of SIZE words of hard regs in reg_class CLASS 1937 that can hold something of machine-mode MODE 1938 (but actually we test only the first of the block for holding MODE) 1939 and still free between insn BORN_INDEX and insn DEAD_INDEX, 1940 and return the number of the first of them. 1941 Return -1 if such a block cannot be found. 1942 If QTY crosses calls, insist on a register preserved by calls, 1943 unless ACCEPT_CALL_CLOBBERED is nonzero. 1944 1945 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested 1946 register is available. If not, return -1. */ 1947 1948static int 1949find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested, 1950 born_index, dead_index) 1951 enum reg_class class; 1952 enum machine_mode mode; 1953 int qty; 1954 int accept_call_clobbered; 1955 int just_try_suggested; 1956 int born_index, dead_index; 1957{ 1958 register int i, ins; 1959#ifdef HARD_REG_SET 1960 register /* Declare it register if it's a scalar. */ 1961#endif 1962 HARD_REG_SET used, first_used; 1963#ifdef ELIMINABLE_REGS 1964 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS; 1965#endif 1966 1967 /* Validate our parameters. */ 1968 if (born_index < 0 || born_index > dead_index) 1969 abort (); 1970 1971 /* Don't let a pseudo live in a reg across a function call 1972 if we might get a nonlocal goto. */ 1973 if (current_function_has_nonlocal_label 1974 && qty_n_calls_crossed[qty] > 0) 1975 return -1; 1976 1977 if (accept_call_clobbered) 1978 COPY_HARD_REG_SET (used, call_fixed_reg_set); 1979 else if (qty_n_calls_crossed[qty] == 0) 1980 COPY_HARD_REG_SET (used, fixed_reg_set); 1981 else 1982 COPY_HARD_REG_SET (used, call_used_reg_set); 1983 1984 if (accept_call_clobbered) 1985 IOR_HARD_REG_SET (used, losing_caller_save_reg_set); 1986 1987 for (ins = born_index; ins < dead_index; ins++) 1988 IOR_HARD_REG_SET (used, regs_live_at[ins]); 1989 1990 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]); 1991 1992 /* Don't use the frame pointer reg in local-alloc even if 1993 we may omit the frame pointer, because if we do that and then we 1994 need a frame pointer, reload won't know how to move the pseudo 1995 to another hard reg. It can move only regs made by global-alloc. 1996 1997 This is true of any register that can be eliminated. */ 1998#ifdef ELIMINABLE_REGS 1999 for (i = 0; i < (int)(sizeof eliminables / sizeof eliminables[0]); i++) 2000 SET_HARD_REG_BIT (used, eliminables[i].from); 2001#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM 2002 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one 2003 that it might be eliminated into. */ 2004 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM); 2005#endif 2006#else 2007 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM); 2008#endif 2009 2010#ifdef CLASS_CANNOT_CHANGE_SIZE 2011 if (qty_changes_size[qty]) 2012 IOR_HARD_REG_SET (used, 2013 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]); 2014#endif 2015 2016 /* Normally, the registers that can be used for the first register in 2017 a multi-register quantity are the same as those that can be used for 2018 subsequent registers. However, if just trying suggested registers, 2019 restrict our consideration to them. If there are copy-suggested 2020 register, try them. Otherwise, try the arithmetic-suggested 2021 registers. */ 2022 COPY_HARD_REG_SET (first_used, used); 2023 2024 if (just_try_suggested) 2025 { 2026 if (qty_phys_num_copy_sugg[qty] != 0) 2027 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]); 2028 else 2029 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]); 2030 } 2031 2032 /* If all registers are excluded, we can't do anything. */ 2033 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail); 2034 2035 /* If at least one would be suitable, test each hard reg. */ 2036 2037 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 2038 { 2039#ifdef REG_ALLOC_ORDER 2040 int regno = reg_alloc_order[i]; 2041#else 2042 int regno = i; 2043#endif 2044 if (! TEST_HARD_REG_BIT (first_used, regno) 2045 && HARD_REGNO_MODE_OK (regno, mode) 2046 && (qty_n_calls_crossed[qty] == 0 2047 || accept_call_clobbered 2048 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) 2049 { 2050 register int j; 2051 register int size1 = HARD_REGNO_NREGS (regno, mode); 2052 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++); 2053 if (j == size1) 2054 { 2055 /* Mark that this register is in use between its birth and death 2056 insns. */ 2057 post_mark_life (regno, mode, 1, born_index, dead_index); 2058 return regno; 2059 } 2060#ifndef REG_ALLOC_ORDER 2061 i += j; /* Skip starting points we know will lose */ 2062#endif 2063 } 2064 } 2065 2066 fail: 2067 2068 /* If we are just trying suggested register, we have just tried copy- 2069 suggested registers, and there are arithmetic-suggested registers, 2070 try them. */ 2071 2072 /* If it would be profitable to allocate a call-clobbered register 2073 and save and restore it around calls, do that. */ 2074 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0 2075 && qty_phys_num_sugg[qty] != 0) 2076 { 2077 /* Don't try the copy-suggested regs again. */ 2078 qty_phys_num_copy_sugg[qty] = 0; 2079 return find_free_reg (class, mode, qty, accept_call_clobbered, 1, 2080 born_index, dead_index); 2081 } 2082 2083 /* We need not check to see if the current function has nonlocal 2084 labels because we don't put any pseudos that are live over calls in 2085 registers in that case. */ 2086 2087 if (! accept_call_clobbered 2088 && flag_caller_saves 2089 && ! just_try_suggested 2090 && qty_n_calls_crossed[qty] != 0 2091 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty])) 2092 { 2093 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index); 2094 if (i >= 0) 2095 caller_save_needed = 1; 2096 return i; 2097 } 2098 return -1; 2099} 2100 2101/* Mark that REGNO with machine-mode MODE is live starting from the current 2102 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE 2103 is zero). */ 2104 2105static void 2106mark_life (regno, mode, life) 2107 register int regno; 2108 enum machine_mode mode; 2109 int life; 2110{ 2111 register int j = HARD_REGNO_NREGS (regno, mode); 2112 if (life) 2113 while (--j >= 0) 2114 SET_HARD_REG_BIT (regs_live, regno + j); 2115 else 2116 while (--j >= 0) 2117 CLEAR_HARD_REG_BIT (regs_live, regno + j); 2118} 2119 2120/* Mark register number REGNO (with machine-mode MODE) as live (if LIFE 2121 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive) 2122 to insn number DEATH (exclusive). */ 2123 2124static void 2125post_mark_life (regno, mode, life, birth, death) 2126 int regno; 2127 enum machine_mode mode; 2128 int life, birth, death; 2129{ 2130 register int j = HARD_REGNO_NREGS (regno, mode); 2131#ifdef HARD_REG_SET 2132 register /* Declare it register if it's a scalar. */ 2133#endif 2134 HARD_REG_SET this_reg; 2135 2136 CLEAR_HARD_REG_SET (this_reg); 2137 while (--j >= 0) 2138 SET_HARD_REG_BIT (this_reg, regno + j); 2139 2140 if (life) 2141 while (birth < death) 2142 { 2143 IOR_HARD_REG_SET (regs_live_at[birth], this_reg); 2144 birth++; 2145 } 2146 else 2147 while (birth < death) 2148 { 2149 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg); 2150 birth++; 2151 } 2152} 2153 2154/* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0 2155 is the register being clobbered, and R1 is a register being used in 2156 the equivalent expression. 2157 2158 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn 2159 in which it is used, return 1. 2160 2161 Otherwise, return 0. */ 2162 2163static int 2164no_conflict_p (insn, r0, r1) 2165 rtx insn, r0, r1; 2166{ 2167 int ok = 0; 2168 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX); 2169 rtx p, last; 2170 2171 /* If R1 is a hard register, return 0 since we handle this case 2172 when we scan the insns that actually use it. */ 2173 2174 if (note == 0 2175 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER) 2176 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG 2177 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER)) 2178 return 0; 2179 2180 last = XEXP (note, 0); 2181 2182 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p)) 2183 if (GET_RTX_CLASS (GET_CODE (p)) == 'i') 2184 { 2185 if (find_reg_note (p, REG_DEAD, r1)) 2186 ok = 1; 2187 2188 /* There must be a REG_NO_CONFLICT note on every insn, otherwise 2189 some earlier optimization pass has inserted instructions into 2190 the sequence, and it is not safe to perform this optimization. 2191 Note that emit_no_conflict_block always ensures that this is 2192 true when these sequences are created. */ 2193 if (! find_reg_note (p, REG_NO_CONFLICT, r1)) 2194 return 0; 2195 } 2196 2197 return ok; 2198} 2199 2200#ifdef REGISTER_CONSTRAINTS 2201 2202/* Return the number of alternatives for which the constraint string P 2203 indicates that the operand must be equal to operand 0 and that no register 2204 is acceptable. */ 2205 2206static int 2207requires_inout (p) 2208 const char *p; 2209{ 2210 char c; 2211 int found_zero = 0; 2212 int reg_allowed = 0; 2213 int num_matching_alts = 0; 2214 2215 while ((c = *p++)) 2216 switch (c) 2217 { 2218 case '=': case '+': case '?': 2219 case '#': case '&': case '!': 2220 case '*': case '%': 2221 case '1': case '2': case '3': case '4': 2222 case 'm': case '<': case '>': case 'V': case 'o': 2223 case 'E': case 'F': case 'G': case 'H': 2224 case 's': case 'i': case 'n': 2225 case 'I': case 'J': case 'K': case 'L': 2226 case 'M': case 'N': case 'O': case 'P': 2227#ifdef EXTRA_CONSTRAINT 2228 case 'Q': case 'R': case 'S': case 'T': case 'U': 2229#endif 2230 case 'X': 2231 /* These don't say anything we care about. */ 2232 break; 2233 2234 case ',': 2235 if (found_zero && ! reg_allowed) 2236 num_matching_alts++; 2237 2238 found_zero = reg_allowed = 0; 2239 break; 2240 2241 case '0': 2242 found_zero = 1; 2243 break; 2244 2245 case 'p': 2246 case 'g': case 'r': 2247 default: 2248 reg_allowed = 1; 2249 break; 2250 } 2251 2252 if (found_zero && ! reg_allowed) 2253 num_matching_alts++; 2254 2255 return num_matching_alts; 2256} 2257#endif /* REGISTER_CONSTRAINTS */ 2258 2259void 2260dump_local_alloc (file) 2261 FILE *file; 2262{ 2263 register int i; 2264 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 2265 if (reg_renumber[i] != -1) 2266 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]); 2267} 2268