1/* Subroutines for insn-output.c for Matsushita MN10300 series 2 Copyright (C) 1996, 1997 Free Software Foundation, Inc. 3 Contributed by Jeff Law (law@cygnus.com). 4 5This file is part of GNU CC. 6 7GNU CC is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2, or (at your option) 10any later version. 11 12GNU CC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GNU CC; see the file COPYING. If not, write to 19the Free Software Foundation, 59 Temple Place - Suite 330, 20Boston, MA 02111-1307, USA. */ 21 22#include "config.h" 23#include <stdio.h> 24#include "rtl.h" 25#include "regs.h" 26#include "hard-reg-set.h" 27#include "real.h" 28#include "insn-config.h" 29#include "conditions.h" 30#include "insn-flags.h" 31#include "output.h" 32#include "insn-attr.h" 33#include "flags.h" 34#include "recog.h" 35#include "expr.h" 36#include "tree.h" 37#include "obstack.h" 38 39/* The size of the callee register save area. Right now we save everything 40 on entry since it costs us nothing in code size. It does cost us from a 41 speed standpoint, so we want to optimize this sooner or later. */ 42#define REG_SAVE_BYTES (4 * regs_ever_live[2] \ 43 + 4 * regs_ever_live[3] \ 44 + 4 * regs_ever_live[6] \ 45 + 4 * regs_ever_live[7]) 46 47void 48asm_file_start (file) 49 FILE *file; 50{ 51 fprintf (file, "#\tGCC For the Matsushita MN10300\n"); 52 if (optimize) 53 fprintf (file, "# -O%d\n", optimize); 54 else 55 fprintf (file, "\n\n"); 56 output_file_directive (file, main_input_filename); 57} 58 59 60/* Print operand X using operand code CODE to assembly language output file 61 FILE. */ 62 63void 64print_operand (file, x, code) 65 FILE *file; 66 rtx x; 67 int code; 68{ 69 switch (code) 70 { 71 case 'b': 72 case 'B': 73 /* These are normal and reversed branches. */ 74 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) 75 { 76 case NE: 77 fprintf (file, "ne"); 78 break; 79 case EQ: 80 fprintf (file, "eq"); 81 break; 82 case GE: 83 fprintf (file, "ge"); 84 break; 85 case GT: 86 fprintf (file, "gt"); 87 break; 88 case LE: 89 fprintf (file, "le"); 90 break; 91 case LT: 92 fprintf (file, "lt"); 93 break; 94 case GEU: 95 fprintf (file, "cc"); 96 break; 97 case GTU: 98 fprintf (file, "hi"); 99 break; 100 case LEU: 101 fprintf (file, "ls"); 102 break; 103 case LTU: 104 fprintf (file, "cs"); 105 break; 106 default: 107 abort (); 108 } 109 break; 110 case 'C': 111 /* This is used for the operand to a call instruction; 112 if it's a REG, enclose it in parens, else output 113 the operand normally. */ 114 if (GET_CODE (x) == REG) 115 { 116 fputc ('(', file); 117 print_operand (file, x, 0); 118 fputc (')', file); 119 } 120 else 121 print_operand (file, x, 0); 122 break; 123 124 /* These are the least significant word in a 64bit value. */ 125 case 'L': 126 switch (GET_CODE (x)) 127 { 128 case MEM: 129 fputc ('(', file); 130 output_address (XEXP (x, 0)); 131 fputc (')', file); 132 break; 133 134 case REG: 135 fprintf (file, "%s", reg_names[REGNO (x)]); 136 break; 137 138 case SUBREG: 139 fprintf (file, "%s", 140 reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]); 141 break; 142 143 case CONST_DOUBLE: 144 { 145 long val[2]; 146 REAL_VALUE_TYPE rv; 147 148 switch (GET_MODE (x)) 149 { 150 case DFmode: 151 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 152 REAL_VALUE_TO_TARGET_DOUBLE (rv, val); 153 print_operand_address (file, GEN_INT (val[0])); 154 break;; 155 case SFmode: 156 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 157 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); 158 print_operand_address (file, GEN_INT (val[0])); 159 break;; 160 case VOIDmode: 161 case DImode: 162 print_operand_address (file, 163 GEN_INT (CONST_DOUBLE_LOW (x))); 164 break; 165 } 166 break; 167 } 168 169 case CONST_INT: 170 print_operand_address (file, x); 171 break; 172 173 default: 174 abort (); 175 } 176 break; 177 178 /* Similarly, but for the most significant word. */ 179 case 'H': 180 switch (GET_CODE (x)) 181 { 182 case MEM: 183 fputc ('(', file); 184 x = adj_offsettable_operand (x, 4); 185 output_address (XEXP (x, 0)); 186 fputc (')', file); 187 break; 188 189 case REG: 190 fprintf (file, "%s", reg_names[REGNO (x) + 1]); 191 break; 192 193 case SUBREG: 194 fprintf (file, "%s", 195 reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)] + 1); 196 break; 197 198 case CONST_DOUBLE: 199 { 200 long val[2]; 201 REAL_VALUE_TYPE rv; 202 203 switch (GET_MODE (x)) 204 { 205 case DFmode: 206 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 207 REAL_VALUE_TO_TARGET_DOUBLE (rv, val); 208 print_operand_address (file, GEN_INT (val[1])); 209 break;; 210 case SFmode: 211 abort (); 212 case VOIDmode: 213 case DImode: 214 print_operand_address (file, 215 GEN_INT (CONST_DOUBLE_HIGH (x))); 216 break; 217 } 218 break; 219 } 220 221 case CONST_INT: 222 if (INTVAL (x) < 0) 223 print_operand_address (file, GEN_INT (-1)); 224 else 225 print_operand_address (file, GEN_INT (0)); 226 break; 227 default: 228 abort (); 229 } 230 break; 231 232 case 'A': 233 fputc ('(', file); 234 if (GET_CODE (XEXP (x, 0)) == REG) 235 output_address (gen_rtx (PLUS, SImode, XEXP (x, 0), GEN_INT (0))); 236 else 237 output_address (XEXP (x, 0)); 238 fputc (')', file); 239 break; 240 241 case 'N': 242 output_address (GEN_INT ((~INTVAL (x)) & 0xff)); 243 break; 244 245 /* For shift counts. The hardware ignores the upper bits of 246 any immediate, but the assembler will flag an out of range 247 shift count as an error. So we mask off the high bits 248 of the immediate here. */ 249 case 'S': 250 if (GET_CODE (x) == CONST_INT) 251 { 252 fprintf (file, "%d", INTVAL (x) & 0x1f); 253 break; 254 } 255 /* FALL THROUGH */ 256 257 default: 258 switch (GET_CODE (x)) 259 { 260 case MEM: 261 fputc ('(', file); 262 output_address (XEXP (x, 0)); 263 fputc (')', file); 264 break; 265 266 case PLUS: 267 output_address (x); 268 break; 269 270 case REG: 271 fprintf (file, "%s", reg_names[REGNO (x)]); 272 break; 273 274 case SUBREG: 275 fprintf (file, "%s", 276 reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]); 277 break; 278 279 /* This will only be single precision.... */ 280 case CONST_DOUBLE: 281 { 282 unsigned long val; 283 REAL_VALUE_TYPE rv; 284 285 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 286 REAL_VALUE_TO_TARGET_SINGLE (rv, val); 287 print_operand_address (file, GEN_INT (val)); 288 break; 289 } 290 291 case CONST_INT: 292 case SYMBOL_REF: 293 case CONST: 294 case LABEL_REF: 295 case CODE_LABEL: 296 print_operand_address (file, x); 297 break; 298 default: 299 abort (); 300 } 301 break; 302 } 303} 304 305/* Output assembly language output for the address ADDR to FILE. */ 306 307void 308print_operand_address (file, addr) 309 FILE *file; 310 rtx addr; 311{ 312 switch (GET_CODE (addr)) 313 { 314 case REG: 315 if (addr == stack_pointer_rtx) 316 print_operand_address (file, gen_rtx (PLUS, SImode, 317 stack_pointer_rtx, 318 GEN_INT (0))); 319 else 320 print_operand (file, addr, 0); 321 break; 322 case PLUS: 323 { 324 rtx base, index; 325 if (REG_P (XEXP (addr, 0)) 326 && REG_OK_FOR_BASE_P (XEXP (addr, 0))) 327 base = XEXP (addr, 0), index = XEXP (addr, 1); 328 else if (REG_P (XEXP (addr, 1)) 329 && REG_OK_FOR_BASE_P (XEXP (addr, 1))) 330 base = XEXP (addr, 1), index = XEXP (addr, 0); 331 else 332 abort (); 333 print_operand (file, index, 0); 334 fputc (',', file); 335 print_operand (file, base, 0);; 336 break; 337 } 338 case SYMBOL_REF: 339 output_addr_const (file, addr); 340 break; 341 default: 342 output_addr_const (file, addr); 343 break; 344 } 345} 346 347int 348can_use_return_insn () 349{ 350 /* size includes the fixed stack space needed for function calls. */ 351 int size = get_frame_size () + current_function_outgoing_args_size; 352 353 /* And space for the return pointer. */ 354 size += current_function_outgoing_args_size ? 4 : 0; 355 356 return (reload_completed 357 && size == 0 358 && !regs_ever_live[2] 359 && !regs_ever_live[3] 360 && !regs_ever_live[6] 361 && !regs_ever_live[7] 362 && !frame_pointer_needed); 363} 364 365void 366expand_prologue () 367{ 368 unsigned int size; 369 370 /* SIZE includes the fixed stack space needed for function calls. */ 371 size = get_frame_size () + current_function_outgoing_args_size; 372 size += (current_function_outgoing_args_size ? 4 : 0); 373 374 /* If this is an old-style varargs function, then its arguments 375 need to be flushed back to the stack. */ 376 if (current_function_varargs) 377 { 378 emit_move_insn (gen_rtx (MEM, SImode, 379 gen_rtx (PLUS, Pmode, stack_pointer_rtx, 380 GEN_INT (4))), 381 gen_rtx (REG, SImode, 0)); 382 emit_move_insn (gen_rtx (MEM, SImode, 383 gen_rtx (PLUS, Pmode, stack_pointer_rtx, 384 GEN_INT (8))), 385 gen_rtx (REG, SImode, 1)); 386 } 387 388 /* And now store all the registers onto the stack with a 389 single two byte instruction. */ 390 if (regs_ever_live[2] || regs_ever_live[3] 391 || regs_ever_live[6] || regs_ever_live[7] 392 || frame_pointer_needed) 393 emit_insn (gen_store_movm ()); 394 395 /* Now put the frame pointer into the frame pointer register. */ 396 if (frame_pointer_needed) 397 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); 398 399 /* Allocate stack for this frame. */ 400 if (size) 401 emit_insn (gen_addsi3 (stack_pointer_rtx, 402 stack_pointer_rtx, 403 GEN_INT (-size))); 404} 405 406void 407expand_epilogue () 408{ 409 unsigned int size; 410 411 /* SIZE includes the fixed stack space needed for function calls. */ 412 size = get_frame_size () + current_function_outgoing_args_size; 413 size += (current_function_outgoing_args_size ? 4 : 0); 414 415 /* Maybe cut back the stack, except for the register save area. 416 417 If the frame pointer exists, then use the frame pointer to 418 cut back the stack. 419 420 If the stack size + register save area is more than 255 bytes, 421 then the stack must be cut back here since the size + register 422 save size is too big for a ret/retf instruction. 423 424 Else leave it alone, it will be cut back as part of the 425 ret/retf instruction, or there wasn't any stack to begin with. 426 427 Under no circumstanes should the register save area be 428 deallocated here, that would leave a window where an interrupt 429 could occur and trash the register save area. */ 430 if (frame_pointer_needed) 431 { 432 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); 433 size = 0; 434 } 435 else if ((regs_ever_live[2] || regs_ever_live[3] 436 || regs_ever_live[6] || regs_ever_live[7]) 437 && size + REG_SAVE_BYTES > 255) 438 { 439 emit_insn (gen_addsi3 (stack_pointer_rtx, 440 stack_pointer_rtx, 441 GEN_INT (size))); 442 size = 0; 443 } 444 445 /* For simplicity, we just movm all the callee saved registers to 446 the stack with one instruction. 447 448 ?!? Only save registers which are actually used. Reduces 449 stack requirements and is faster. */ 450 if (regs_ever_live[2] || regs_ever_live[3] 451 || regs_ever_live[6] || regs_ever_live[7] 452 || frame_pointer_needed) 453 emit_jump_insn (gen_return_internal_regs (GEN_INT (size + REG_SAVE_BYTES))); 454 else 455 { 456 if (size) 457 { 458 emit_insn (gen_addsi3 (stack_pointer_rtx, 459 stack_pointer_rtx, 460 GEN_INT (size))); 461 emit_jump_insn (gen_return_internal ()); 462 } 463 else 464 { 465 emit_jump_insn (gen_return ()); 466 } 467 } 468} 469 470/* Update the condition code from the insn. */ 471 472void 473notice_update_cc (body, insn) 474 rtx body; 475 rtx insn; 476{ 477 switch (get_attr_cc (insn)) 478 { 479 case CC_NONE: 480 /* Insn does not affect CC at all. */ 481 break; 482 483 case CC_NONE_0HIT: 484 /* Insn does not change CC, but the 0'th operand has been changed. */ 485 if (cc_status.value1 != 0 486 && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1)) 487 cc_status.value1 = 0; 488 break; 489 490 case CC_SET_ZN: 491 /* Insn sets the Z,N flags of CC to recog_operand[0]. 492 V,C are unusable. */ 493 CC_STATUS_INIT; 494 cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE; 495 cc_status.value1 = recog_operand[0]; 496 break; 497 498 case CC_SET_ZNV: 499 /* Insn sets the Z,N,V flags of CC to recog_operand[0]. 500 C is unusable. */ 501 CC_STATUS_INIT; 502 cc_status.flags |= CC_NO_CARRY; 503 cc_status.value1 = recog_operand[0]; 504 break; 505 506 case CC_COMPARE: 507 /* The insn is a compare instruction. */ 508 CC_STATUS_INIT; 509 cc_status.value1 = SET_SRC (body); 510 break; 511 512 case CC_INVERT: 513 /* The insn is a compare instruction. */ 514 CC_STATUS_INIT; 515 cc_status.value1 = SET_SRC (body); 516 cc_status.flags |= CC_INVERTED; 517 break; 518 519 case CC_CLOBBER: 520 /* Insn doesn't leave CC in a usable state. */ 521 CC_STATUS_INIT; 522 break; 523 524 default: 525 abort (); 526 } 527} 528 529/* Return true if OP is a valid call operand. */ 530 531int 532call_address_operand (op, mode) 533 rtx op; 534 enum machine_mode mode; 535{ 536 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG); 537} 538 539/* What (if any) secondary registers are needed to move IN with mode 540 MODE into a register from in register class CLASS. 541 542 We might be able to simplify this. */ 543enum reg_class 544secondary_reload_class (class, mode, in) 545 enum reg_class class; 546 enum machine_mode mode; 547 rtx in; 548{ 549 int regno; 550 551 /* Memory loads less than a full word wide can't have an 552 address or stack pointer destination. They must use 553 a data register as an intermediate register. */ 554 if (GET_CODE (in) == MEM 555 && (mode == QImode || mode == HImode) 556 && (class == ADDRESS_REGS || class == SP_REGS)) 557 { 558 return DATA_REGS; 559 } 560 561 /* We can't directly load sp + const_int into a data register; 562 we must use an address register as an intermediate. */ 563 if (class != SP_REGS 564 && class != ADDRESS_REGS 565 && class != SP_OR_ADDRESS_REGS 566 && (in == stack_pointer_rtx 567 || (GET_CODE (in) == PLUS 568 && (XEXP (in, 0) == stack_pointer_rtx 569 || XEXP (in, 1) == stack_pointer_rtx)))) 570 return ADDRESS_REGS; 571 572 if (GET_CODE (in) == PLUS 573 && (XEXP (in, 0) == stack_pointer_rtx 574 || XEXP (in, 1) == stack_pointer_rtx)) 575 { 576 return DATA_REGS; 577 } 578 579 /* Otherwise assume no secondary reloads are needed. */ 580 return NO_REGS; 581} 582 583int 584initial_offset (from, to) 585 int from, to; 586{ 587 /* The difference between the argument pointer and the frame pointer 588 is the size of the callee register save area. */ 589 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) 590 { 591 if (regs_ever_live[2] || regs_ever_live[3] 592 || regs_ever_live[6] || regs_ever_live[7] 593 || frame_pointer_needed) 594 return REG_SAVE_BYTES; 595 else 596 return 0; 597 } 598 599 /* The difference between the argument pointer and the stack pointer is 600 the sum of the size of this function's frame, the callee register save 601 area, and the fixed stack space needed for function calls (if any). */ 602 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) 603 { 604 if (regs_ever_live[2] || regs_ever_live[3] 605 || regs_ever_live[6] || regs_ever_live[7] 606 || frame_pointer_needed) 607 return (get_frame_size () + REG_SAVE_BYTES 608 + (current_function_outgoing_args_size 609 ? current_function_outgoing_args_size + 4 : 0)); 610 else 611 return (get_frame_size () 612 + (current_function_outgoing_args_size 613 ? current_function_outgoing_args_size + 4 : 0)); 614 } 615 616 /* The difference between the frame pointer and stack pointer is the sum 617 of the size of this function's frame and the fixed stack space needed 618 for function calls (if any). */ 619 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) 620 return (get_frame_size () 621 + (current_function_outgoing_args_size 622 ? current_function_outgoing_args_size + 4 : 0)); 623 624 abort (); 625} 626 627/* Flush the argument registers to the stack for a stdarg function; 628 return the new argument pointer. */ 629rtx 630mn10300_builtin_saveregs (arglist) 631 tree arglist; 632{ 633 rtx offset; 634 tree fntype = TREE_TYPE (current_function_decl); 635 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 636 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) 637 != void_type_node))) 638 ? UNITS_PER_WORD : 0); 639 640 if (argadj) 641 offset = plus_constant (current_function_arg_offset_rtx, argadj); 642 else 643 offset = current_function_arg_offset_rtx; 644 645 emit_move_insn (gen_rtx (MEM, SImode, current_function_internal_arg_pointer), 646 gen_rtx (REG, SImode, 0)); 647 emit_move_insn (gen_rtx (MEM, SImode, 648 plus_constant 649 (current_function_internal_arg_pointer, 4)), 650 gen_rtx (REG, SImode, 1)); 651 return copy_to_reg (expand_binop (Pmode, add_optab, 652 current_function_internal_arg_pointer, 653 offset, 0, 0, OPTAB_LIB_WIDEN)); 654} 655 656/* Return an RTX to represent where a value with mode MODE will be returned 657 from a function. If the result is 0, the argument is pushed. */ 658 659rtx 660function_arg (cum, mode, type, named) 661 CUMULATIVE_ARGS *cum; 662 enum machine_mode mode; 663 tree type; 664 int named; 665{ 666 rtx result = 0; 667 int size, align; 668 669 /* We only support using 2 data registers as argument registers. */ 670 int nregs = 2; 671 672 /* Figure out the size of the object to be passed. */ 673 if (mode == BLKmode) 674 size = int_size_in_bytes (type); 675 else 676 size = GET_MODE_SIZE (mode); 677 678 /* Figure out the alignment of the object to be passed. */ 679 align = size; 680 681 cum->nbytes = (cum->nbytes + 3) & ~3; 682 683 /* Don't pass this arg via a register if all the argument registers 684 are used up. */ 685 if (cum->nbytes > nregs * UNITS_PER_WORD) 686 return 0; 687 688 /* Don't pass this arg via a register if it would be split between 689 registers and memory. */ 690 if (type == NULL_TREE 691 && cum->nbytes + size > nregs * UNITS_PER_WORD) 692 return 0; 693 694 switch (cum->nbytes / UNITS_PER_WORD) 695 { 696 case 0: 697 result = gen_rtx (REG, mode, 0); 698 break; 699 case 1: 700 result = gen_rtx (REG, mode, 1); 701 break; 702 default: 703 result = 0; 704 } 705 706 return result; 707} 708 709/* Return the number of registers to use for an argument passed partially 710 in registers and partially in memory. */ 711 712int 713function_arg_partial_nregs (cum, mode, type, named) 714 CUMULATIVE_ARGS *cum; 715 enum machine_mode mode; 716 tree type; 717 int named; 718{ 719 int size, align; 720 721 /* We only support using 2 data registers as argument registers. */ 722 int nregs = 2; 723 724 /* Figure out the size of the object to be passed. */ 725 if (mode == BLKmode) 726 size = int_size_in_bytes (type); 727 else 728 size = GET_MODE_SIZE (mode); 729 730 /* Figure out the alignment of the object to be passed. */ 731 align = size; 732 733 cum->nbytes = (cum->nbytes + 3) & ~3; 734 735 /* Don't pass this arg via a register if all the argument registers 736 are used up. */ 737 if (cum->nbytes > nregs * UNITS_PER_WORD) 738 return 0; 739 740 if (cum->nbytes + size <= nregs * UNITS_PER_WORD) 741 return 0; 742 743 /* Don't pass this arg via a register if it would be split between 744 registers and memory. */ 745 if (type == NULL_TREE 746 && cum->nbytes + size > nregs * UNITS_PER_WORD) 747 return 0; 748 749 return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD; 750} 751 752/* Output a tst insn. */ 753char * 754output_tst (operand, insn) 755 rtx operand, insn; 756{ 757 rtx temp; 758 int past_call = 0; 759 760 /* We can save a byte if we can find a register which has the value 761 zero in it. */ 762 temp = PREV_INSN (insn); 763 while (optimize && temp) 764 { 765 rtx set; 766 767 /* We allow the search to go through call insns. We record 768 the fact that we've past a CALL_INSN and reject matches which 769 use call clobbered registers. */ 770 if (GET_CODE (temp) == CODE_LABEL 771 || GET_CODE (temp) == JUMP_INSN 772 || GET_CODE (temp) == BARRIER) 773 break; 774 775 if (GET_CODE (temp) == CALL_INSN) 776 past_call = 1; 777 778 if (GET_CODE (temp) == NOTE) 779 { 780 temp = PREV_INSN (temp); 781 continue; 782 } 783 784 /* It must be an insn, see if it is a simple set. */ 785 set = single_set (temp); 786 if (!set) 787 { 788 temp = PREV_INSN (temp); 789 continue; 790 } 791 792 /* Are we setting a data register to zero (this does not win for 793 address registers)? 794 795 If it's a call clobbered register, have we past a call? 796 797 Make sure the register we find isn't the same as ourself; 798 the mn10300 can't encode that. 799 800 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN 801 so the code to detect calls here isn't doing anything useful. */ 802 if (REG_P (SET_DEST (set)) 803 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) 804 && !reg_set_between_p (SET_DEST (set), temp, insn) 805 && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) 806 == REGNO_REG_CLASS (REGNO (operand))) 807 && REGNO (SET_DEST (set)) != REGNO (operand) 808 && (!past_call 809 || !call_used_regs[REGNO (SET_DEST (set))])) 810 { 811 rtx xoperands[2]; 812 xoperands[0] = operand; 813 xoperands[1] = SET_DEST (set); 814 815 output_asm_insn ("cmp %1,%0", xoperands); 816 return ""; 817 } 818 temp = PREV_INSN (temp); 819 } 820 return "cmp 0,%0"; 821} 822 823int 824impossible_plus_operand (op, mode) 825 rtx op; 826 enum machine_mode mode; 827{ 828 extern rtx *reg_equiv_mem; 829 rtx reg1, reg2; 830 831 if (GET_CODE (op) != PLUS) 832 return 0; 833 834 if (XEXP (op, 0) == stack_pointer_rtx 835 || XEXP (op, 1) == stack_pointer_rtx) 836 return 1; 837 838 return 0; 839} 840 841/* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used 842 for the btst insn which may examine memory or a register (the memory 843 variant only allows an unsigned 8 bit integer). */ 844int 845const_8bit_operand (op, mode) 846 register rtx op; 847 enum machine_mode mode; 848{ 849 return (GET_CODE (op) == CONST_INT 850 && INTVAL (op) >= 0 851 && INTVAL (op) < 256); 852} 853 854/* Similarly, but when using a zero_extract pattern for a btst where 855 the source operand might end up in memory. */ 856int 857mask_ok_for_mem_btst (len, bit) 858 int len; 859 int bit; 860{ 861 int mask = 0; 862 863 while (len > 0) 864 { 865 mask |= (1 << bit); 866 bit++; 867 len--; 868 } 869 870 /* MASK must bit into an 8bit value. */ 871 return (((mask & 0xff) == mask) 872 || ((mask & 0xff00) == mask) 873 || ((mask & 0xff0000) == mask) 874 || ((mask & 0xff000000) == mask)); 875} 876 877/* Return 1 if X contains a symbolic expression. We know these 878 expressions will have one of a few well defined forms, so 879 we need only check those forms. */ 880int 881symbolic_operand (op, mode) 882 register rtx op; 883 enum machine_mode mode; 884{ 885 switch (GET_CODE (op)) 886 { 887 case SYMBOL_REF: 888 case LABEL_REF: 889 return 1; 890 case CONST: 891 op = XEXP (op, 0); 892 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF 893 || GET_CODE (XEXP (op, 0)) == LABEL_REF) 894 && GET_CODE (XEXP (op, 1)) == CONST_INT); 895 default: 896 return 0; 897 } 898} 899 900/* Try machine dependent ways of modifying an illegitimate address 901 to be legitimate. If we find one, return the new valid address. 902 This macro is used in only one place: `memory_address' in explow.c. 903 904 OLDX is the address as it was before break_out_memory_refs was called. 905 In some cases it is useful to look at this to decide what needs to be done. 906 907 MODE and WIN are passed so that this macro can use 908 GO_IF_LEGITIMATE_ADDRESS. 909 910 Normally it is always safe for this macro to do nothing. It exists to 911 recognize opportunities to optimize the output. 912 913 But on a few ports with segmented architectures and indexed addressing 914 (mn10300, hppa) it is used to rewrite certain problematical addresses. */ 915rtx 916legitimize_address (x, oldx, mode) 917 rtx x; 918 rtx oldx; 919 enum machine_mode mode; 920{ 921 /* Uh-oh. We might have an address for x[n-100000]. This needs 922 special handling to avoid creating an indexed memory address 923 with x-100000 as the base. */ 924 if (GET_CODE (x) == PLUS 925 && symbolic_operand (XEXP (x, 1), VOIDmode)) 926 { 927 /* Ugly. We modify things here so that the address offset specified 928 by the index expression is computed first, then added to x to form 929 the entire address. */ 930 931 rtx regx1, regx2, regy1, regy2, y; 932 933 /* Strip off any CONST. */ 934 y = XEXP (x, 1); 935 if (GET_CODE (y) == CONST) 936 y = XEXP (y, 0); 937 938 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) 939 { 940 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); 941 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); 942 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); 943 regx1 = force_reg (Pmode, 944 gen_rtx (GET_CODE (y), Pmode, regx1, regy2)); 945 return force_reg (Pmode, gen_rtx (PLUS, Pmode, regx1, regy1)); 946 } 947 } 948 return x; 949} 950