1/* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000 3 Free Software Foundation, Inc. 4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 5 and Martin Simmons (@harleqn.co.uk). 6 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk) 7 8This file is part of GNU CC. 9 10GNU CC is free software; you can redistribute it and/or modify 11it under the terms of the GNU General Public License as published by 12the Free Software Foundation; either version 2, or (at your option) 13any later version. 14 15GNU CC is distributed in the hope that it will be useful, 16but WITHOUT ANY WARRANTY; without even the implied warranty of 17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18GNU General Public License for more details. 19 20You should have received a copy of the GNU General Public License 21along with GNU CC; see the file COPYING. If not, write to 22the Free Software Foundation, 59 Temple Place - Suite 330, 23Boston, MA 02111-1307, USA. */ 24 25/* Configuration triples for ARM ports work as follows: 26 (This is a bit of a mess and needs some thought) 27 arm-*-*: little endian 28 armel-*-*: little endian 29 armeb-*-*: big endian 30 If a non-embedded environment (ie: "real" OS) is specified, `arm' 31 should default to that used by the OS. 32*/ 33 34#ifndef __ARM_H__ 35#define __ARM_H__ 36 37#define TARGET_CPU_arm2 0x0000 38#define TARGET_CPU_arm250 0x0000 39#define TARGET_CPU_arm3 0x0000 40#define TARGET_CPU_arm6 0x0001 41#define TARGET_CPU_arm600 0x0001 42#define TARGET_CPU_arm610 0x0002 43#define TARGET_CPU_arm7 0x0001 44#define TARGET_CPU_arm7m 0x0004 45#define TARGET_CPU_arm7dm 0x0004 46#define TARGET_CPU_arm7dmi 0x0004 47#define TARGET_CPU_arm700 0x0001 48#define TARGET_CPU_arm710 0x0002 49#define TARGET_CPU_arm7100 0x0002 50#define TARGET_CPU_arm7500 0x0002 51#define TARGET_CPU_arm7500fe 0x1001 52#define TARGET_CPU_arm7tdmi 0x0008 53#define TARGET_CPU_arm8 0x0010 54#define TARGET_CPU_arm810 0x0020 55#define TARGET_CPU_strongarm 0x0040 56#define TARGET_CPU_strongarm110 0x0040 57#define TARGET_CPU_strongarm1100 0x0040 58#define TARGET_CPU_arm9 0x0080 59#define TARGET_CPU_arm9tdmi 0x0080 60/* Configure didn't specify */ 61#define TARGET_CPU_generic 0x8000 62 63enum arm_cond_code 64{ 65 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 66 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 67}; 68extern enum arm_cond_code arm_current_cc; 69extern char *arm_condition_codes[]; 70 71#define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1)) 72 73/* This is needed by the tail-calling peepholes */ 74extern int frame_pointer_needed; 75 76 77/* Just in case configure has failed to define anything. */ 78#ifndef TARGET_CPU_DEFAULT 79#define TARGET_CPU_DEFAULT TARGET_CPU_generic 80#endif 81 82/* If the configuration file doesn't specify the cpu, the subtarget may 83 override it. If it doesn't, then default to an ARM6. */ 84#if TARGET_CPU_DEFAULT == TARGET_CPU_generic 85#undef TARGET_CPU_DEFAULT 86#ifdef SUBTARGET_CPU_DEFAULT 87#define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT 88#else 89#define TARGET_CPU_DEFAULT TARGET_CPU_arm6 90#endif 91#endif 92 93#if TARGET_CPU_DEFAULT == TARGET_CPU_arm2 94#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__" 95#else 96#if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe 97#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__" 98#else 99#if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m 100#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__" 101#else 102#if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 103#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__" 104#else 105#if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm 106#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__" 107#else 108Unrecognized value in TARGET_CPU_DEFAULT. 109#endif 110#endif 111#endif 112#endif 113#endif 114 115#ifndef CPP_PREDEFINES 116#define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)" 117#endif 118 119#define CPP_SPEC "\ 120%(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \ 121%(cpp_endian) %(subtarget_cpp_spec)" 122 123/* Set the architecture define -- if -march= is set, then it overrides 124 the -mcpu= setting. */ 125#define CPP_CPU_ARCH_SPEC "\ 126%{march=arm2:-D__ARM_ARCH_2__} \ 127%{march=arm250:-D__ARM_ARCH_2__} \ 128%{march=arm3:-D__ARM_ARCH_2__} \ 129%{march=arm6:-D__ARM_ARCH_3__} \ 130%{march=arm600:-D__ARM_ARCH_3__} \ 131%{march=arm610:-D__ARM_ARCH_3__} \ 132%{march=arm7:-D__ARM_ARCH_3__} \ 133%{march=arm700:-D__ARM_ARCH_3__} \ 134%{march=arm710:-D__ARM_ARCH_3__} \ 135%{march=arm7100:-D__ARM_ARCH_3__} \ 136%{march=arm7500:-D__ARM_ARCH_3__} \ 137%{march=arm7500fe:-D__ARM_ARCH_3__} \ 138%{march=arm7m:-D__ARM_ARCH_3M__} \ 139%{march=arm7dm:-D__ARM_ARCH_3M__} \ 140%{march=arm7dmi:-D__ARM_ARCH_3M__} \ 141%{march=arm7tdmi:-D__ARM_ARCH_4T__} \ 142%{march=arm8:-D__ARM_ARCH_4__} \ 143%{march=arm810:-D__ARM_ARCH_4__} \ 144%{march=arm9:-D__ARM_ARCH_4T__} \ 145%{march=arm9tdmi:-D__ARM_ARCH_4T__} \ 146%{march=strongarm:-D__ARM_ARCH_4__} \ 147%{march=strongarm110:-D__ARM_ARCH_4__} \ 148%{march=strongarm1100:-D__ARM_ARCH_4__} \ 149%{march=armv2:-D__ARM_ARCH_2__} \ 150%{march=armv2a:-D__ARM_ARCH_2__} \ 151%{march=armv3:-D__ARM_ARCH_3__} \ 152%{march=armv3m:-D__ARM_ARCH_3M__} \ 153%{march=armv4:-D__ARM_ARCH_4__} \ 154%{march=armv4t:-D__ARM_ARCH_4T__} \ 155%{!march=*: \ 156 %{mcpu=arm2:-D__ARM_ARCH_2__} \ 157 %{mcpu=arm250:-D__ARM_ARCH_2__} \ 158 %{mcpu=arm3:-D__ARM_ARCH_2__} \ 159 %{mcpu=arm6:-D__ARM_ARCH_3__} \ 160 %{mcpu=arm600:-D__ARM_ARCH_3__} \ 161 %{mcpu=arm610:-D__ARM_ARCH_3__} \ 162 %{mcpu=arm7:-D__ARM_ARCH_3__} \ 163 %{mcpu=arm700:-D__ARM_ARCH_3__} \ 164 %{mcpu=arm710:-D__ARM_ARCH_3__} \ 165 %{mcpu=arm7100:-D__ARM_ARCH_3__} \ 166 %{mcpu=arm7500:-D__ARM_ARCH_3__} \ 167 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \ 168 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \ 169 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \ 170 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \ 171 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \ 172 %{mcpu=arm8:-D__ARM_ARCH_4__} \ 173 %{mcpu=arm810:-D__ARM_ARCH_4__} \ 174 %{mcpu=arm9:-D__ARM_ARCH_4T__} \ 175 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \ 176 %{mcpu=strongarm:-D__ARM_ARCH_4__} \ 177 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \ 178 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \ 179 %{!mcpu*:%(cpp_cpu_arch_default)}} \ 180" 181 182/* Define __APCS_26__ if the PC also contains the PSR */ 183#define CPP_APCS_PC_SPEC "\ 184%{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \ 185 -D__APCS_32__} \ 186%{mapcs-26:-D__APCS_26__} \ 187%{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \ 188" 189 190#ifndef CPP_APCS_PC_DEFAULT_SPEC 191#define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__" 192#endif 193 194#define CPP_FLOAT_SPEC "\ 195%{msoft-float:\ 196 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \ 197 -D__SOFTFP__} \ 198%{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \ 199" 200 201/* Default is hard float, which doesn't define anything */ 202#define CPP_FLOAT_DEFAULT_SPEC "" 203 204#define CPP_ENDIAN_SPEC "\ 205%{mbig-endian: \ 206 %{mlittle-endian: \ 207 %e-mbig-endian and -mlittle-endian may not be used together} \ 208 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \ 209%{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \ 210" 211 212/* Default is little endian, which doesn't define anything. */ 213#define CPP_ENDIAN_DEFAULT_SPEC "" 214 215#define CC1_SPEC "" 216 217/* This macro defines names of additional specifications to put in the specs 218 that can be used in various specifications like CC1_SPEC. Its definition 219 is an initializer with a subgrouping for each command option. 220 221 Each subgrouping contains a string constant, that defines the 222 specification name, and a string constant that used by the GNU CC driver 223 program. 224 225 Do not define this macro if it does not need to do anything. */ 226#define EXTRA_SPECS \ 227 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \ 228 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \ 229 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \ 230 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \ 231 { "cpp_float", CPP_FLOAT_SPEC }, \ 232 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \ 233 { "cpp_endian", CPP_ENDIAN_SPEC }, \ 234 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \ 235 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 236 SUBTARGET_EXTRA_SPECS 237 238#define SUBTARGET_EXTRA_SPECS 239#define SUBTARGET_CPP_SPEC "" 240 241 242/* Run-time Target Specification. */ 243#ifndef TARGET_VERSION 244#define TARGET_VERSION \ 245 fputs (" (ARM/generic)", stderr); 246#endif 247 248/* Run-time compilation parameters selecting different hardware subsets. */ 249extern int target_flags; 250 251/* The floating point instruction architecture, can be 2 or 3 */ 252extern const char * target_fp_name; 253 254/* Nonzero if the function prologue (and epilogue) should obey 255 the ARM Procedure Call Standard. */ 256#define ARM_FLAG_APCS_FRAME (0x0001) 257 258/* Nonzero if the function prologue should output the function name to enable 259 the post mortem debugger to print a backtrace (very useful on RISCOS, 260 unused on RISCiX). Specifying this flag also enables 261 -fno-omit-frame-pointer. 262 XXX Must still be implemented in the prologue. */ 263#define ARM_FLAG_POKE (0x0002) 264 265/* Nonzero if floating point instructions are emulated by the FPE, in which 266 case instruction scheduling becomes very uninteresting. */ 267#define ARM_FLAG_FPE (0x0004) 268 269/* Nonzero if destined for a processor in 32-bit program mode. Takes out bit 270 that assume restoration of the condition flags when returning from a 271 branch and link (ie a function). */ 272#define ARM_FLAG_APCS_32 (0x0020) 273 274/* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */ 275 276/* Nonzero if stack checking should be performed on entry to each function 277 which allocates temporary variables on the stack. */ 278#define ARM_FLAG_APCS_STACK (0x0040) 279 280/* Nonzero if floating point parameters should be passed to functions in 281 floating point registers. */ 282#define ARM_FLAG_APCS_FLOAT (0x0080) 283 284/* Nonzero if re-entrant, position independent code should be generated. 285 This is equivalent to -fpic. */ 286#define ARM_FLAG_APCS_REENT (0x0100) 287 288/* Nonzero if the MMU will trap unaligned word accesses, so shorts must be 289 loaded byte-at-a-time. */ 290#define ARM_FLAG_SHORT_BYTE (0x0200) 291 292/* Nonzero if all floating point instructions are missing (and there is no 293 emulator either). Generate function calls for all ops in this case. */ 294#define ARM_FLAG_SOFT_FLOAT (0x0400) 295 296/* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */ 297#define ARM_FLAG_BIG_END (0x0800) 298 299/* Nonzero if we should compile for Thumb interworking. */ 300#define ARM_FLAG_THUMB (0x1000) 301 302/* Nonzero if we should have little-endian words even when compiling for 303 big-endian (for backwards compatibility with older versions of GCC). */ 304#define ARM_FLAG_LITTLE_WORDS (0x2000) 305 306/* Nonzero if we need to protect the prolog from scheduling */ 307#define ARM_FLAG_NO_SCHED_PRO (0x4000) 308 309/* Nonzero if a call to abort should be generated if a noreturn 310function tries to return. */ 311#define ARM_FLAG_ABORT_NORETURN (0x8000) 312 313#define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME) 314#define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) 315#define TARGET_FPE (target_flags & ARM_FLAG_FPE) 316#define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32) 317#define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK) 318#define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT) 319#define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT) 320/* Note: TARGET_SHORT_BY_BYTES is really a misnomer. What it means is 321 that short values sould not be accessed using word load instructions 322 as there is a possibility that they may not be word aligned and this 323 would generate an MMU fault. On processors which do not have a 16 bit 324 load instruction therefore, short values must be loaded by individual 325 byte accesses rather than loading a word and then shifting the desired 326 value into place. */ 327#define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE) 328#define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT) 329#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) 330#define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END) 331#define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB) 332#define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS) 333#define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO) 334#define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN) 335 336/* SUBTARGET_SWITCHES is used to add flags on a per-config basis. 337 Bit 31 is reserved. See riscix.h. */ 338#ifndef SUBTARGET_SWITCHES 339#define SUBTARGET_SWITCHES 340#endif 341 342#define TARGET_SWITCHES \ 343{ \ 344 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \ 345 {"apcs-frame", ARM_FLAG_APCS_FRAME, \ 346 "Generate APCS conformant stack frames" }, \ 347 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \ 348 {"poke-function-name", ARM_FLAG_POKE, \ 349 "Store function names in object code" }, \ 350 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \ 351 {"fpe", ARM_FLAG_FPE, "" }, \ 352 {"apcs-32", ARM_FLAG_APCS_32, \ 353 "Use the 32bit version of the APCS" }, \ 354 {"apcs-26", -ARM_FLAG_APCS_32, \ 355 "Use the 26bit version of the APCS" }, \ 356 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \ 357 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \ 358 {"apcs-float", ARM_FLAG_APCS_FLOAT, \ 359 "Pass FP arguments in FP registers" }, \ 360 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \ 361 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \ 362 "Generate re-entrant, PIC code" }, \ 363 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \ 364 {"short-load-bytes", ARM_FLAG_SHORT_BYTE, \ 365 "Load shorts a byte at a time" }, \ 366 {"no-short-load-bytes", -ARM_FLAG_SHORT_BYTE, "" }, \ 367 {"short-load-words", -ARM_FLAG_SHORT_BYTE, \ 368 "Load words a byte at a time" }, \ 369 {"no-short-load-words", ARM_FLAG_SHORT_BYTE, "" }, \ 370 {"soft-float", ARM_FLAG_SOFT_FLOAT, \ 371 "Use library calls to perform FP operations" }, \ 372 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \ 373 "Use hardware floating point instructions" }, \ 374 {"big-endian", ARM_FLAG_BIG_END, \ 375 "Assume target CPU is configured as big endian" }, \ 376 {"little-endian", -ARM_FLAG_BIG_END, \ 377 "Assume target CPU is configured as little endian" }, \ 378 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \ 379 "Assume big endian bytes, little endian words" }, \ 380 {"thumb-interwork", ARM_FLAG_THUMB, \ 381 "Support calls between THUMB and ARM instructions sets" }, \ 382 {"no-thumb-interwork", -ARM_FLAG_THUMB, "" }, \ 383 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \ 384 "Generate a call to abort if a noreturn function returns"}, \ 385 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, ""}, \ 386 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \ 387 "Do not move instructions into a function's prologue" }, \ 388 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \ 389 SUBTARGET_SWITCHES \ 390 {"", TARGET_DEFAULT } \ 391} 392 393#define TARGET_OPTIONS \ 394{ \ 395 {"cpu=", & arm_select[0].string, \ 396 "Specify the name of the target CPU" }, \ 397 {"arch=", & arm_select[1].string, \ 398 "Specify the name of the target architecture" }, \ 399 {"tune=", & arm_select[2].string, "" }, \ 400 {"fpe=", & target_fp_name, "" }, \ 401 {"fp=", & target_fp_name, \ 402 "Specify the version of the floating point emulator" }, \ 403 { "structure-size-boundary=", & structure_size_string, \ 404 "Specify the minumum bit alignment of structures" } \ 405} 406 407struct arm_cpu_select 408{ 409 const char * string; 410 const char * name; 411 const struct processors * processors; 412}; 413 414/* This is a magic array. If the user specifies a command line switch 415 which matches one of the entries in TARGET_OPTIONS then the corresponding 416 string pointer will be set to the value specified by the user. */ 417extern struct arm_cpu_select arm_select[]; 418 419enum prog_mode_type 420{ 421 prog_mode26, 422 prog_mode32 423}; 424 425/* Recast the program mode class to be the prog_mode attribute */ 426#define arm_prog_mode ((enum attr_prog_mode) arm_prgmode) 427 428extern enum prog_mode_type arm_prgmode; 429 430/* What sort of floating point unit do we have? Hardware or software. 431 If software, is it issue 2 or issue 3? */ 432enum floating_point_type 433{ 434 FP_HARD, 435 FP_SOFT2, 436 FP_SOFT3 437}; 438 439/* Recast the floating point class to be the floating point attribute. */ 440#define arm_fpu_attr ((enum attr_fpu) arm_fpu) 441 442/* What type of floating point to tune for */ 443extern enum floating_point_type arm_fpu; 444 445/* What type of floating point instructions are available */ 446extern enum floating_point_type arm_fpu_arch; 447 448/* Default floating point architecture. Override in sub-target if 449 necessary. */ 450#define FP_DEFAULT FP_SOFT2 451 452/* Nonzero if the processor has a fast multiply insn, and one that does 453 a 64-bit multiply of two 32-bit values. */ 454extern int arm_fast_multiply; 455 456/* Nonzero if this chip supports the ARM Architecture 4 extensions */ 457extern int arm_arch4; 458 459/* Nonzero if this chip can benefit from load scheduling. */ 460extern int arm_ld_sched; 461 462/* Nonzero if this chip is a StrongARM. */ 463extern int arm_is_strong; 464 465/* Nonzero if this chip is a an ARM6 or an ARM7. */ 466extern int arm_is_6_or_7; 467 468#ifndef TARGET_DEFAULT 469#define TARGET_DEFAULT 0 470#endif 471 472/* The frame pointer register used in gcc has nothing to do with debugging; 473 that is controlled by the APCS-FRAME option. */ 474/* Not fully implemented yet */ 475/* #define CAN_DEBUG_WITHOUT_FP 1 */ 476 477#define TARGET_MEM_FUNCTIONS 1 478 479#define OVERRIDE_OPTIONS arm_override_options () 480 481/* Nonzero if PIC code requires explicit qualifiers to generate 482 PLT and GOT relocs rather than the assembler doing so implicitly. 483 Subtargets can override this if required. */ 484#ifndef NEED_PLT_GOT 485#define NEED_PLT_GOT 0 486#endif 487 488/* Nonzero if we need to refer to the GOT with a PC-relative 489 offset. In other words, generate 490 491 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 492 493 rather than 494 495 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 496 497 The default is true, which matches NetBSD. Subtargets can 498 override this if required. */ 499#ifndef GOT_PCREL 500#define GOT_PCREL 1 501#endif 502 503 504/* Target machine storage Layout. */ 505 506 507/* Define this macro if it is advisable to hold scalars in registers 508 in a wider mode than that declared by the program. In such cases, 509 the value is constrained to be within the bounds of the declared 510 type, but kept valid in the wider mode. The signedness of the 511 extension may differ from that of the type. */ 512 513/* It is far faster to zero extend chars than to sign extend them */ 514 515#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 516 if (GET_MODE_CLASS (MODE) == MODE_INT \ 517 && GET_MODE_SIZE (MODE) < 4) \ 518 { \ 519 if (MODE == QImode) \ 520 UNSIGNEDP = 1; \ 521 else if (MODE == HImode) \ 522 UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \ 523 (MODE) = SImode; \ 524 } 525 526/* Define this macro if the promotion described by `PROMOTE_MODE' 527 should also be done for outgoing function arguments. */ 528/* This is required to ensure that push insns always push a word. */ 529#define PROMOTE_FUNCTION_ARGS 530 531/* Define for XFmode extended real floating point support. 532 This will automatically cause REAL_ARITHMETIC to be defined. */ 533/* For the ARM: 534 I think I have added all the code to make this work. Unfortunately, 535 early releases of the floating point emulation code on RISCiX used a 536 different format for extended precision numbers. On my RISCiX box there 537 is a bug somewhere which causes the machine to lock up when running enquire 538 with long doubles. There is the additional aspect that Norcroft C 539 treats long doubles as doubles and we ought to remain compatible. 540 Perhaps someone with an FPA coprocessor and not running RISCiX would like 541 to try this someday. */ 542/* #define LONG_DOUBLE_TYPE_SIZE 96 */ 543 544/* Disable XFmode patterns in md file */ 545#define ENABLE_XF_PATTERNS 0 546 547/* Define if you don't want extended real, but do want to use the 548 software floating point emulator for REAL_ARITHMETIC and 549 decimal <-> binary conversion. */ 550/* See comment above */ 551#define REAL_ARITHMETIC 552 553/* Define this if most significant bit is lowest numbered 554 in instructions that operate on numbered bit-fields. */ 555#define BITS_BIG_ENDIAN 0 556 557/* Define this if most significant byte of a word is the lowest numbered. 558 Most ARM processors are run in little endian mode, so that is the default. 559 If you want to have it run-time selectable, change the definition in a 560 cover file to be TARGET_BIG_ENDIAN. */ 561#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 562 563/* Define this if most significant word of a multiword number is the lowest 564 numbered. 565 This is always false, even when in big-endian mode. */ 566#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) 567 568/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based 569 on processor pre-defineds when compiling libgcc2.c. */ 570#if defined(__ARMEB__) && !defined(__ARMWEL__) 571#define LIBGCC2_WORDS_BIG_ENDIAN 1 572#else 573#define LIBGCC2_WORDS_BIG_ENDIAN 0 574#endif 575 576/* Define this if most significant word of doubles is the lowest numbered. 577 This is always true, even when in little-endian mode. */ 578#define FLOAT_WORDS_BIG_ENDIAN 1 579 580/* Number of bits in an addressable storage unit */ 581#define BITS_PER_UNIT 8 582 583#define BITS_PER_WORD 32 584 585#define UNITS_PER_WORD 4 586 587#define POINTER_SIZE 32 588 589#define PARM_BOUNDARY 32 590 591#define STACK_BOUNDARY 32 592 593#define FUNCTION_BOUNDARY 32 594 595#define EMPTY_FIELD_BOUNDARY 32 596 597#define BIGGEST_ALIGNMENT 32 598 599/* Make strings word-aligned so strcpy from constants will be faster. */ 600#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 601 (TREE_CODE (EXP) == STRING_CST \ 602 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 603 604/* Every structures size must be a multiple of 32 bits. */ 605/* This is for compatibility with ARMCC. ARM SDT Reference Manual 606 (ARM DUI 0020D) page 2-20 says "Structures are aligned on word 607 boundaries". */ 608#ifndef STRUCTURE_SIZE_BOUNDARY 609#define STRUCTURE_SIZE_BOUNDARY 32 610#endif 611 612/* Used when parsing command line option -mstructure_size_boundary. */ 613extern const char * structure_size_string; 614 615/* Non-zero if move instructions will actually fail to work 616 when given unaligned data. */ 617#define STRICT_ALIGNMENT 1 618 619#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT 620 621 622/* Standard register usage. */ 623 624/* Register allocation in ARM Procedure Call Standard (as used on RISCiX): 625 (S - saved over call). 626 627 r0 * argument word/integer result 628 r1-r3 argument word 629 630 r4-r8 S register variable 631 r9 S (rfp) register variable (real frame pointer) 632 633 r10 F S (sl) stack limit (used by -mapcs-stack-check) 634 r11 F S (fp) argument pointer 635 r12 (ip) temp workspace 636 r13 F S (sp) lower end of current stack frame 637 r14 (lr) link address/workspace 638 r15 F (pc) program counter 639 640 f0 floating point result 641 f1-f3 floating point scratch 642 643 f4-f7 S floating point variable 644 645 cc This is NOT a real register, but is used internally 646 to represent things that use or set the condition 647 codes. 648 sfp This isn't either. It is used during rtl generation 649 since the offset between the frame pointer and the 650 auto's isn't known until after register allocation. 651 afp Nor this, we only need this because of non-local 652 goto. Without it fp appears to be used and the 653 elimination code won't get rid of sfp. It tracks 654 fp exactly at all times. 655 656 *: See CONDITIONAL_REGISTER_USAGE */ 657 658/* The stack backtrace structure is as follows: 659 fp points to here: | save code pointer | [fp] 660 | return link value | [fp, #-4] 661 | return sp value | [fp, #-8] 662 | return fp value | [fp, #-12] 663 [| saved r10 value |] 664 [| saved r9 value |] 665 [| saved r8 value |] 666 [| saved r7 value |] 667 [| saved r6 value |] 668 [| saved r5 value |] 669 [| saved r4 value |] 670 [| saved r3 value |] 671 [| saved r2 value |] 672 [| saved r1 value |] 673 [| saved r0 value |] 674 [| saved f7 value |] three words 675 [| saved f6 value |] three words 676 [| saved f5 value |] three words 677 [| saved f4 value |] three words 678 r0-r3 are not normally saved in a C function. */ 679 680/* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */ 681#define FIRST_PSEUDO_REGISTER 27 682 683/* 1 for registers that have pervasive standard uses 684 and are not available for the register allocator. */ 685#define FIXED_REGISTERS \ 686{ \ 687 0,0,0,0,0,0,0,0, \ 688 0,0,0,1,0,1,0,1, \ 689 0,0,0,0,0,0,0,0, \ 690 1,1,1 \ 691} 692 693/* 1 for registers not available across function calls. 694 These must include the FIXED_REGISTERS and also any 695 registers that can be used without being saved. 696 The latter must include the registers where values are returned 697 and the register where structure-value addresses are passed. 698 Aside from that, you can include as many other registers as you like. 699 The CC is not preserved over function calls on the ARM 6, so it is 700 easier to assume this for all. SFP is preserved, since FP is. */ 701#define CALL_USED_REGISTERS \ 702{ \ 703 1,1,1,1,0,0,0,0, \ 704 0,0,0,1,1,1,1,1, \ 705 1,1,1,1,0,0,0,0, \ 706 1,1,1 \ 707} 708 709#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 710#define SUBTARGET_CONDITIONAL_REGISTER_USAGE 711#endif 712 713/* If doing stupid life analysis, avoid a bug causing a return value r0 to be 714 trampled. This effectively reduces the number of available registers by 1. 715 XXX It is a hack, I know. 716 XXX Is this still needed? */ 717#define CONDITIONAL_REGISTER_USAGE \ 718{ \ 719 if (obey_regdecls) \ 720 fixed_regs[0] = 1; \ 721 if (TARGET_SOFT_FLOAT) \ 722 { \ 723 int regno; \ 724 for (regno = 16; regno < 24; ++regno) \ 725 fixed_regs[regno] = call_used_regs[regno] = 1; \ 726 } \ 727 if (flag_pic) \ 728 { \ 729 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 730 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 731 } \ 732 else if (TARGET_APCS_STACK) \ 733 { \ 734 fixed_regs[10] = 1; \ 735 call_used_regs[10] = 1; \ 736 } \ 737 SUBTARGET_CONDITIONAL_REGISTER_USAGE \ 738} 739 740/* Return number of consecutive hard regs needed starting at reg REGNO 741 to hold something of mode MODE. 742 This is ordinarily the length in words of a value of mode MODE 743 but can be less for certain modes in special long registers. 744 745 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP 746 mode. */ 747#define HARD_REGNO_NREGS(REGNO, MODE) \ 748 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \ 749 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \ 750 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 751 752/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 753 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU 754 regs holding FP. */ 755#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 756 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \ 757 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \ 758 || REGNO == ARG_POINTER_REGNUM \ 759 || GET_MODE_CLASS (MODE) == MODE_FLOAT)) 760 761/* Value is 1 if it is a good idea to tie two pseudo registers 762 when one has mode MODE1 and one has mode MODE2. 763 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 764 for any hard reg, then this must be 0 for correct output. */ 765#define MODES_TIEABLE_P(MODE1, MODE2) \ 766 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 767 768/* Specify the registers used for certain standard purposes. 769 The values of these macros are register numbers. */ 770 771/* Define this if the program counter is overloaded on a register. */ 772#define PC_REGNUM 15 773 774/* Register to use for pushing function arguments. */ 775#define STACK_POINTER_REGNUM 13 776 777/* Base register for access to local variables of the function. */ 778#define FRAME_POINTER_REGNUM 25 779 780/* Define this to be where the real frame pointer is if it is not possible to 781 work out the offset between the frame pointer and the automatic variables 782 until after register allocation has taken place. FRAME_POINTER_REGNUM 783 should point to a special register that we will make sure is eliminated. */ 784#define HARD_FRAME_POINTER_REGNUM 11 785 786/* Value should be nonzero if functions must have frame pointers. 787 Zero means the frame pointer need not be set up (and parms may be accessed 788 via the stack pointer) in functions that seem suitable. 789 If we have to have a frame pointer we might as well make use of it. 790 APCS says that the frame pointer does not need to be pushed in leaf 791 functions, or simple tail call functions. */ 792#define FRAME_POINTER_REQUIRED \ 793 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ())) 794 795/* Base register for access to arguments of the function. */ 796#define ARG_POINTER_REGNUM 26 797 798/* The native (Norcroft) Pascal compiler for the ARM passes the static chain 799 as an invisible last argument (possible since varargs don't exist in 800 Pascal), so the following is not true. */ 801#define STATIC_CHAIN_REGNUM 8 802 803/* Register in which address to store a structure value 804 is passed to a function. */ 805#define STRUCT_VALUE_REGNUM 0 806 807/* Internal, so that we don't need to refer to a raw number */ 808#define CC_REGNUM 24 809 810/* The order in which register should be allocated. It is good to use ip 811 since no saving is required (though calls clobber it) and it never contains 812 function parameters. It is quite good to use lr since other calls may 813 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 814 least likely to contain a function parameter; in addition results are 815 returned in r0. 816 */ 817#define REG_ALLOC_ORDER \ 818{ \ 819 3, 2, 1, 0, 12, 14, 4, 5, \ 820 6, 7, 8, 10, 9, 11, 13, 15, \ 821 16, 17, 18, 19, 20, 21, 22, 23, \ 822 24, 25, 26 \ 823} 824 825/* Register and constant classes. */ 826 827/* Register classes: all ARM regs or all FPU regs---simple! */ 828enum reg_class 829{ 830 NO_REGS, 831 FPU_REGS, 832 GENERAL_REGS, 833 ALL_REGS, 834 LIM_REG_CLASSES 835}; 836 837#define N_REG_CLASSES (int) LIM_REG_CLASSES 838 839/* Give names of register classes as strings for dump file. */ 840#define REG_CLASS_NAMES \ 841{ \ 842 "NO_REGS", \ 843 "FPU_REGS", \ 844 "GENERAL_REGS", \ 845 "ALL_REGS", \ 846} 847 848/* Define which registers fit in which classes. 849 This is an initializer for a vector of HARD_REG_SET 850 of length N_REG_CLASSES. */ 851#define REG_CLASS_CONTENTS \ 852{ \ 853 { 0x0000000 }, /* NO_REGS */ \ 854 { 0x0FF0000 }, /* FPU_REGS */ \ 855 { 0x200FFFF }, /* GENERAL_REGS */ \ 856 { 0x2FFFFFF } /* ALL_REGS */ \ 857} 858 859/* The same information, inverted: 860 Return the class number of the smallest class containing 861 reg number REGNO. This could be a conditional expression 862 or could index an array. */ 863#define REGNO_REG_CLASS(REGNO) \ 864 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \ 865 || REGNO == ARG_POINTER_REGNUM) \ 866 ? GENERAL_REGS : (REGNO) == CC_REGNUM \ 867 ? NO_REGS : FPU_REGS) 868 869/* The class value for index registers, and the one for base regs. */ 870#define INDEX_REG_CLASS GENERAL_REGS 871#define BASE_REG_CLASS GENERAL_REGS 872 873/* Get reg_class from a letter such as appears in the machine description. 874 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */ 875#define REG_CLASS_FROM_LETTER(C) \ 876 ((C)=='f' ? FPU_REGS : NO_REGS) 877 878/* The letters I, J, K, L and M in a register constraint string 879 can be used to stand for particular ranges of immediate operands. 880 This macro defines what the ranges are. 881 C is the letter, and VALUE is a constant value. 882 Return 1 if VALUE is in the range specified by C. 883 I: immediate arithmetic operand (i.e. 8 bits shifted as required). 884 J: valid indexing constants. 885 K: ~value ok in rhs argument of data operand. 886 L: -value ok in rhs argument of data operand. 887 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */ 888#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 889 ((C) == 'I' ? const_ok_for_arm (VALUE) : \ 890 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ 891 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \ 892 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \ 893 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \ 894 || (((VALUE) & ((VALUE) - 1)) == 0)) \ 895 : 0) 896 897/* For the ARM, `Q' means that this is a memory operand that is just 898 an offset from a register. 899 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL 900 address. This means that the symbol is in the text segment and can be 901 accessed without using a load. */ 902 903#define EXTRA_CONSTRAINT(OP, C) \ 904 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ 905 : (C) == 'R' ? (GET_CODE (OP) == MEM \ 906 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ 907 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \ 908 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \ 909 : 0) 910 911/* Constant letter 'G' for the FPU immediate constants. 912 'H' means the same constant negated. */ 913#define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \ 914 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \ 915 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0) 916 917/* Given an rtx X being reloaded into a reg required to be 918 in class CLASS, return the class of reg to actually use. 919 In general this is just CLASS; but on some machines 920 in some cases it is preferable to use a more restrictive class. */ 921#define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) 922 923/* Return the register class of a scratch register needed to copy IN into 924 or out of a register in CLASS in MODE. If it can be done directly, 925 NO_REGS is returned. */ 926#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ 927 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 928 ? GENERAL_REGS : NO_REGS) 929 930/* If we need to load shorts byte-at-a-time, then we need a scratch. */ 931#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \ 932 (((MODE) == HImode && ! arm_arch4 && TARGET_SHORT_BY_BYTES \ 933 && (GET_CODE (X) == MEM \ 934 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ 935 && true_regnum (X) == -1))) \ 936 ? GENERAL_REGS : NO_REGS) 937 938/* Try a machine-dependent way of reloading an illegitimate address 939 operand. If we find one, push the reload and jump to WIN. This 940 macro is used in only one place: `find_reloads_address' in reload.c. 941 942 For the ARM, we wish to handle large displacements off a base 943 register by splitting the addend across a MOV and the mem insn. 944 This can cut the number of reloads needed. */ 945#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 946do { \ 947 if (GET_CODE (X) == PLUS \ 948 && GET_CODE (XEXP (X, 0)) == REG \ 949 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ 950 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ 951 && GET_CODE (XEXP (X, 1)) == CONST_INT) \ 952 { \ 953 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ 954 HOST_WIDE_INT low, high; \ 955 \ 956 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ 957 low = ((val & 0xf) ^ 0x8) - 0x8; \ 958 else if (MODE == SImode || MODE == QImode \ 959 || (MODE == SFmode && TARGET_SOFT_FLOAT) \ 960 || (MODE == HImode && ! arm_arch4)) \ 961 /* Need to be careful, -4096 is not a valid offset */ \ 962 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ 963 else if (MODE == HImode && arm_arch4) \ 964 /* Need to be careful, -256 is not a valid offset */ \ 965 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ 966 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 967 && TARGET_HARD_FLOAT) \ 968 /* Need to be careful, -1024 is not a valid offset */ \ 969 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ 970 else \ 971 break; \ 972 \ 973 high = ((((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000); \ 974 /* Check for overflow or zero */ \ 975 if (low == 0 || high == 0 || (high + low != val)) \ 976 break; \ 977 \ 978 /* Reload the high part into a base reg; leave the low part \ 979 in the mem. */ \ 980 X = gen_rtx_PLUS (GET_MODE (X), \ 981 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ 982 GEN_INT (high)), \ 983 GEN_INT (low)); \ 984 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \ 985 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ 986 OPNUM, TYPE); \ 987 goto WIN; \ 988 } \ 989} while (0) 990 991/* Return the maximum number of consecutive registers 992 needed to represent mode MODE in a register of class CLASS. 993 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */ 994#define CLASS_MAX_NREGS(CLASS, MODE) \ 995 ((CLASS) == FPU_REGS ? 1 \ 996 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 997 998/* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */ 999#define REGISTER_MOVE_COST(CLASS1, CLASS2) \ 1000 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \ 1001 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \ 1002 ? 20 : 2) 1003 1004/* Stack layout; function entry, exit and calling. */ 1005 1006/* Define this if pushing a word on the stack 1007 makes the stack pointer a smaller address. */ 1008#define STACK_GROWS_DOWNWARD 1 1009 1010/* Define this if the nominal address of the stack frame 1011 is at the high-address end of the local variables; 1012 that is, each additional local variable allocated 1013 goes at a more negative offset in the frame. */ 1014#define FRAME_GROWS_DOWNWARD 1 1015 1016/* Offset within stack frame to start allocating local variables at. 1017 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1018 first local allocated. Otherwise, it is the offset to the BEGINNING 1019 of the first local allocated. */ 1020#define STARTING_FRAME_OFFSET 0 1021 1022/* If we generate an insn to push BYTES bytes, 1023 this says how many the stack pointer really advances by. */ 1024/* The push insns do not do this rounding implicitly. So don't define this. */ 1025/* #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) */ 1026 1027/* Define this if the maximum size of all the outgoing args is to be 1028 accumulated and pushed during the prologue. The amount can be 1029 found in the variable current_function_outgoing_args_size. */ 1030#define ACCUMULATE_OUTGOING_ARGS 1031 1032/* Offset of first parameter from the argument pointer register value. */ 1033#define FIRST_PARM_OFFSET(FNDECL) 4 1034 1035/* Value is the number of byte of arguments automatically 1036 popped when returning from a subroutine call. 1037 FUNDECL is the declaration node of the function (as a tree), 1038 FUNTYPE is the data type of the function (as a tree), 1039 or for a library call it is an identifier node for the subroutine name. 1040 SIZE is the number of bytes of arguments passed on the stack. 1041 1042 On the ARM, the caller does not pop any of its arguments that were passed 1043 on the stack. */ 1044#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1045 1046/* Define how to find the value returned by a function. 1047 VALTYPE is the data type of the value (as a tree). 1048 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1049 otherwise, FUNC is 0. */ 1050#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1051 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT && TARGET_HARD_FLOAT \ 1052 ? gen_rtx_REG (TYPE_MODE (VALTYPE), 16) \ 1053 : gen_rtx_REG (TYPE_MODE (VALTYPE), 0)) 1054 1055/* Define how to find the value returned by a library function 1056 assuming the value has mode MODE. */ 1057#define LIBCALL_VALUE(MODE) \ 1058 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \ 1059 ? gen_rtx_REG (MODE, 16) \ 1060 : gen_rtx_REG (MODE, 0)) 1061 1062/* 1 if N is a possible register number for a function value. 1063 On the ARM, only r0 and f0 can return results. */ 1064#define FUNCTION_VALUE_REGNO_P(REGNO) \ 1065 ((REGNO) == 0 || (((REGNO) == 16) && TARGET_HARD_FLOAT)) 1066 1067/* How large values are returned */ 1068/* A C expression which can inhibit the returning of certain function values 1069 in registers, based on the type of value. */ 1070#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE) 1071 1072/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1073 values must be in memory. On the ARM, they need only do so if larger 1074 than a word, or if they contain elements offset from zero in the struct. */ 1075#define DEFAULT_PCC_STRUCT_RETURN 0 1076 1077/* Define where to put the arguments to a function. 1078 Value is zero to push the argument on the stack, 1079 or a hard register in which to store the argument. 1080 1081 MODE is the argument's machine mode. 1082 TYPE is the data type of the argument (as a tree). 1083 This is null for libcalls where that information may 1084 not be available. 1085 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1086 the preceding args and about the function being called. 1087 NAMED is nonzero if this argument is a named parameter 1088 (otherwise it is an extra parameter matching an ellipsis). 1089 1090 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all 1091 other arguments are passed on the stack. If (NAMED == 0) (which happens 1092 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is 1093 passed in the stack (function_prologue will indeed make it pass in the 1094 stack if necessary). */ 1095#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1096 ((NAMED) \ 1097 ? ((CUM) >= 16 ? 0 : gen_rtx_REG (MODE, (CUM) / 4)) \ 1098 : 0) 1099 1100/* For an arg passed partly in registers and partly in memory, 1101 this is the number of registers used. 1102 For args passed entirely in registers or entirely in memory, zero. */ 1103#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1104 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \ 1105 ? GET_MODE_SIZE (MODE) \ 1106 : int_size_in_bytes (TYPE)) \ 1107 ? 4 - (CUM) / 4 : 0) 1108 1109/* A C type for declaring a variable that is used as the first argument of 1110 `FUNCTION_ARG' and other related values. For some target machines, the 1111 type `int' suffices and can hold the number of bytes of argument so far. 1112 1113 On the ARM, this is the number of bytes of arguments scanned so far. */ 1114#define CUMULATIVE_ARGS int 1115 1116/* Initialize a variable CUM of type CUMULATIVE_ARGS 1117 for a call to a function whose data type is FNTYPE. 1118 For a library call, FNTYPE is 0. 1119 On the ARM, the offset starts at 0. */ 1120#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ 1121 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0)) 1122 1123/* Update the data in CUM to advance over an argument 1124 of mode MODE and data type TYPE. 1125 (TYPE is null for libcalls where that information may not be available.) */ 1126#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1127 (CUM) += ((MODE) != BLKmode \ 1128 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ 1129 : (int_size_in_bytes (TYPE) + 3) & ~3) \ 1130 1131/* 1 if N is a possible register number for function argument passing. 1132 On the ARM, r0-r3 are used to pass args. */ 1133#define FUNCTION_ARG_REGNO_P(REGNO) \ 1134 ((REGNO) >= 0 && (REGNO) <= 3) 1135 1136/* Perform any actions needed for a function that is receiving a variable 1137 number of arguments. CUM is as above. MODE and TYPE are the mode and type 1138 of the current parameter. PRETEND_SIZE is a variable that should be set to 1139 the amount of stack that must be pushed by the prolog to pretend that our 1140 caller pushed it. 1141 1142 Normally, this macro will push all remaining incoming registers on the 1143 stack and set PRETEND_SIZE to the length of the registers pushed. 1144 1145 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last 1146 named arg and all anonymous args onto the stack. 1147 XXX I know the prologue shouldn't be pushing registers, but it is faster 1148 that way. */ 1149#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 1150{ \ 1151 extern int current_function_anonymous_args; \ 1152 current_function_anonymous_args = 1; \ 1153 if ((CUM) < 16) \ 1154 (PRETEND_SIZE) = 16 - (CUM); \ 1155} 1156 1157/* Generate assembly output for the start of a function. */ 1158#define FUNCTION_PROLOGUE(STREAM, SIZE) \ 1159 output_func_prologue ((STREAM), (SIZE)) 1160 1161/* If your target environment doesn't prefix user functions with an 1162 underscore, you may wish to re-define this to prevent any conflicts. 1163 e.g. AOF may prefix mcount with an underscore. */ 1164#ifndef ARM_MCOUNT_NAME 1165#define ARM_MCOUNT_NAME "*mcount" 1166#endif 1167 1168/* Call the function profiler with a given profile label. The Acorn 1169 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1170 On the ARM the full profile code will look like: 1171 .data 1172 LP1 1173 .word 0 1174 .text 1175 mov ip, lr 1176 bl mcount 1177 .word LP1 1178 1179 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1180 will output the .text section. 1181 1182 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1183 ``prof'' doesn't seem to mind about this! */ 1184#define FUNCTION_PROFILER(STREAM,LABELNO) \ 1185{ \ 1186 char temp[20]; \ 1187 rtx sym; \ 1188 \ 1189 fprintf ((STREAM), "\tmov\t%s%s, %s%s\n\tbl\t", \ 1190 REGISTER_PREFIX, reg_names[12] /* ip */, \ 1191 REGISTER_PREFIX, reg_names[14] /* lr */); \ 1192 assemble_name ((STREAM), ARM_MCOUNT_NAME); \ 1193 fputc ('\n', (STREAM)); \ 1194 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", (LABELNO)); \ 1195 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \ 1196 ASM_OUTPUT_INT ((STREAM), sym); \ 1197} 1198 1199/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1200 the stack pointer does not matter. The value is tested only in 1201 functions that have frame pointers. 1202 No definition is equivalent to always zero. 1203 1204 On the ARM, the function epilogue recovers the stack pointer from the 1205 frame. */ 1206#define EXIT_IGNORE_STACK 1 1207 1208/* Generate the assembly code for function exit. */ 1209#define FUNCTION_EPILOGUE(STREAM, SIZE) \ 1210 output_func_epilogue ((STREAM), (SIZE)) 1211 1212/* Determine if the epilogue should be output as RTL. 1213 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1214#define USE_RETURN_INSN(ISCOND) use_return_insn (ISCOND) 1215 1216/* Definitions for register eliminations. 1217 1218 This is an array of structures. Each structure initializes one pair 1219 of eliminable registers. The "from" register number is given first, 1220 followed by "to". Eliminations of the same "from" register are listed 1221 in order of preference. 1222 1223 We have two registers that can be eliminated on the ARM. First, the 1224 arg pointer register can often be eliminated in favor of the stack 1225 pointer register. Secondly, the pseudo frame pointer register can always 1226 be eliminated; it is replaced with either the stack or the real frame 1227 pointer. */ 1228 1229#define ELIMINABLE_REGS \ 1230{{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1231 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1232 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1233 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 1234 1235/* Given FROM and TO register numbers, say whether this elimination is allowed. 1236 Frame pointer elimination is automatically handled. 1237 1238 All eliminations are permissible. Note that ARG_POINTER_REGNUM and 1239 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame 1240 pointer, we must eliminate FRAME_POINTER_REGNUM into 1241 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */ 1242#define CAN_ELIMINATE(FROM, TO) \ 1243 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1) 1244 1245/* Define the offset between two registers, one to be eliminated, and the other 1246 its replacement, at the start of a routine. */ 1247#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1248{ \ 1249 int volatile_func = arm_volatile_func (); \ 1250 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\ 1251 (OFFSET) = 0; \ 1252 else if ((FROM) == FRAME_POINTER_REGNUM \ 1253 && (TO) == STACK_POINTER_REGNUM) \ 1254 (OFFSET) = (current_function_outgoing_args_size \ 1255 + ((get_frame_size () + 3) & ~3)); \ 1256 else \ 1257 { \ 1258 int regno; \ 1259 int offset = 12; \ 1260 int saved_hard_reg = 0; \ 1261 \ 1262 if (! volatile_func) \ 1263 { \ 1264 for (regno = 0; regno <= 10; regno++) \ 1265 if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 1266 saved_hard_reg = 1, offset += 4; \ 1267 /* PIC register is a fixed reg, so call_used_regs set. */ \ 1268 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \ 1269 saved_hard_reg = 1, offset += 4; \ 1270 for (regno = 16; regno <=23; regno++) \ 1271 if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 1272 offset += 12; \ 1273 } \ 1274 if ((FROM) == FRAME_POINTER_REGNUM) \ 1275 (OFFSET) = -offset; \ 1276 else \ 1277 { \ 1278 if (! frame_pointer_needed) \ 1279 offset -= 16; \ 1280 if (! volatile_func \ 1281 && (regs_ever_live[14] || saved_hard_reg)) \ 1282 offset += 4; \ 1283 offset += current_function_outgoing_args_size; \ 1284 (OFFSET) = ((get_frame_size () + 3) & ~3) + offset; \ 1285 } \ 1286 } \ 1287} 1288 1289/* Output assembler code for a block containing the constant parts 1290 of a trampoline, leaving space for the variable parts. 1291 1292 On the ARM, (if r8 is the static chain regnum, and remembering that 1293 referencing pc adds an offset of 8) the trampoline looks like: 1294 ldr r8, [pc, #0] 1295 ldr pc, [pc] 1296 .word static chain value 1297 .word function's address 1298 ??? FIXME: When the trampoline returns, r8 will be clobbered. */ 1299#define TRAMPOLINE_TEMPLATE(FILE) \ 1300{ \ 1301 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \ 1302 REGISTER_PREFIX, reg_names[STATIC_CHAIN_REGNUM], \ 1303 REGISTER_PREFIX, reg_names[PC_REGNUM]); \ 1304 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \ 1305 REGISTER_PREFIX, reg_names[PC_REGNUM], \ 1306 REGISTER_PREFIX, reg_names[PC_REGNUM]); \ 1307 ASM_OUTPUT_INT ((FILE), const0_rtx); \ 1308 ASM_OUTPUT_INT ((FILE), const0_rtx); \ 1309} 1310 1311/* Length in units of the trampoline for entering a nested function. */ 1312#define TRAMPOLINE_SIZE 16 1313 1314/* Alignment required for a trampoline in units. */ 1315#define TRAMPOLINE_ALIGN 4 1316 1317/* Emit RTL insns to initialize the variable parts of a trampoline. 1318 FNADDR is an RTX for the address of the function's pure code. 1319 CXT is an RTX for the static chain value for the function. */ 1320#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1321{ \ 1322 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \ 1323 (CXT)); \ 1324 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \ 1325 (FNADDR)); \ 1326} 1327 1328 1329/* Addressing modes, and classification of registers for them. */ 1330 1331#define HAVE_POST_INCREMENT 1 1332#define HAVE_PRE_INCREMENT 1 1333#define HAVE_POST_DECREMENT 1 1334#define HAVE_PRE_DECREMENT 1 1335 1336/* Macros to check register numbers against specific register classes. */ 1337 1338/* These assume that REGNO is a hard or pseudo reg number. 1339 They give nonzero only if REGNO is a hard reg of the suitable class 1340 or a pseudo reg currently allocated to a suitable hard reg. 1341 Since they use reg_renumber, they are safe only once reg_renumber 1342 has been allocated, which happens in local-alloc.c. 1343 1344 On the ARM, don't allow the pc to be used. */ 1345#define REGNO_OK_FOR_BASE_P(REGNO) \ 1346 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \ 1347 || (REGNO) == ARG_POINTER_REGNUM \ 1348 || (unsigned) reg_renumber[(REGNO)] < 15 \ 1349 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \ 1350 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM) 1351#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1352 REGNO_OK_FOR_BASE_P(REGNO) 1353 1354/* Maximum number of registers that can appear in a valid memory address. 1355 Shifts in addresses can't be by a register. */ 1356 1357#define MAX_REGS_PER_ADDRESS 2 1358 1359/* Recognize any constant value that is a valid address. */ 1360/* XXX We can address any constant, eventually... */ 1361 1362#ifdef AOF_ASSEMBLER 1363 1364#define CONSTANT_ADDRESS_P(X) \ 1365 (GET_CODE (X) == SYMBOL_REF \ 1366 && CONSTANT_POOL_ADDRESS_P (X)) 1367 1368#else 1369 1370#define CONSTANT_ADDRESS_P(X) \ 1371 (GET_CODE (X) == SYMBOL_REF \ 1372 && (CONSTANT_POOL_ADDRESS_P (X) \ 1373 || (optimize > 0 && SYMBOL_REF_FLAG (X)))) 1374 1375#endif /* AOF_ASSEMBLER */ 1376 1377/* Nonzero if the constant value X is a legitimate general operand. 1378 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1379 1380 On the ARM, allow any integer (invalid ones are removed later by insn 1381 patterns), nice doubles and symbol_refs which refer to the function's 1382 constant pool XXX. */ 1383#define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X)) 1384 1385/* Symbols in the text segment can be accessed without indirecting via the 1386 constant pool; it may take an extra binary operation, but this is still 1387 faster than indirecting via memory. Don't do this when not optimizing, 1388 since we won't be calculating al of the offsets necessary to do this 1389 simplification. */ 1390/* This doesn't work with AOF syntax, since the string table may be in 1391 a different AREA. */ 1392#ifndef AOF_ASSEMBLER 1393#define ENCODE_SECTION_INFO(decl) \ 1394{ \ 1395 if (optimize > 0 && TREE_CONSTANT (decl) \ 1396 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \ 1397 { \ 1398 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \ 1399 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \ 1400 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \ 1401 } \ 1402} 1403#endif 1404 1405/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1406 and check its validity for a certain class. 1407 We have two alternate definitions for each of them. 1408 The usual definition accepts all pseudo regs; the other rejects 1409 them unless they have been allocated suitable hard regs. 1410 The symbol REG_OK_STRICT causes the latter definition to be used. */ 1411#ifndef REG_OK_STRICT 1412 1413/* Nonzero if X is a hard reg that can be used as a base reg 1414 or if it is a pseudo reg. */ 1415#define REG_OK_FOR_BASE_P(X) \ 1416 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1417 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM) 1418 1419/* Nonzero if X is a hard reg that can be used as an index 1420 or if it is a pseudo reg. */ 1421#define REG_OK_FOR_INDEX_P(X) \ 1422 REG_OK_FOR_BASE_P(X) 1423 1424#define REG_OK_FOR_PRE_POST_P(X) \ 1425 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1426 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM) 1427 1428#else 1429 1430/* Nonzero if X is a hard reg that can be used as a base reg. */ 1431#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1432 1433/* Nonzero if X is a hard reg that can be used as an index. */ 1434#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1435 1436#define REG_OK_FOR_PRE_POST_P(X) \ 1437 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \ 1438 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \ 1439 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \ 1440 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM) 1441 1442#endif 1443 1444/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1445 that is a valid memory address for an instruction. 1446 The MODE argument is the machine mode for the MEM expression 1447 that wants to use this address. 1448 1449 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 1450#define BASE_REGISTER_RTX_P(X) \ 1451 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) 1452 1453#define INDEX_REGISTER_RTX_P(X) \ 1454 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) 1455 1456/* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs 1457 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can 1458 only be small constants. */ 1459#define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \ 1460do \ 1461{ \ 1462 HOST_WIDE_INT range; \ 1463 enum rtx_code code = GET_CODE (INDEX); \ 1464 \ 1465 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ 1466 { \ 1467 if (code == CONST_INT && INTVAL (INDEX) < 1024 \ 1468 && INTVAL (INDEX) > -1024 \ 1469 && (INTVAL (INDEX) & 3) == 0) \ 1470 goto LABEL; \ 1471 } \ 1472 else \ 1473 { \ 1474 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \ 1475 goto LABEL; \ 1476 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \ 1477 && (! arm_arch4 || (MODE) != HImode)) \ 1478 { \ 1479 rtx xiop0 = XEXP (INDEX, 0); \ 1480 rtx xiop1 = XEXP (INDEX, 1); \ 1481 if (INDEX_REGISTER_RTX_P (xiop0) \ 1482 && power_of_two_operand (xiop1, SImode)) \ 1483 goto LABEL; \ 1484 if (INDEX_REGISTER_RTX_P (xiop1) \ 1485 && power_of_two_operand (xiop0, SImode)) \ 1486 goto LABEL; \ 1487 } \ 1488 if (GET_MODE_SIZE (MODE) <= 4 \ 1489 && (code == LSHIFTRT || code == ASHIFTRT \ 1490 || code == ASHIFT || code == ROTATERT) \ 1491 && (! arm_arch4 || (MODE) != HImode)) \ 1492 { \ 1493 rtx op = XEXP (INDEX, 1); \ 1494 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \ 1495 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \ 1496 && INTVAL (op) <= 31) \ 1497 goto LABEL; \ 1498 } \ 1499 /* NASTY: Since this limits the addressing of unsigned byte loads */ \ 1500 range = ((MODE) == HImode || (MODE) == QImode) \ 1501 ? (arm_arch4 ? 256 : 4095) : 4096; \ 1502 if (code == CONST_INT && INTVAL (INDEX) < range \ 1503 && INTVAL (INDEX) > -range) \ 1504 goto LABEL; \ 1505 } \ 1506} while (0) 1507 1508/* Jump to LABEL if X is a valid address RTX. This must also take 1509 REG_OK_STRICT into account when deciding about valid registers, but it uses 1510 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX, 1511 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool. 1512 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol 1513 refs must be forced though a static cell to ensure addressability. */ 1514#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 1515{ \ 1516 if (BASE_REGISTER_RTX_P (X)) \ 1517 goto LABEL; \ 1518 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ 1519 && GET_CODE (XEXP (X, 0)) == REG \ 1520 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ 1521 goto LABEL; \ 1522 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ 1523 && (GET_CODE (X) == LABEL_REF \ 1524 || (GET_CODE (X) == CONST \ 1525 && GET_CODE (XEXP ((X), 0)) == PLUS \ 1526 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \ 1527 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\ 1528 goto LABEL; \ 1529 else if ((MODE) == TImode) \ 1530 ; \ 1531 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \ 1532 { \ 1533 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \ 1534 && GET_CODE (XEXP (X, 1)) == CONST_INT) \ 1535 { \ 1536 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ 1537 if (val == 4 || val == -4 || val == -8) \ 1538 goto LABEL; \ 1539 } \ 1540 } \ 1541 else if (GET_CODE (X) == PLUS) \ 1542 { \ 1543 rtx xop0 = XEXP(X,0); \ 1544 rtx xop1 = XEXP(X,1); \ 1545 \ 1546 if (BASE_REGISTER_RTX_P (xop0)) \ 1547 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ 1548 else if (BASE_REGISTER_RTX_P (xop1)) \ 1549 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ 1550 } \ 1551 /* Reload currently can't handle MINUS, so disable this for now */ \ 1552 /* else if (GET_CODE (X) == MINUS) \ 1553 { \ 1554 rtx xop0 = XEXP (X,0); \ 1555 rtx xop1 = XEXP (X,1); \ 1556 \ 1557 if (BASE_REGISTER_RTX_P (xop0)) \ 1558 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \ 1559 } */ \ 1560 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ 1561 && GET_CODE (X) == SYMBOL_REF \ 1562 && CONSTANT_POOL_ADDRESS_P (X) \ 1563 && ! (flag_pic \ 1564 && symbol_mentioned_p (get_pool_constant (X)))) \ 1565 goto LABEL; \ 1566 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ 1567 && (GET_MODE_SIZE (MODE) <= 4) \ 1568 && GET_CODE (XEXP (X, 0)) == REG \ 1569 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ 1570 goto LABEL; \ 1571} 1572 1573/* Try machine-dependent ways of modifying an illegitimate address 1574 to be legitimate. If we find one, return the new, valid address. 1575 This macro is used in only one place: `memory_address' in explow.c. 1576 1577 OLDX is the address as it was before break_out_memory_refs was called. 1578 In some cases it is useful to look at this to decide what needs to be done. 1579 1580 MODE and WIN are passed so that this macro can use 1581 GO_IF_LEGITIMATE_ADDRESS. 1582 1583 It is always safe for this macro to do nothing. It exists to recognize 1584 opportunities to optimize the output. 1585 1586 On the ARM, try to convert [REG, #BIGCONST] 1587 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST], 1588 where VALIDCONST == 0 in case of TImode. */ 1589extern struct rtx_def *legitimize_pic_address (); 1590#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 1591{ \ 1592 if (GET_CODE (X) == PLUS) \ 1593 { \ 1594 rtx xop0 = XEXP (X, 0); \ 1595 rtx xop1 = XEXP (X, 1); \ 1596 \ 1597 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \ 1598 xop0 = force_reg (SImode, xop0); \ 1599 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ 1600 xop1 = force_reg (SImode, xop1); \ 1601 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \ 1602 { \ 1603 HOST_WIDE_INT n, low_n; \ 1604 rtx base_reg, val; \ 1605 n = INTVAL (xop1); \ 1606 \ 1607 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ 1608 { \ 1609 low_n = n & 0x0f; \ 1610 n &= ~0x0f; \ 1611 if (low_n > 4) \ 1612 { \ 1613 n += 16; \ 1614 low_n -= 16; \ 1615 } \ 1616 } \ 1617 else \ 1618 { \ 1619 low_n = ((MODE) == TImode ? 0 \ 1620 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \ 1621 n -= low_n; \ 1622 } \ 1623 base_reg = gen_reg_rtx (SImode); \ 1624 val = force_operand (gen_rtx_PLUS (SImode, xop0, \ 1625 GEN_INT (n)), NULL_RTX); \ 1626 emit_move_insn (base_reg, val); \ 1627 (X) = (low_n == 0 ? base_reg \ 1628 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \ 1629 } \ 1630 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \ 1631 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \ 1632 } \ 1633 else if (GET_CODE (X) == MINUS) \ 1634 { \ 1635 rtx xop0 = XEXP (X, 0); \ 1636 rtx xop1 = XEXP (X, 1); \ 1637 \ 1638 if (CONSTANT_P (xop0)) \ 1639 xop0 = force_reg (SImode, xop0); \ 1640 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ 1641 xop1 = force_reg (SImode, xop1); \ 1642 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \ 1643 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \ 1644 } \ 1645 if (flag_pic) \ 1646 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ 1647 if (memory_address_p (MODE, X)) \ 1648 goto WIN; \ 1649} 1650 1651/* Go to LABEL if ADDR (a legitimate address expression) 1652 has an effect that depends on the machine mode it is used for. */ 1653#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1654{ \ 1655 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \ 1656 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \ 1657 goto LABEL; \ 1658} 1659 1660/* Specify the machine mode that this machine uses 1661 for the index in the tablejump instruction. */ 1662#define CASE_VECTOR_MODE SImode 1663 1664/* Define as C expression which evaluates to nonzero if the tablejump 1665 instruction expects the table to contain offsets from the address of the 1666 table. 1667 Do not define this if the table should contain absolute addresses. */ 1668/* #define CASE_VECTOR_PC_RELATIVE 1 */ 1669 1670/* Specify the tree operation to be used to convert reals to integers. */ 1671#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR 1672 1673/* This is the kind of divide that is easiest to do in the general case. */ 1674#define EASY_DIV_EXPR TRUNC_DIV_EXPR 1675 1676/* signed 'char' is most compatible, but RISC OS wants it unsigned. 1677 unsigned is probably best, but may break some code. */ 1678#ifndef DEFAULT_SIGNED_CHAR 1679#define DEFAULT_SIGNED_CHAR 0 1680#endif 1681 1682/* Don't cse the address of the function being compiled. */ 1683#define NO_RECURSIVE_FUNCTION_CSE 1 1684 1685/* Max number of bytes we can move from memory to memory 1686 in one reasonably fast instruction. */ 1687#define MOVE_MAX 4 1688 1689/* Define if operations between registers always perform the operation 1690 on the full register even if a narrower mode is specified. */ 1691#define WORD_REGISTER_OPERATIONS 1692 1693/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1694 will either zero-extend or sign-extend. The value of this macro should 1695 be the code that says which one of the two operations is implicitly 1696 done, NIL if none. */ 1697#define LOAD_EXTEND_OP(MODE) \ 1698 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 1699 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)) 1700 1701/* Define this if zero-extension is slow (more than one real instruction). 1702 On the ARM, it is more than one instruction only if not fetching from 1703 memory. */ 1704/* #define SLOW_ZERO_EXTEND */ 1705 1706/* Nonzero if access to memory by bytes is slow and undesirable. */ 1707#define SLOW_BYTE_ACCESS 0 1708 1709/* Immediate shift counts are truncated by the output routines (or was it 1710 the assembler?). Shift counts in a register are truncated by ARM. Note 1711 that the native compiler puts too large (> 32) immediate shift counts 1712 into a register and shifts by the register, letting the ARM decide what 1713 to do instead of doing that itself. */ 1714/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 1715 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 1716 On the arm, Y in a register is used modulo 256 for the shift. Only for 1717 rotates is modulo 32 used. */ 1718/* #define SHIFT_COUNT_TRUNCATED 1 */ 1719 1720/* All integers have the same format so truncation is easy. */ 1721#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 1722 1723/* Calling from registers is a massive pain. */ 1724#define NO_FUNCTION_CSE 1 1725 1726/* Chars and shorts should be passed as ints. */ 1727#define PROMOTE_PROTOTYPES 1 1728 1729/* The machine modes of pointers and functions */ 1730#define Pmode SImode 1731#define FUNCTION_MODE Pmode 1732 1733/* The structure type of the machine dependent info field of insns 1734 No uses for this yet. */ 1735/* #define INSN_MACHINE_INFO struct machine_info */ 1736 1737/* The relative costs of various types of constants. Note that cse.c defines 1738 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ 1739#define CONST_COSTS(RTX, CODE, OUTER_CODE) \ 1740 case CONST_INT: \ 1741 if (const_ok_for_arm (INTVAL (RTX))) \ 1742 return (OUTER_CODE) == SET ? 2 : -1; \ 1743 else if (OUTER_CODE == AND \ 1744 && const_ok_for_arm (~INTVAL (RTX))) \ 1745 return -1; \ 1746 else if ((OUTER_CODE == COMPARE \ 1747 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \ 1748 && const_ok_for_arm (-INTVAL (RTX))) \ 1749 return -1; \ 1750 else \ 1751 return 5; \ 1752 case CONST: \ 1753 case LABEL_REF: \ 1754 case SYMBOL_REF: \ 1755 return 6; \ 1756 case CONST_DOUBLE: \ 1757 if (const_double_rtx_ok_for_fpu (RTX)) \ 1758 return (OUTER_CODE) == SET ? 2 : -1; \ 1759 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \ 1760 && neg_const_double_rtx_ok_for_fpu (RTX)) \ 1761 return -1; \ 1762 return(7); 1763 1764#define ARM_FRAME_RTX(X) \ 1765 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 1766 || (X) == arg_pointer_rtx) 1767 1768#define DEFAULT_RTX_COSTS(X,CODE,OUTER_CODE) \ 1769 return arm_rtx_costs (X, CODE); 1770 1771/* Moves to and from memory are quite expensive */ 1772#define MEMORY_MOVE_COST(MODE,CLASS,IN) 10 1773 1774/* All address computations that can be done are free, but rtx cost returns 1775 the same for practically all of them. So we weight the different types 1776 of address here in the order (most pref first): 1777 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ 1778#define ADDRESS_COST(X) \ 1779 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \ 1780 || GET_CODE (X) == SYMBOL_REF) \ 1781 ? 0 \ 1782 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \ 1783 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ 1784 ? 10 \ 1785 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \ 1786 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \ 1787 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \ 1788 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \ 1789 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \ 1790 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \ 1791 ? 1 : 0)) \ 1792 : 4))))) 1793 1794 1795 1796/* Try to generate sequences that don't involve branches, we can then use 1797 conditional instructions */ 1798#define BRANCH_COST 4 1799 1800/* A C statement to update the variable COST based on the relationship 1801 between INSN that is dependent on DEP through dependence LINK. */ 1802#define ADJUST_COST(INSN,LINK,DEP,COST) \ 1803 (COST) = arm_adjust_cost ((INSN), (LINK), (DEP), (COST)) 1804 1805/* Position Independent Code. */ 1806/* We decide which register to use based on the compilation options and 1807 the assembler in use; this is more general than the APCS restriction of 1808 using sb (r9) all the time. */ 1809extern int arm_pic_register; 1810 1811/* The register number of the register used to address a table of static 1812 data addresses in memory. */ 1813#define PIC_OFFSET_TABLE_REGNUM arm_pic_register 1814 1815#define FINALIZE_PIC arm_finalize_pic () 1816 1817/* We can't directly access anything that contains a symbol, 1818 nor can we indirect via the constant pool. */ 1819#define LEGITIMATE_PIC_OPERAND_P(X) \ 1820 (! symbol_mentioned_p (X) \ 1821 && (! CONSTANT_POOL_ADDRESS_P (X) \ 1822 || ! symbol_mentioned_p (get_pool_constant (X)))) 1823 1824/* We need to know when we are making a constant pool; this determines 1825 whether data needs to be in the GOT or can be referenced via a GOT 1826 offset. */ 1827extern int making_const_table; 1828 1829 1830/* Condition code information. */ 1831/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1832 return the mode to be used for the comparison. 1833 CCFPEmode should be used with floating inequalities, 1834 CCFPmode should be used with floating equalities. 1835 CC_NOOVmode should be used with SImode integer equalities. 1836 CC_Zmode should be used if only the Z flag is set correctly 1837 CCmode should be used otherwise. */ 1838 1839#define EXTRA_CC_MODES CC_NOOVmode, CC_Zmode, CC_SWPmode, \ 1840 CCFPmode, CCFPEmode, CC_DNEmode, CC_DEQmode, CC_DLEmode, \ 1841 CC_DLTmode, CC_DGEmode, CC_DGTmode, CC_DLEUmode, CC_DLTUmode, \ 1842 CC_DGEUmode, CC_DGTUmode, CC_Cmode 1843 1844#define EXTRA_CC_NAMES "CC_NOOV", "CC_Z", "CC_SWP", "CCFP", "CCFPE", \ 1845 "CC_DNE", "CC_DEQ", "CC_DLE", "CC_DLT", "CC_DGE", "CC_DGT", "CC_DLEU", \ 1846 "CC_DLTU", "CC_DGEU", "CC_DGTU", "CC_C" 1847 1848#define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y)) 1849 1850#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) 1851 1852#define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \ 1853do \ 1854{ \ 1855 if (GET_CODE (OP1) == CONST_INT \ 1856 && ! (const_ok_for_arm (INTVAL (OP1)) \ 1857 || (const_ok_for_arm (- INTVAL (OP1))))) \ 1858 { \ 1859 rtx const_op = OP1; \ 1860 CODE = arm_canonicalize_comparison ((CODE), &const_op); \ 1861 OP1 = const_op; \ 1862 } \ 1863} while (0) 1864 1865#define STORE_FLAG_VALUE 1 1866 1867/* Define the information needed to generate branch insns. This is 1868 stored from the compare operation. Note that we can't use "rtx" here 1869 since it hasn't been defined! */ 1870 1871extern struct rtx_def *arm_compare_op0, *arm_compare_op1; 1872 1873/* Define the codes that are matched by predicates in arm.c */ 1874#define PREDICATE_CODES \ 1875 {"s_register_operand", {SUBREG, REG}}, \ 1876 {"f_register_operand", {SUBREG, REG}}, \ 1877 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ 1878 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ 1879 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ 1880 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ 1881 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ 1882 {"offsettable_memory_operand", {MEM}}, \ 1883 {"bad_signed_byte_operand", {MEM}}, \ 1884 {"alignable_memory_operand", {MEM}}, \ 1885 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ 1886 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ 1887 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \ 1888 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ 1889 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ 1890 {"load_multiple_operation", {PARALLEL}}, \ 1891 {"store_multiple_operation", {PARALLEL}}, \ 1892 {"equality_operator", {EQ, NE}}, \ 1893 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ 1894 {"const_shift_operand", {CONST_INT}}, \ 1895 {"index_operand", {SUBREG, REG, CONST_INT}}, \ 1896 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ 1897 {"multi_register_push", {PARALLEL}}, \ 1898 {"cc_register", {REG}}, \ 1899 {"dominant_cc_register", {REG}}, 1900 1901 1902 1903/* Gcc puts the pool in the wrong place for ARM, since we can only 1904 load addresses a limited distance around the pc. We do some 1905 special munging to move the constant pool values to the correct 1906 point in the code. */ 1907#define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN)) 1908 1909/* The pool is empty, since we have moved everything into the code. */ 1910#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE,X,MODE,ALIGN,LABELNO,JUMPTO) \ 1911 goto JUMPTO 1912 1913/* Output an internal label definition. */ 1914#ifndef ASM_OUTPUT_INTERNAL_LABEL 1915#define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ 1916 do \ 1917 { \ 1918 char * s = (char *) alloca (40 + strlen (PREFIX)); \ 1919 extern int arm_target_label, arm_ccfsm_state; \ 1920 extern rtx arm_target_insn; \ 1921 \ 1922 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \ 1923 && !strcmp (PREFIX, "L")) \ 1924 { \ 1925 arm_ccfsm_state = 0; \ 1926 arm_target_insn = NULL; \ 1927 } \ 1928 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \ 1929 ASM_OUTPUT_LABEL (STREAM, s); \ 1930 } while (0) 1931#endif 1932 1933/* Output a push or a pop instruction (only used when profiling). */ 1934#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ 1935 fprintf (STREAM,"\tstmfd\t%ssp!,{%s%s}\n", \ 1936 REGISTER_PREFIX, REGISTER_PREFIX, reg_names [REGNO]) 1937 1938#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ 1939 fprintf (STREAM,"\tldmfd\t%ssp!,{%s%s}\n", \ 1940 REGISTER_PREFIX, REGISTER_PREFIX, reg_names [REGNO]) 1941 1942/* Target characters. */ 1943#define TARGET_BELL 007 1944#define TARGET_BS 010 1945#define TARGET_TAB 011 1946#define TARGET_NEWLINE 012 1947#define TARGET_VT 013 1948#define TARGET_FF 014 1949#define TARGET_CR 015 1950 1951/* Only perform branch elimination (by making instructions conditional) if 1952 we're optimising. Otherwise it's of no use anyway. */ 1953#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 1954 if (optimize) \ 1955 arm_final_prescan_insn (INSN) 1956 1957#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 1958 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@') 1959/* Output an operand of an instruction. */ 1960#define PRINT_OPERAND(STREAM, X, CODE) \ 1961 arm_print_operand (STREAM, X, CODE) 1962 1963#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 1964 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \ 1965 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \ 1966 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \ 1967 ? ((~ (HOST_WIDE_INT) 0) \ 1968 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 1969 : 0)))) 1970 1971/* Output the address of an operand. */ 1972#define PRINT_OPERAND_ADDRESS(STREAM,X) \ 1973{ \ 1974 int is_minus = GET_CODE (X) == MINUS; \ 1975 \ 1976 if (GET_CODE (X) == REG) \ 1977 fprintf (STREAM, "[%s%s, #0]", REGISTER_PREFIX, \ 1978 reg_names[REGNO (X)]); \ 1979 else if (GET_CODE (X) == PLUS || is_minus) \ 1980 { \ 1981 rtx base = XEXP (X, 0); \ 1982 rtx index = XEXP (X, 1); \ 1983 char * base_reg_name; \ 1984 HOST_WIDE_INT offset = 0; \ 1985 if (GET_CODE (base) != REG) \ 1986 { \ 1987 /* Ensure that BASE is a register (one of them must be). */ \ 1988 rtx temp = base; \ 1989 base = index; \ 1990 index = temp; \ 1991 } \ 1992 base_reg_name = reg_names[REGNO (base)]; \ 1993 switch (GET_CODE (index)) \ 1994 { \ 1995 case CONST_INT: \ 1996 offset = INTVAL (index); \ 1997 if (is_minus) \ 1998 offset = -offset; \ 1999 fprintf (STREAM, "[%s%s, #%d]", REGISTER_PREFIX, \ 2000 base_reg_name, offset); \ 2001 break; \ 2002 \ 2003 case REG: \ 2004 fprintf (STREAM, "[%s%s, %s%s%s]", REGISTER_PREFIX, \ 2005 base_reg_name, is_minus ? "-" : "", \ 2006 REGISTER_PREFIX, reg_names[REGNO (index)] ); \ 2007 break; \ 2008 \ 2009 case MULT: \ 2010 case ASHIFTRT: \ 2011 case LSHIFTRT: \ 2012 case ASHIFT: \ 2013 case ROTATERT: \ 2014 { \ 2015 fprintf (STREAM, "[%s%s, %s%s%s", REGISTER_PREFIX, \ 2016 base_reg_name, is_minus ? "-" : "", REGISTER_PREFIX,\ 2017 reg_names[REGNO (XEXP (index, 0))]); \ 2018 arm_print_operand (STREAM, index, 'S'); \ 2019 fputs ("]", STREAM); \ 2020 break; \ 2021 } \ 2022 \ 2023 default: \ 2024 abort(); \ 2025 } \ 2026 } \ 2027 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ 2028 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ 2029 { \ 2030 extern int output_memory_reference_mode; \ 2031 \ 2032 if (GET_CODE (XEXP (X, 0)) != REG) \ 2033 abort (); \ 2034 \ 2035 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ 2036 fprintf (STREAM, "[%s%s, #%s%d]!", REGISTER_PREFIX, \ 2037 reg_names[REGNO (XEXP (X, 0))], \ 2038 GET_CODE (X) == PRE_DEC ? "-" : "", \ 2039 GET_MODE_SIZE (output_memory_reference_mode)); \ 2040 else \ 2041 fprintf (STREAM, "[%s%s], #%s%d", REGISTER_PREFIX, \ 2042 reg_names[REGNO (XEXP (X, 0))], \ 2043 GET_CODE (X) == POST_DEC ? "-" : "", \ 2044 GET_MODE_SIZE (output_memory_reference_mode)); \ 2045 } \ 2046 else output_addr_const(STREAM, X); \ 2047} 2048 2049/* Handles PIC addr specially */ 2050#define OUTPUT_INT_ADDR_CONST(STREAM,X) \ 2051 { \ 2052 if (flag_pic && GET_CODE(X) == CONST && is_pic(X)) \ 2053 { \ 2054 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \ 2055 fputs(" - (", STREAM); \ 2056 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \ 2057 fputs(")", STREAM); \ 2058 } \ 2059 else output_addr_const(STREAM, X); \ 2060 \ 2061 /* Mark symbols as position independent. We only do this in the \ 2062 .text segment, not in the .data segment. */ \ 2063 if (NEED_PLT_GOT && flag_pic && making_const_table && \ 2064 (GET_CODE(X) == SYMBOL_REF || GET_CODE(X) == LABEL_REF)) \ 2065 { \ 2066 if (GET_CODE(X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P(X)) \ 2067 fprintf(STREAM, "(GOTOFF)"); \ 2068 else if (GET_CODE (X) == LABEL_REF) \ 2069 fprintf(STREAM, "(GOTOFF)"); \ 2070 else \ 2071 fprintf(STREAM, "(GOT)"); \ 2072 } \ 2073 } 2074 2075/* Output code to add DELTA to the first argument, and then jump to FUNCTION. 2076 Used for C++ multiple inheritance. */ 2077#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ 2078do { \ 2079 int mi_delta = (DELTA); \ 2080 char *mi_op = mi_delta < 0 ? "sub" : "add"; \ 2081 int shift = 0; \ 2082 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \ 2083 ? 1 : 0); \ 2084 if (mi_delta < 0) mi_delta = -mi_delta; \ 2085 while (mi_delta != 0) \ 2086 { \ 2087 if (mi_delta & (3 << shift) == 0) \ 2088 shift += 2; \ 2089 else \ 2090 { \ 2091 fprintf (FILE, "\t%s\t%s%s, %s%s, #%d\n", \ 2092 mi_op, REGISTER_PREFIX, reg_names[this_regno], \ 2093 REGISTER_PREFIX, reg_names[this_regno], \ 2094 mi_delta & (0xff << shift)); \ 2095 mi_delta &= ~(0xff << shift); \ 2096 shift += 8; \ 2097 } \ 2098 } \ 2099 fputs ("\tb\t", FILE); \ 2100 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ 2101 if (NEED_PLT_GOT) \ 2102 fputs ("(PLT)", FILE); \ 2103 fputc ('\n', FILE); \ 2104} while (0) 2105 2106/* A C expression whose value is RTL representing the value of the return 2107 address for the frame COUNT steps up from the current frame. */ 2108 2109#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2110 ((COUNT == 0) \ 2111 ? gen_rtx_MEM (Pmode, plus_constant (FRAME, -4)) \ 2112 : NULL_RTX) 2113 2114/* Used to mask out junk bits from the return address, such as 2115 processor state, interrupt status, condition codes and the like. */ 2116#define MASK_RETURN_ADDR \ 2117 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2118 in 26 bit mode, the condition codes must be masked out of the \ 2119 return address. This does not apply to ARM6 and later processors \ 2120 when running in 32 bit mode. */ \ 2121 ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff))) 2122 2123/* The remainder of this file is only needed for building the compiler 2124 itself, not for the collateral. */ 2125#ifdef HAVE_CONFIG_H 2126 2127/* Prototypes for functions in arm.c */ 2128 2129#ifdef BUFSIZ /* stdio.h has been included, ok to use FILE * */ 2130#define STDIO_PROTO(ARGS) PROTO (ARGS) 2131#else 2132#define STDIO_PROTO(ARGS) () 2133#endif 2134 2135#ifndef TREE_CODE 2136union tree_node; 2137#define Tree union tree_node * 2138#else 2139#define Tree tree 2140#endif 2141 2142#ifndef RTX_CODE 2143struct rtx_def; 2144#define Rtx struct rtx_def * 2145#else 2146#define Rtx rtx 2147#endif 2148 2149#ifndef HOST_WIDE_INT 2150#include "hwint.h" 2151#endif 2152 2153#ifndef HAVE_MACHINE_MODES 2154#include "machmode.h" 2155#endif 2156#define Mmode enum machine_mode 2157 2158#ifdef RTX_CODE 2159#define RTX_CODE_PROTO(ARGS) PROTO (ARGS) 2160#else 2161#define RTX_CODE_PROTO(ARGS) () 2162#endif 2163#define Rcode enum rtx_code 2164 2165void arm_override_options PROTO ((void)); 2166int use_return_insn PROTO ((int)); 2167int const_ok_for_arm PROTO ((HOST_WIDE_INT)); 2168int arm_split_constant RTX_CODE_PROTO ((Rcode, Mmode, HOST_WIDE_INT, Rtx, Rtx, int)); 2169Rcode arm_canonicalize_comparison RTX_CODE_PROTO ((Rcode, Rtx *)); 2170int arm_return_in_memory PROTO ((Tree)); 2171int legitimate_pic_operand_p PROTO ((Rtx)); 2172Rtx legitimize_pic_address PROTO ((Rtx, Mmode, Rtx)); 2173int is_pic PROTO ((Rtx)); 2174void arm_finalize_pic PROTO ((void)); 2175int arm_rtx_costs RTX_CODE_PROTO ((Rtx, Rcode)); 2176int arm_adjust_cost PROTO ((Rtx, Rtx, Rtx, int)); 2177int const_double_rtx_ok_for_fpu PROTO ((Rtx)); 2178int neg_const_double_rtx_ok_for_fpu PROTO ((Rtx)); 2179int s_register_operand PROTO ((Rtx, Mmode)); 2180int f_register_operand PROTO ((Rtx, Mmode)); 2181int reg_or_int_operand PROTO ((Rtx, Mmode)); 2182int reload_memory_operand PROTO ((Rtx, Mmode)); 2183int arm_rhs_operand PROTO ((Rtx, Mmode)); 2184int arm_rhsm_operand PROTO ((Rtx, Mmode)); 2185int arm_add_operand PROTO ((Rtx, Mmode)); 2186int arm_not_operand PROTO ((Rtx, Mmode)); 2187int offsettable_memory_operand PROTO ((Rtx, Mmode)); 2188int alignable_memory_operand PROTO ((Rtx, Mmode)); 2189int bad_signed_byte_operand PROTO ((Rtx, Mmode)); 2190int fpu_rhs_operand PROTO ((Rtx, Mmode)); 2191int fpu_add_operand PROTO ((Rtx, Mmode)); 2192int power_of_two_operand PROTO ((Rtx, Mmode)); 2193int di_operand PROTO ((Rtx, Mmode)); 2194int soft_df_operand PROTO ((Rtx, Mmode)); 2195int index_operand PROTO ((Rtx, Mmode)); 2196int const_shift_operand PROTO ((Rtx, Mmode)); 2197int shiftable_operator PROTO ((Rtx, Mmode)); 2198int shift_operator PROTO ((Rtx, Mmode)); 2199int equality_operator PROTO ((Rtx, Mmode)); 2200int minmax_operator PROTO ((Rtx, Mmode)); 2201int cc_register PROTO ((Rtx, Mmode)); 2202int dominant_cc_register PROTO ((Rtx, Mmode)); 2203int symbol_mentioned_p PROTO ((Rtx)); 2204int label_mentioned_p PROTO ((Rtx)); 2205Rcode minmax_code PROTO ((Rtx)); 2206int adjacent_mem_locations PROTO ((Rtx, Rtx)); 2207int load_multiple_operation PROTO ((Rtx, Mmode)); 2208int store_multiple_operation PROTO ((Rtx, Mmode)); 2209int load_multiple_sequence PROTO ((Rtx *, int, int *, int *, HOST_WIDE_INT *)); 2210char * emit_ldm_seq PROTO ((Rtx *, int)); 2211int store_multiple_sequence PROTO ((Rtx *, int, int *, int *, HOST_WIDE_INT *)); 2212char * emit_stm_seq PROTO ((Rtx *, int)); 2213int arm_valid_machine_decl_attribute PROTO ((Tree, Tree, Tree)); 2214Rtx arm_gen_load_multiple PROTO ((int, int, Rtx, int, int, int, int, int)); 2215Rtx arm_gen_store_multiple PROTO ((int, int, Rtx, int, int, int, int, int)); 2216int arm_gen_movstrqi PROTO ((Rtx *)); 2217Rtx gen_rotated_half_load PROTO ((Rtx)); 2218Mmode arm_select_cc_mode RTX_CODE_PROTO ((Rcode, Rtx, Rtx)); 2219Rtx gen_compare_reg RTX_CODE_PROTO ((Rcode, Rtx, Rtx, int)); 2220void arm_reload_in_hi PROTO ((Rtx *)); 2221void arm_reload_out_hi PROTO ((Rtx *)); 2222void arm_reorg PROTO ((Rtx)); 2223char * fp_immediate_constant PROTO ((Rtx)); 2224void print_multi_reg STDIO_PROTO ((FILE *, char *, int, int)); 2225char * output_call PROTO ((Rtx *)); 2226char * output_call_mem PROTO ((Rtx *)); 2227char * output_mov_long_double_fpu_from_arm PROTO ((Rtx *)); 2228char * output_mov_long_double_arm_from_fpu PROTO ((Rtx *)); 2229char * output_mov_long_double_arm_from_arm PROTO ((Rtx *)); 2230char * output_mov_double_fpu_from_arm PROTO ((Rtx *)); 2231char * output_mov_double_arm_from_fpu PROTO ((Rtx *)); 2232char * output_move_double PROTO ((Rtx *)); 2233char * output_mov_immediate PROTO ((Rtx *)); 2234char * output_add_immediate PROTO ((Rtx *)); 2235char * arithmetic_instr PROTO ((Rtx, int)); 2236void output_ascii_pseudo_op STDIO_PROTO ((FILE *, unsigned char *, int)); 2237char * output_return_instruction PROTO ((Rtx, int, int)); 2238int arm_volatile_func PROTO ((void)); 2239void arm_poke_function_name STDIO_PROTO ((FILE *, char *)); 2240void output_func_prologue STDIO_PROTO ((FILE *, int)); 2241void output_func_epilogue STDIO_PROTO ((FILE *, int)); 2242void arm_expand_prologue PROTO ((void)); 2243void arm_print_operand STDIO_PROTO ((FILE *, Rtx, int)); 2244void arm_final_prescan_insn PROTO ((Rtx)); 2245int short_branch PROTO ((int, int)); 2246void assemble_align PROTO((int)); /* Used in arm.md, but defined in output.c */ 2247int multi_register_push PROTO ((Rtx, Mmode)); 2248#ifdef AOF_ASSEMBLER 2249Rtx aof_pic_entry PROTO ((Rtx)); 2250void aof_dump_pic_table STDIO_PROTO ((FILE *)); 2251char * aof_text_section PROTO ((void)); 2252char * aof_data_section PROTO ((void)); 2253void aof_add_import PROTO ((char *)); 2254void aof_delete_import PROTO ((char *)); 2255void aof_dump_imports STDIO_PROTO ((FILE *)); 2256#endif 2257#endif /* HAVE_CONFIG_H */ 2258 2259#endif /* __ARM_H__ */ 2260