1/* CPU data for fr30.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright 1996-2005 Free Software Foundation, Inc.
6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2151 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
23*/
24
25#include "sysdep.h"
26#include <stdio.h>
27#include <stdarg.h>
28#include "ansidecl.h"
29#include "bfd.h"
30#include "symcat.h"
31#include "fr30-desc.h"
32#include "fr30-opc.h"
33#include "opintl.h"
34#include "libiberty.h"
35#include "xregex.h"
36
37/* Attributes.  */
38
39static const CGEN_ATTR_ENTRY bool_attr[] =
40{
41  { "#f", 0 },
42  { "#t", 1 },
43  { 0, 0 }
44};
45
46static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
47{
48  { "base", MACH_BASE },
49  { "fr30", MACH_FR30 },
50  { "max", MACH_MAX },
51  { 0, 0 }
52};
53
54static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
55{
56  { "fr30", ISA_FR30 },
57  { "max", ISA_MAX },
58  { 0, 0 }
59};
60
61const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
62{
63  { "MACH", & MACH_attr[0], & MACH_attr[0] },
64  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
65  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
66  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
67  { "RESERVED", &bool_attr[0], &bool_attr[0] },
68  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
69  { "SIGNED", &bool_attr[0], &bool_attr[0] },
70  { 0, 0, 0 }
71};
72
73const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
74{
75  { "MACH", & MACH_attr[0], & MACH_attr[0] },
76  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
77  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
78  { "PC", &bool_attr[0], &bool_attr[0] },
79  { "PROFILE", &bool_attr[0], &bool_attr[0] },
80  { 0, 0, 0 }
81};
82
83const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
84{
85  { "MACH", & MACH_attr[0], & MACH_attr[0] },
86  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
87  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
88  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
89  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
90  { "SIGNED", &bool_attr[0], &bool_attr[0] },
91  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
92  { "RELAX", &bool_attr[0], &bool_attr[0] },
93  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
94  { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
95  { 0, 0, 0 }
96};
97
98const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
99{
100  { "MACH", & MACH_attr[0], & MACH_attr[0] },
101  { "ALIAS", &bool_attr[0], &bool_attr[0] },
102  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
103  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
104  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
105  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
106  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
107  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
108  { "RELAXED", &bool_attr[0], &bool_attr[0] },
109  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
110  { "PBB", &bool_attr[0], &bool_attr[0] },
111  { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
112  { 0, 0, 0 }
113};
114
115/* Instruction set variants.  */
116
117static const CGEN_ISA fr30_cgen_isa_table[] = {
118  { "fr30", 16, 16, 16, 48 },
119  { 0, 0, 0, 0, 0 }
120};
121
122/* Machine variants.  */
123
124static const CGEN_MACH fr30_cgen_mach_table[] = {
125  { "fr30", "fr30", MACH_FR30, 0 },
126  { 0, 0, 0, 0 }
127};
128
129static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
130{
131  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
132  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
133  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
134  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
135  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
136  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
137  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
138  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
139  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
140  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
141  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
142  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
143  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
144  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
145  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
146  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
147  { "ac", 13, {0, {{{0, 0}}}}, 0, 0 },
148  { "fp", 14, {0, {{{0, 0}}}}, 0, 0 },
149  { "sp", 15, {0, {{{0, 0}}}}, 0, 0 }
150};
151
152CGEN_KEYWORD fr30_cgen_opval_gr_names =
153{
154  & fr30_cgen_opval_gr_names_entries[0],
155  19,
156  0, 0, 0, 0, ""
157};
158
159static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
160{
161  { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 },
162  { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 },
163  { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 },
164  { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 },
165  { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 },
166  { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 },
167  { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 },
168  { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 },
169  { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 },
170  { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 },
171  { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 },
172  { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 },
173  { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 },
174  { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 },
175  { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 },
176  { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 }
177};
178
179CGEN_KEYWORD fr30_cgen_opval_cr_names =
180{
181  & fr30_cgen_opval_cr_names_entries[0],
182  16,
183  0, 0, 0, 0, ""
184};
185
186static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
187{
188  { "tbr", 0, {0, {{{0, 0}}}}, 0, 0 },
189  { "rp", 1, {0, {{{0, 0}}}}, 0, 0 },
190  { "ssp", 2, {0, {{{0, 0}}}}, 0, 0 },
191  { "usp", 3, {0, {{{0, 0}}}}, 0, 0 },
192  { "mdh", 4, {0, {{{0, 0}}}}, 0, 0 },
193  { "mdl", 5, {0, {{{0, 0}}}}, 0, 0 }
194};
195
196CGEN_KEYWORD fr30_cgen_opval_dr_names =
197{
198  & fr30_cgen_opval_dr_names_entries[0],
199  6,
200  0, 0, 0, 0, ""
201};
202
203static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
204{
205  { "ps", 0, {0, {{{0, 0}}}}, 0, 0 }
206};
207
208CGEN_KEYWORD fr30_cgen_opval_h_ps =
209{
210  & fr30_cgen_opval_h_ps_entries[0],
211  1,
212  0, 0, 0, 0, ""
213};
214
215static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
216{
217  { "r13", 0, {0, {{{0, 0}}}}, 0, 0 }
218};
219
220CGEN_KEYWORD fr30_cgen_opval_h_r13 =
221{
222  & fr30_cgen_opval_h_r13_entries[0],
223  1,
224  0, 0, 0, 0, ""
225};
226
227static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
228{
229  { "r14", 0, {0, {{{0, 0}}}}, 0, 0 }
230};
231
232CGEN_KEYWORD fr30_cgen_opval_h_r14 =
233{
234  & fr30_cgen_opval_h_r14_entries[0],
235  1,
236  0, 0, 0, 0, ""
237};
238
239static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
240{
241  { "r15", 0, {0, {{{0, 0}}}}, 0, 0 }
242};
243
244CGEN_KEYWORD fr30_cgen_opval_h_r15 =
245{
246  & fr30_cgen_opval_h_r15_entries[0],
247  1,
248  0, 0, 0, 0, ""
249};
250
251
252/* The hardware table.  */
253
254#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
255#define A(a) (1 << CGEN_HW_##a)
256#else
257#define A(a) (1 << CGEN_HW_/**/a)
258#endif
259
260const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
261{
262  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
263  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
264  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
265  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
266  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
267  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
268  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
269  { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
270  { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
271  { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { { { (1<<MACH_BASE), 0 } } } } },
272  { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { { { (1<<MACH_BASE), 0 } } } } },
273  { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { { { (1<<MACH_BASE), 0 } } } } },
274  { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { { { (1<<MACH_BASE), 0 } } } } },
275  { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
276  { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
277  { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
278  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
279  { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
280  { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
281  { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
282  { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
283  { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
284  { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
285  { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
286  { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
287  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
288};
289
290#undef A
291
292
293/* The instruction field table.  */
294
295#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
296#define A(a) (1 << CGEN_IFLD_##a)
297#else
298#define A(a) (1 << CGEN_IFLD_/**/a)
299#endif
300
301const CGEN_IFLD fr30_cgen_ifld_table[] =
302{
303  { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
304  { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
305  { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
306  { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
307  { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
308  { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
309  { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
310  { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
311  { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
312  { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
313  { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
314  { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
315  { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
316  { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
317  { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
318  { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
319  { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
320  { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
321  { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
322  { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
323  { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
324  { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
325  { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
326  { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
327  { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
328  { FR30_F_I20, "f-i20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
329  { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
330  { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
331  { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
332  { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
333  { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
334  { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
335  { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
336  { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
337  { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
338  { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
339  { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
340  { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
341  { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
342  { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
343  { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
344  { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
345  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
346};
347
348#undef A
349
350
351
352/* multi ifield declarations */
353
354const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [];
355
356
357/* multi ifield definitions */
358
359const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] =
360{
361    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_4] } },
362    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_16] } },
363    { 0, { (const PTR) 0 } }
364};
365
366/* The operand table.  */
367
368#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
369#define A(a) (1 << CGEN_OPERAND_##a)
370#else
371#define A(a) (1 << CGEN_OPERAND_/**/a)
372#endif
373#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
374#define OPERAND(op) FR30_OPERAND_##op
375#else
376#define OPERAND(op) FR30_OPERAND_/**/op
377#endif
378
379const CGEN_OPERAND fr30_cgen_operand_table[] =
380{
381/* pc: program counter */
382  { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
383    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } },
384    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
385/* Ri: destination register */
386  { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
387    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } },
388    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
389/* Rj: source register */
390  { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
391    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } },
392    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
393/* Ric: target register coproc insn */
394  { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
395    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } },
396    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
397/* Rjc: source register coproc insn */
398  { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
399    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } },
400    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
401/* CRi: coprocessor register */
402  { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
403    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } },
404    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
405/* CRj: coprocessor register */
406  { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
407    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } },
408    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
409/* Rs1: dedicated register */
410  { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
411    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } },
412    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
413/* Rs2: dedicated register */
414  { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
415    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } },
416    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
417/* R13: General Register 13 */
418  { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
419    { 0, { (const PTR) 0 } },
420    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
421/* R14: General Register 14 */
422  { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
423    { 0, { (const PTR) 0 } },
424    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
425/* R15: General Register 15 */
426  { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
427    { 0, { (const PTR) 0 } },
428    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
429/* ps: Program Status register */
430  { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
431    { 0, { (const PTR) 0 } },
432    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
433/* u4: 4  bit unsigned immediate */
434  { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
435    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } },
436    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
437/* u4c: 4  bit unsigned immediate */
438  { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
439    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } },
440    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
441/* u8: 8  bit unsigned immediate */
442  { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
443    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } },
444    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
445/* i8: 8  bit unsigned immediate */
446  { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
447    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } },
448    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
449/* udisp6: 6  bit unsigned immediate */
450  { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
451    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } },
452    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
453/* disp8: 8  bit signed   immediate */
454  { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
455    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } },
456    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
457/* disp9: 9  bit signed   immediate */
458  { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
459    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } },
460    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
461/* disp10: 10 bit signed   immediate */
462  { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
463    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } },
464    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
465/* s10: 10 bit signed   immediate */
466  { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
467    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } },
468    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
469/* u10: 10 bit unsigned immediate */
470  { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
471    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } },
472    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
473/* i32: 32 bit immediate */
474  { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
475    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } },
476    { 0|A(HASH_PREFIX)|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
477/* m4: 4  bit negative immediate */
478  { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
479    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } },
480    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
481/* i20: 20 bit immediate */
482  { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
483    { 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } },
484    { 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
485/* dir8: 8  bit direct address */
486  { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
487    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } },
488    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
489/* dir9: 9  bit direct address */
490  { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
491    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } },
492    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
493/* dir10: 10 bit direct address */
494  { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
495    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } },
496    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
497/* label9: 9  bit pc relative address */
498  { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
499    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } },
500    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
501/* label12: 12 bit pc relative address */
502  { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
503    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } },
504    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
505/* reglist_low_ld: 8 bit low register mask for ldm */
506  { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
507    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } },
508    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
509/* reglist_hi_ld: 8 bit high register mask for ldm */
510  { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
511    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } },
512    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
513/* reglist_low_st: 8 bit low register mask for stm */
514  { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
515    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } },
516    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
517/* reglist_hi_st: 8 bit high register mask for stm */
518  { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
519    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } },
520    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
521/* cc: condition codes */
522  { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
523    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } },
524    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
525/* ccc: coprocessor calc */
526  { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
527    { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } },
528    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
529/* nbit: negative   bit */
530  { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
531    { 0, { (const PTR) 0 } },
532    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
533/* vbit: overflow   bit */
534  { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
535    { 0, { (const PTR) 0 } },
536    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
537/* zbit: zero       bit */
538  { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
539    { 0, { (const PTR) 0 } },
540    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
541/* cbit: carry      bit */
542  { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
543    { 0, { (const PTR) 0 } },
544    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
545/* ibit: interrupt  bit */
546  { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
547    { 0, { (const PTR) 0 } },
548    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
549/* sbit: stack      bit */
550  { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
551    { 0, { (const PTR) 0 } },
552    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
553/* tbit: trace trap bit */
554  { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
555    { 0, { (const PTR) 0 } },
556    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
557/* d0bit: division 0 bit */
558  { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
559    { 0, { (const PTR) 0 } },
560    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
561/* d1bit: division 1 bit */
562  { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
563    { 0, { (const PTR) 0 } },
564    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
565/* ccr: condition code bits */
566  { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
567    { 0, { (const PTR) 0 } },
568    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
569/* scr: system condition bits */
570  { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
571    { 0, { (const PTR) 0 } },
572    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
573/* ilm: interrupt level mask */
574  { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
575    { 0, { (const PTR) 0 } },
576    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
577/* sentinel */
578  { 0, 0, 0, 0, 0,
579    { 0, { (const PTR) 0 } },
580    { 0, { { { (1<<MACH_BASE), 0 } } } } }
581};
582
583#undef A
584
585
586/* The instruction table.  */
587
588#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
589#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
590#define A(a) (1 << CGEN_INSN_##a)
591#else
592#define A(a) (1 << CGEN_INSN_/**/a)
593#endif
594
595static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
596{
597  /* Special null first entry.
598     A `num' value of zero is thus invalid.
599     Also, the special `invalid' insn resides here.  */
600  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
601/* add $Rj,$Ri */
602  {
603    FR30_INSN_ADD, "add", "add", 16,
604    { 0, { { { (1<<MACH_BASE), 0 } } } }
605  },
606/* add $u4,$Ri */
607  {
608    FR30_INSN_ADDI, "addi", "add", 16,
609    { 0, { { { (1<<MACH_BASE), 0 } } } }
610  },
611/* add2 $m4,$Ri */
612  {
613    FR30_INSN_ADD2, "add2", "add2", 16,
614    { 0, { { { (1<<MACH_BASE), 0 } } } }
615  },
616/* addc $Rj,$Ri */
617  {
618    FR30_INSN_ADDC, "addc", "addc", 16,
619    { 0, { { { (1<<MACH_BASE), 0 } } } }
620  },
621/* addn $Rj,$Ri */
622  {
623    FR30_INSN_ADDN, "addn", "addn", 16,
624    { 0, { { { (1<<MACH_BASE), 0 } } } }
625  },
626/* addn $u4,$Ri */
627  {
628    FR30_INSN_ADDNI, "addni", "addn", 16,
629    { 0, { { { (1<<MACH_BASE), 0 } } } }
630  },
631/* addn2 $m4,$Ri */
632  {
633    FR30_INSN_ADDN2, "addn2", "addn2", 16,
634    { 0, { { { (1<<MACH_BASE), 0 } } } }
635  },
636/* sub $Rj,$Ri */
637  {
638    FR30_INSN_SUB, "sub", "sub", 16,
639    { 0, { { { (1<<MACH_BASE), 0 } } } }
640  },
641/* subc $Rj,$Ri */
642  {
643    FR30_INSN_SUBC, "subc", "subc", 16,
644    { 0, { { { (1<<MACH_BASE), 0 } } } }
645  },
646/* subn $Rj,$Ri */
647  {
648    FR30_INSN_SUBN, "subn", "subn", 16,
649    { 0, { { { (1<<MACH_BASE), 0 } } } }
650  },
651/* cmp $Rj,$Ri */
652  {
653    FR30_INSN_CMP, "cmp", "cmp", 16,
654    { 0, { { { (1<<MACH_BASE), 0 } } } }
655  },
656/* cmp $u4,$Ri */
657  {
658    FR30_INSN_CMPI, "cmpi", "cmp", 16,
659    { 0, { { { (1<<MACH_BASE), 0 } } } }
660  },
661/* cmp2 $m4,$Ri */
662  {
663    FR30_INSN_CMP2, "cmp2", "cmp2", 16,
664    { 0, { { { (1<<MACH_BASE), 0 } } } }
665  },
666/* and $Rj,$Ri */
667  {
668    FR30_INSN_AND, "and", "and", 16,
669    { 0, { { { (1<<MACH_BASE), 0 } } } }
670  },
671/* or $Rj,$Ri */
672  {
673    FR30_INSN_OR, "or", "or", 16,
674    { 0, { { { (1<<MACH_BASE), 0 } } } }
675  },
676/* eor $Rj,$Ri */
677  {
678    FR30_INSN_EOR, "eor", "eor", 16,
679    { 0, { { { (1<<MACH_BASE), 0 } } } }
680  },
681/* and $Rj,@$Ri */
682  {
683    FR30_INSN_ANDM, "andm", "and", 16,
684    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
685  },
686/* andh $Rj,@$Ri */
687  {
688    FR30_INSN_ANDH, "andh", "andh", 16,
689    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
690  },
691/* andb $Rj,@$Ri */
692  {
693    FR30_INSN_ANDB, "andb", "andb", 16,
694    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
695  },
696/* or $Rj,@$Ri */
697  {
698    FR30_INSN_ORM, "orm", "or", 16,
699    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
700  },
701/* orh $Rj,@$Ri */
702  {
703    FR30_INSN_ORH, "orh", "orh", 16,
704    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
705  },
706/* orb $Rj,@$Ri */
707  {
708    FR30_INSN_ORB, "orb", "orb", 16,
709    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
710  },
711/* eor $Rj,@$Ri */
712  {
713    FR30_INSN_EORM, "eorm", "eor", 16,
714    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
715  },
716/* eorh $Rj,@$Ri */
717  {
718    FR30_INSN_EORH, "eorh", "eorh", 16,
719    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
720  },
721/* eorb $Rj,@$Ri */
722  {
723    FR30_INSN_EORB, "eorb", "eorb", 16,
724    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
725  },
726/* bandl $u4,@$Ri */
727  {
728    FR30_INSN_BANDL, "bandl", "bandl", 16,
729    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
730  },
731/* borl $u4,@$Ri */
732  {
733    FR30_INSN_BORL, "borl", "borl", 16,
734    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
735  },
736/* beorl $u4,@$Ri */
737  {
738    FR30_INSN_BEORL, "beorl", "beorl", 16,
739    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
740  },
741/* bandh $u4,@$Ri */
742  {
743    FR30_INSN_BANDH, "bandh", "bandh", 16,
744    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
745  },
746/* borh $u4,@$Ri */
747  {
748    FR30_INSN_BORH, "borh", "borh", 16,
749    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
750  },
751/* beorh $u4,@$Ri */
752  {
753    FR30_INSN_BEORH, "beorh", "beorh", 16,
754    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
755  },
756/* btstl $u4,@$Ri */
757  {
758    FR30_INSN_BTSTL, "btstl", "btstl", 16,
759    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
760  },
761/* btsth $u4,@$Ri */
762  {
763    FR30_INSN_BTSTH, "btsth", "btsth", 16,
764    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
765  },
766/* mul $Rj,$Ri */
767  {
768    FR30_INSN_MUL, "mul", "mul", 16,
769    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
770  },
771/* mulu $Rj,$Ri */
772  {
773    FR30_INSN_MULU, "mulu", "mulu", 16,
774    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
775  },
776/* mulh $Rj,$Ri */
777  {
778    FR30_INSN_MULH, "mulh", "mulh", 16,
779    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
780  },
781/* muluh $Rj,$Ri */
782  {
783    FR30_INSN_MULUH, "muluh", "muluh", 16,
784    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
785  },
786/* div0s $Ri */
787  {
788    FR30_INSN_DIV0S, "div0s", "div0s", 16,
789    { 0, { { { (1<<MACH_BASE), 0 } } } }
790  },
791/* div0u $Ri */
792  {
793    FR30_INSN_DIV0U, "div0u", "div0u", 16,
794    { 0, { { { (1<<MACH_BASE), 0 } } } }
795  },
796/* div1 $Ri */
797  {
798    FR30_INSN_DIV1, "div1", "div1", 16,
799    { 0, { { { (1<<MACH_BASE), 0 } } } }
800  },
801/* div2 $Ri */
802  {
803    FR30_INSN_DIV2, "div2", "div2", 16,
804    { 0, { { { (1<<MACH_BASE), 0 } } } }
805  },
806/* div3 */
807  {
808    FR30_INSN_DIV3, "div3", "div3", 16,
809    { 0, { { { (1<<MACH_BASE), 0 } } } }
810  },
811/* div4s */
812  {
813    FR30_INSN_DIV4S, "div4s", "div4s", 16,
814    { 0, { { { (1<<MACH_BASE), 0 } } } }
815  },
816/* lsl $Rj,$Ri */
817  {
818    FR30_INSN_LSL, "lsl", "lsl", 16,
819    { 0, { { { (1<<MACH_BASE), 0 } } } }
820  },
821/* lsl $u4,$Ri */
822  {
823    FR30_INSN_LSLI, "lsli", "lsl", 16,
824    { 0, { { { (1<<MACH_BASE), 0 } } } }
825  },
826/* lsl2 $u4,$Ri */
827  {
828    FR30_INSN_LSL2, "lsl2", "lsl2", 16,
829    { 0, { { { (1<<MACH_BASE), 0 } } } }
830  },
831/* lsr $Rj,$Ri */
832  {
833    FR30_INSN_LSR, "lsr", "lsr", 16,
834    { 0, { { { (1<<MACH_BASE), 0 } } } }
835  },
836/* lsr $u4,$Ri */
837  {
838    FR30_INSN_LSRI, "lsri", "lsr", 16,
839    { 0, { { { (1<<MACH_BASE), 0 } } } }
840  },
841/* lsr2 $u4,$Ri */
842  {
843    FR30_INSN_LSR2, "lsr2", "lsr2", 16,
844    { 0, { { { (1<<MACH_BASE), 0 } } } }
845  },
846/* asr $Rj,$Ri */
847  {
848    FR30_INSN_ASR, "asr", "asr", 16,
849    { 0, { { { (1<<MACH_BASE), 0 } } } }
850  },
851/* asr $u4,$Ri */
852  {
853    FR30_INSN_ASRI, "asri", "asr", 16,
854    { 0, { { { (1<<MACH_BASE), 0 } } } }
855  },
856/* asr2 $u4,$Ri */
857  {
858    FR30_INSN_ASR2, "asr2", "asr2", 16,
859    { 0, { { { (1<<MACH_BASE), 0 } } } }
860  },
861/* ldi:8 $i8,$Ri */
862  {
863    FR30_INSN_LDI8, "ldi8", "ldi:8", 16,
864    { 0, { { { (1<<MACH_BASE), 0 } } } }
865  },
866/* ldi:20 $i20,$Ri */
867  {
868    FR30_INSN_LDI20, "ldi20", "ldi:20", 32,
869    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
870  },
871/* ldi:32 $i32,$Ri */
872  {
873    FR30_INSN_LDI32, "ldi32", "ldi:32", 48,
874    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
875  },
876/* ld @$Rj,$Ri */
877  {
878    FR30_INSN_LD, "ld", "ld", 16,
879    { 0, { { { (1<<MACH_BASE), 0 } } } }
880  },
881/* lduh @$Rj,$Ri */
882  {
883    FR30_INSN_LDUH, "lduh", "lduh", 16,
884    { 0, { { { (1<<MACH_BASE), 0 } } } }
885  },
886/* ldub @$Rj,$Ri */
887  {
888    FR30_INSN_LDUB, "ldub", "ldub", 16,
889    { 0, { { { (1<<MACH_BASE), 0 } } } }
890  },
891/* ld @($R13,$Rj),$Ri */
892  {
893    FR30_INSN_LDR13, "ldr13", "ld", 16,
894    { 0, { { { (1<<MACH_BASE), 0 } } } }
895  },
896/* lduh @($R13,$Rj),$Ri */
897  {
898    FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16,
899    { 0, { { { (1<<MACH_BASE), 0 } } } }
900  },
901/* ldub @($R13,$Rj),$Ri */
902  {
903    FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16,
904    { 0, { { { (1<<MACH_BASE), 0 } } } }
905  },
906/* ld @($R14,$disp10),$Ri */
907  {
908    FR30_INSN_LDR14, "ldr14", "ld", 16,
909    { 0, { { { (1<<MACH_BASE), 0 } } } }
910  },
911/* lduh @($R14,$disp9),$Ri */
912  {
913    FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16,
914    { 0, { { { (1<<MACH_BASE), 0 } } } }
915  },
916/* ldub @($R14,$disp8),$Ri */
917  {
918    FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16,
919    { 0, { { { (1<<MACH_BASE), 0 } } } }
920  },
921/* ld @($R15,$udisp6),$Ri */
922  {
923    FR30_INSN_LDR15, "ldr15", "ld", 16,
924    { 0, { { { (1<<MACH_BASE), 0 } } } }
925  },
926/* ld @$R15+,$Ri */
927  {
928    FR30_INSN_LDR15GR, "ldr15gr", "ld", 16,
929    { 0, { { { (1<<MACH_BASE), 0 } } } }
930  },
931/* ld @$R15+,$Rs2 */
932  {
933    FR30_INSN_LDR15DR, "ldr15dr", "ld", 16,
934    { 0, { { { (1<<MACH_BASE), 0 } } } }
935  },
936/* ld @$R15+,$ps */
937  {
938    FR30_INSN_LDR15PS, "ldr15ps", "ld", 16,
939    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
940  },
941/* st $Ri,@$Rj */
942  {
943    FR30_INSN_ST, "st", "st", 16,
944    { 0, { { { (1<<MACH_BASE), 0 } } } }
945  },
946/* sth $Ri,@$Rj */
947  {
948    FR30_INSN_STH, "sth", "sth", 16,
949    { 0, { { { (1<<MACH_BASE), 0 } } } }
950  },
951/* stb $Ri,@$Rj */
952  {
953    FR30_INSN_STB, "stb", "stb", 16,
954    { 0, { { { (1<<MACH_BASE), 0 } } } }
955  },
956/* st $Ri,@($R13,$Rj) */
957  {
958    FR30_INSN_STR13, "str13", "st", 16,
959    { 0, { { { (1<<MACH_BASE), 0 } } } }
960  },
961/* sth $Ri,@($R13,$Rj) */
962  {
963    FR30_INSN_STR13H, "str13h", "sth", 16,
964    { 0, { { { (1<<MACH_BASE), 0 } } } }
965  },
966/* stb $Ri,@($R13,$Rj) */
967  {
968    FR30_INSN_STR13B, "str13b", "stb", 16,
969    { 0, { { { (1<<MACH_BASE), 0 } } } }
970  },
971/* st $Ri,@($R14,$disp10) */
972  {
973    FR30_INSN_STR14, "str14", "st", 16,
974    { 0, { { { (1<<MACH_BASE), 0 } } } }
975  },
976/* sth $Ri,@($R14,$disp9) */
977  {
978    FR30_INSN_STR14H, "str14h", "sth", 16,
979    { 0, { { { (1<<MACH_BASE), 0 } } } }
980  },
981/* stb $Ri,@($R14,$disp8) */
982  {
983    FR30_INSN_STR14B, "str14b", "stb", 16,
984    { 0, { { { (1<<MACH_BASE), 0 } } } }
985  },
986/* st $Ri,@($R15,$udisp6) */
987  {
988    FR30_INSN_STR15, "str15", "st", 16,
989    { 0, { { { (1<<MACH_BASE), 0 } } } }
990  },
991/* st $Ri,@-$R15 */
992  {
993    FR30_INSN_STR15GR, "str15gr", "st", 16,
994    { 0, { { { (1<<MACH_BASE), 0 } } } }
995  },
996/* st $Rs2,@-$R15 */
997  {
998    FR30_INSN_STR15DR, "str15dr", "st", 16,
999    { 0, { { { (1<<MACH_BASE), 0 } } } }
1000  },
1001/* st $ps,@-$R15 */
1002  {
1003    FR30_INSN_STR15PS, "str15ps", "st", 16,
1004    { 0, { { { (1<<MACH_BASE), 0 } } } }
1005  },
1006/* mov $Rj,$Ri */
1007  {
1008    FR30_INSN_MOV, "mov", "mov", 16,
1009    { 0, { { { (1<<MACH_BASE), 0 } } } }
1010  },
1011/* mov $Rs1,$Ri */
1012  {
1013    FR30_INSN_MOVDR, "movdr", "mov", 16,
1014    { 0, { { { (1<<MACH_BASE), 0 } } } }
1015  },
1016/* mov $ps,$Ri */
1017  {
1018    FR30_INSN_MOVPS, "movps", "mov", 16,
1019    { 0, { { { (1<<MACH_BASE), 0 } } } }
1020  },
1021/* mov $Ri,$Rs1 */
1022  {
1023    FR30_INSN_MOV2DR, "mov2dr", "mov", 16,
1024    { 0, { { { (1<<MACH_BASE), 0 } } } }
1025  },
1026/* mov $Ri,$ps */
1027  {
1028    FR30_INSN_MOV2PS, "mov2ps", "mov", 16,
1029    { 0, { { { (1<<MACH_BASE), 0 } } } }
1030  },
1031/* jmp @$Ri */
1032  {
1033    FR30_INSN_JMP, "jmp", "jmp", 16,
1034    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1035  },
1036/* jmp:d @$Ri */
1037  {
1038    FR30_INSN_JMPD, "jmpd", "jmp:d", 16,
1039    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1040  },
1041/* call @$Ri */
1042  {
1043    FR30_INSN_CALLR, "callr", "call", 16,
1044    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1045  },
1046/* call:d @$Ri */
1047  {
1048    FR30_INSN_CALLRD, "callrd", "call:d", 16,
1049    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1050  },
1051/* call $label12 */
1052  {
1053    FR30_INSN_CALL, "call", "call", 16,
1054    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1055  },
1056/* call:d $label12 */
1057  {
1058    FR30_INSN_CALLD, "calld", "call:d", 16,
1059    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1060  },
1061/* ret */
1062  {
1063    FR30_INSN_RET, "ret", "ret", 16,
1064    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1065  },
1066/* ret:d */
1067  {
1068    FR30_INSN_RET_D, "ret:d", "ret:d", 16,
1069    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1070  },
1071/* int $u8 */
1072  {
1073    FR30_INSN_INT, "int", "int", 16,
1074    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1075  },
1076/* inte */
1077  {
1078    FR30_INSN_INTE, "inte", "inte", 16,
1079    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1080  },
1081/* reti */
1082  {
1083    FR30_INSN_RETI, "reti", "reti", 16,
1084    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1085  },
1086/* bra:d $label9 */
1087  {
1088    FR30_INSN_BRAD, "brad", "bra:d", 16,
1089    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1090  },
1091/* bra $label9 */
1092  {
1093    FR30_INSN_BRA, "bra", "bra", 16,
1094    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1095  },
1096/* bno:d $label9 */
1097  {
1098    FR30_INSN_BNOD, "bnod", "bno:d", 16,
1099    { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1100  },
1101/* bno $label9 */
1102  {
1103    FR30_INSN_BNO, "bno", "bno", 16,
1104    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1105  },
1106/* beq:d $label9 */
1107  {
1108    FR30_INSN_BEQD, "beqd", "beq:d", 16,
1109    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1110  },
1111/* beq $label9 */
1112  {
1113    FR30_INSN_BEQ, "beq", "beq", 16,
1114    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1115  },
1116/* bne:d $label9 */
1117  {
1118    FR30_INSN_BNED, "bned", "bne:d", 16,
1119    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1120  },
1121/* bne $label9 */
1122  {
1123    FR30_INSN_BNE, "bne", "bne", 16,
1124    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1125  },
1126/* bc:d $label9 */
1127  {
1128    FR30_INSN_BCD, "bcd", "bc:d", 16,
1129    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1130  },
1131/* bc $label9 */
1132  {
1133    FR30_INSN_BC, "bc", "bc", 16,
1134    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1135  },
1136/* bnc:d $label9 */
1137  {
1138    FR30_INSN_BNCD, "bncd", "bnc:d", 16,
1139    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1140  },
1141/* bnc $label9 */
1142  {
1143    FR30_INSN_BNC, "bnc", "bnc", 16,
1144    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1145  },
1146/* bn:d $label9 */
1147  {
1148    FR30_INSN_BND, "bnd", "bn:d", 16,
1149    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1150  },
1151/* bn $label9 */
1152  {
1153    FR30_INSN_BN, "bn", "bn", 16,
1154    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1155  },
1156/* bp:d $label9 */
1157  {
1158    FR30_INSN_BPD, "bpd", "bp:d", 16,
1159    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1160  },
1161/* bp $label9 */
1162  {
1163    FR30_INSN_BP, "bp", "bp", 16,
1164    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1165  },
1166/* bv:d $label9 */
1167  {
1168    FR30_INSN_BVD, "bvd", "bv:d", 16,
1169    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1170  },
1171/* bv $label9 */
1172  {
1173    FR30_INSN_BV, "bv", "bv", 16,
1174    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1175  },
1176/* bnv:d $label9 */
1177  {
1178    FR30_INSN_BNVD, "bnvd", "bnv:d", 16,
1179    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1180  },
1181/* bnv $label9 */
1182  {
1183    FR30_INSN_BNV, "bnv", "bnv", 16,
1184    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1185  },
1186/* blt:d $label9 */
1187  {
1188    FR30_INSN_BLTD, "bltd", "blt:d", 16,
1189    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1190  },
1191/* blt $label9 */
1192  {
1193    FR30_INSN_BLT, "blt", "blt", 16,
1194    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1195  },
1196/* bge:d $label9 */
1197  {
1198    FR30_INSN_BGED, "bged", "bge:d", 16,
1199    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1200  },
1201/* bge $label9 */
1202  {
1203    FR30_INSN_BGE, "bge", "bge", 16,
1204    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1205  },
1206/* ble:d $label9 */
1207  {
1208    FR30_INSN_BLED, "bled", "ble:d", 16,
1209    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1210  },
1211/* ble $label9 */
1212  {
1213    FR30_INSN_BLE, "ble", "ble", 16,
1214    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1215  },
1216/* bgt:d $label9 */
1217  {
1218    FR30_INSN_BGTD, "bgtd", "bgt:d", 16,
1219    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1220  },
1221/* bgt $label9 */
1222  {
1223    FR30_INSN_BGT, "bgt", "bgt", 16,
1224    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1225  },
1226/* bls:d $label9 */
1227  {
1228    FR30_INSN_BLSD, "blsd", "bls:d", 16,
1229    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1230  },
1231/* bls $label9 */
1232  {
1233    FR30_INSN_BLS, "bls", "bls", 16,
1234    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1235  },
1236/* bhi:d $label9 */
1237  {
1238    FR30_INSN_BHID, "bhid", "bhi:d", 16,
1239    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1240  },
1241/* bhi $label9 */
1242  {
1243    FR30_INSN_BHI, "bhi", "bhi", 16,
1244    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1245  },
1246/* dmov $R13,@$dir10 */
1247  {
1248    FR30_INSN_DMOVR13, "dmovr13", "dmov", 16,
1249    { 0, { { { (1<<MACH_BASE), 0 } } } }
1250  },
1251/* dmovh $R13,@$dir9 */
1252  {
1253    FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", 16,
1254    { 0, { { { (1<<MACH_BASE), 0 } } } }
1255  },
1256/* dmovb $R13,@$dir8 */
1257  {
1258    FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", 16,
1259    { 0, { { { (1<<MACH_BASE), 0 } } } }
1260  },
1261/* dmov @$R13+,@$dir10 */
1262  {
1263    FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", 16,
1264    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1265  },
1266/* dmovh @$R13+,@$dir9 */
1267  {
1268    FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", 16,
1269    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1270  },
1271/* dmovb @$R13+,@$dir8 */
1272  {
1273    FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", 16,
1274    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1275  },
1276/* dmov @$R15+,@$dir10 */
1277  {
1278    FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", 16,
1279    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1280  },
1281/* dmov @$dir10,$R13 */
1282  {
1283    FR30_INSN_DMOV2R13, "dmov2r13", "dmov", 16,
1284    { 0, { { { (1<<MACH_BASE), 0 } } } }
1285  },
1286/* dmovh @$dir9,$R13 */
1287  {
1288    FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", 16,
1289    { 0, { { { (1<<MACH_BASE), 0 } } } }
1290  },
1291/* dmovb @$dir8,$R13 */
1292  {
1293    FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", 16,
1294    { 0, { { { (1<<MACH_BASE), 0 } } } }
1295  },
1296/* dmov @$dir10,@$R13+ */
1297  {
1298    FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", 16,
1299    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1300  },
1301/* dmovh @$dir9,@$R13+ */
1302  {
1303    FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", 16,
1304    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1305  },
1306/* dmovb @$dir8,@$R13+ */
1307  {
1308    FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", 16,
1309    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1310  },
1311/* dmov @$dir10,@-$R15 */
1312  {
1313    FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", 16,
1314    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1315  },
1316/* ldres @$Ri+,$u4 */
1317  {
1318    FR30_INSN_LDRES, "ldres", "ldres", 16,
1319    { 0, { { { (1<<MACH_BASE), 0 } } } }
1320  },
1321/* stres $u4,@$Ri+ */
1322  {
1323    FR30_INSN_STRES, "stres", "stres", 16,
1324    { 0, { { { (1<<MACH_BASE), 0 } } } }
1325  },
1326/* copop $u4c,$ccc,$CRj,$CRi */
1327  {
1328    FR30_INSN_COPOP, "copop", "copop", 32,
1329    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1330  },
1331/* copld $u4c,$ccc,$Rjc,$CRi */
1332  {
1333    FR30_INSN_COPLD, "copld", "copld", 32,
1334    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1335  },
1336/* copst $u4c,$ccc,$CRj,$Ric */
1337  {
1338    FR30_INSN_COPST, "copst", "copst", 32,
1339    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1340  },
1341/* copsv $u4c,$ccc,$CRj,$Ric */
1342  {
1343    FR30_INSN_COPSV, "copsv", "copsv", 32,
1344    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1345  },
1346/* nop */
1347  {
1348    FR30_INSN_NOP, "nop", "nop", 16,
1349    { 0, { { { (1<<MACH_BASE), 0 } } } }
1350  },
1351/* andccr $u8 */
1352  {
1353    FR30_INSN_ANDCCR, "andccr", "andccr", 16,
1354    { 0, { { { (1<<MACH_BASE), 0 } } } }
1355  },
1356/* orccr $u8 */
1357  {
1358    FR30_INSN_ORCCR, "orccr", "orccr", 16,
1359    { 0, { { { (1<<MACH_BASE), 0 } } } }
1360  },
1361/* stilm $u8 */
1362  {
1363    FR30_INSN_STILM, "stilm", "stilm", 16,
1364    { 0, { { { (1<<MACH_BASE), 0 } } } }
1365  },
1366/* addsp $s10 */
1367  {
1368    FR30_INSN_ADDSP, "addsp", "addsp", 16,
1369    { 0, { { { (1<<MACH_BASE), 0 } } } }
1370  },
1371/* extsb $Ri */
1372  {
1373    FR30_INSN_EXTSB, "extsb", "extsb", 16,
1374    { 0, { { { (1<<MACH_BASE), 0 } } } }
1375  },
1376/* extub $Ri */
1377  {
1378    FR30_INSN_EXTUB, "extub", "extub", 16,
1379    { 0, { { { (1<<MACH_BASE), 0 } } } }
1380  },
1381/* extsh $Ri */
1382  {
1383    FR30_INSN_EXTSH, "extsh", "extsh", 16,
1384    { 0, { { { (1<<MACH_BASE), 0 } } } }
1385  },
1386/* extuh $Ri */
1387  {
1388    FR30_INSN_EXTUH, "extuh", "extuh", 16,
1389    { 0, { { { (1<<MACH_BASE), 0 } } } }
1390  },
1391/* ldm0 ($reglist_low_ld) */
1392  {
1393    FR30_INSN_LDM0, "ldm0", "ldm0", 16,
1394    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1395  },
1396/* ldm1 ($reglist_hi_ld) */
1397  {
1398    FR30_INSN_LDM1, "ldm1", "ldm1", 16,
1399    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1400  },
1401/* stm0 ($reglist_low_st) */
1402  {
1403    FR30_INSN_STM0, "stm0", "stm0", 16,
1404    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1405  },
1406/* stm1 ($reglist_hi_st) */
1407  {
1408    FR30_INSN_STM1, "stm1", "stm1", 16,
1409    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1410  },
1411/* enter $u10 */
1412  {
1413    FR30_INSN_ENTER, "enter", "enter", 16,
1414    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1415  },
1416/* leave */
1417  {
1418    FR30_INSN_LEAVE, "leave", "leave", 16,
1419    { 0, { { { (1<<MACH_BASE), 0 } } } }
1420  },
1421/* xchb @$Rj,$Ri */
1422  {
1423    FR30_INSN_XCHB, "xchb", "xchb", 16,
1424    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1425  },
1426};
1427
1428#undef OP
1429#undef A
1430
1431/* Initialize anything needed to be done once, before any cpu_open call.  */
1432
1433static void
1434init_tables (void)
1435{
1436}
1437
1438static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1439static void build_hw_table      (CGEN_CPU_TABLE *);
1440static void build_ifield_table  (CGEN_CPU_TABLE *);
1441static void build_operand_table (CGEN_CPU_TABLE *);
1442static void build_insn_table    (CGEN_CPU_TABLE *);
1443static void fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1444
1445/* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name.  */
1446
1447static const CGEN_MACH *
1448lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1449{
1450  while (table->name)
1451    {
1452      if (strcmp (name, table->bfd_name) == 0)
1453	return table;
1454      ++table;
1455    }
1456  abort ();
1457}
1458
1459/* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1460
1461static void
1462build_hw_table (CGEN_CPU_TABLE *cd)
1463{
1464  int i;
1465  int machs = cd->machs;
1466  const CGEN_HW_ENTRY *init = & fr30_cgen_hw_table[0];
1467  /* MAX_HW is only an upper bound on the number of selected entries.
1468     However each entry is indexed by it's enum so there can be holes in
1469     the table.  */
1470  const CGEN_HW_ENTRY **selected =
1471    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1472
1473  cd->hw_table.init_entries = init;
1474  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1475  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1476  /* ??? For now we just use machs to determine which ones we want.  */
1477  for (i = 0; init[i].name != NULL; ++i)
1478    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1479	& machs)
1480      selected[init[i].type] = &init[i];
1481  cd->hw_table.entries = selected;
1482  cd->hw_table.num_entries = MAX_HW;
1483}
1484
1485/* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1486
1487static void
1488build_ifield_table (CGEN_CPU_TABLE *cd)
1489{
1490  cd->ifld_table = & fr30_cgen_ifld_table[0];
1491}
1492
1493/* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
1494
1495static void
1496build_operand_table (CGEN_CPU_TABLE *cd)
1497{
1498  int i;
1499  int machs = cd->machs;
1500  const CGEN_OPERAND *init = & fr30_cgen_operand_table[0];
1501  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1502     However each entry is indexed by it's enum so there can be holes in
1503     the table.  */
1504  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1505
1506  cd->operand_table.init_entries = init;
1507  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1508  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1509  /* ??? For now we just use mach to determine which ones we want.  */
1510  for (i = 0; init[i].name != NULL; ++i)
1511    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1512	& machs)
1513      selected[init[i].type] = &init[i];
1514  cd->operand_table.entries = selected;
1515  cd->operand_table.num_entries = MAX_OPERANDS;
1516}
1517
1518/* Subroutine of fr30_cgen_cpu_open to build the hardware table.
1519   ??? This could leave out insns not supported by the specified mach/isa,
1520   but that would cause errors like "foo only supported by bar" to become
1521   "unknown insn", so for now we include all insns and require the app to
1522   do the checking later.
1523   ??? On the other hand, parsing of such insns may require their hardware or
1524   operand elements to be in the table [which they mightn't be].  */
1525
1526static void
1527build_insn_table (CGEN_CPU_TABLE *cd)
1528{
1529  int i;
1530  const CGEN_IBASE *ib = & fr30_cgen_insn_table[0];
1531  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1532
1533  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1534  for (i = 0; i < MAX_INSNS; ++i)
1535    insns[i].base = &ib[i];
1536  cd->insn_table.init_entries = insns;
1537  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1538  cd->insn_table.num_init_entries = MAX_INSNS;
1539}
1540
1541/* Subroutine of fr30_cgen_cpu_open to rebuild the tables.  */
1542
1543static void
1544fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1545{
1546  int i;
1547  CGEN_BITSET *isas = cd->isas;
1548  unsigned int machs = cd->machs;
1549
1550  cd->int_insn_p = CGEN_INT_INSN_P;
1551
1552  /* Data derived from the isa spec.  */
1553#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1554  cd->default_insn_bitsize = UNSET;
1555  cd->base_insn_bitsize = UNSET;
1556  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
1557  cd->max_insn_bitsize = 0;
1558  for (i = 0; i < MAX_ISAS; ++i)
1559    if (cgen_bitset_contains (isas, i))
1560      {
1561	const CGEN_ISA *isa = & fr30_cgen_isa_table[i];
1562
1563	/* Default insn sizes of all selected isas must be
1564	   equal or we set the result to 0, meaning "unknown".  */
1565	if (cd->default_insn_bitsize == UNSET)
1566	  cd->default_insn_bitsize = isa->default_insn_bitsize;
1567	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1568	  ; /* This is ok.  */
1569	else
1570	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1571
1572	/* Base insn sizes of all selected isas must be equal
1573	   or we set the result to 0, meaning "unknown".  */
1574	if (cd->base_insn_bitsize == UNSET)
1575	  cd->base_insn_bitsize = isa->base_insn_bitsize;
1576	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1577	  ; /* This is ok.  */
1578	else
1579	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1580
1581	/* Set min,max insn sizes.  */
1582	if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1583	  cd->min_insn_bitsize = isa->min_insn_bitsize;
1584	if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1585	  cd->max_insn_bitsize = isa->max_insn_bitsize;
1586      }
1587
1588  /* Data derived from the mach spec.  */
1589  for (i = 0; i < MAX_MACHS; ++i)
1590    if (((1 << i) & machs) != 0)
1591      {
1592	const CGEN_MACH *mach = & fr30_cgen_mach_table[i];
1593
1594	if (mach->insn_chunk_bitsize != 0)
1595	{
1596	  if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1597	    {
1598	      fprintf (stderr, "fr30_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1599		       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1600	      abort ();
1601	    }
1602
1603 	  cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1604	}
1605      }
1606
1607  /* Determine which hw elements are used by MACH.  */
1608  build_hw_table (cd);
1609
1610  /* Build the ifield table.  */
1611  build_ifield_table (cd);
1612
1613  /* Determine which operands are used by MACH/ISA.  */
1614  build_operand_table (cd);
1615
1616  /* Build the instruction table.  */
1617  build_insn_table (cd);
1618}
1619
1620/* Initialize a cpu table and return a descriptor.
1621   It's much like opening a file, and must be the first function called.
1622   The arguments are a set of (type/value) pairs, terminated with
1623   CGEN_CPU_OPEN_END.
1624
1625   Currently supported values:
1626   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1627   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1628   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1629   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1630   CGEN_CPU_OPEN_END:     terminates arguments
1631
1632   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1633   precluded.
1634
1635   ??? We only support ISO C stdargs here, not K&R.
1636   Laziness, plus experiment to see if anything requires K&R - eventually
1637   K&R will no longer be supported - e.g. GDB is currently trying this.  */
1638
1639CGEN_CPU_DESC
1640fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1641{
1642  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1643  static int init_p;
1644  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
1645  unsigned int machs = 0; /* 0 = "unspecified" */
1646  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1647  va_list ap;
1648
1649  if (! init_p)
1650    {
1651      init_tables ();
1652      init_p = 1;
1653    }
1654
1655  memset (cd, 0, sizeof (*cd));
1656
1657  va_start (ap, arg_type);
1658  while (arg_type != CGEN_CPU_OPEN_END)
1659    {
1660      switch (arg_type)
1661	{
1662	case CGEN_CPU_OPEN_ISAS :
1663	  isas = va_arg (ap, CGEN_BITSET *);
1664	  break;
1665	case CGEN_CPU_OPEN_MACHS :
1666	  machs = va_arg (ap, unsigned int);
1667	  break;
1668	case CGEN_CPU_OPEN_BFDMACH :
1669	  {
1670	    const char *name = va_arg (ap, const char *);
1671	    const CGEN_MACH *mach =
1672	      lookup_mach_via_bfd_name (fr30_cgen_mach_table, name);
1673
1674	    machs |= 1 << mach->num;
1675	    break;
1676	  }
1677	case CGEN_CPU_OPEN_ENDIAN :
1678	  endian = va_arg (ap, enum cgen_endian);
1679	  break;
1680	default :
1681	  fprintf (stderr, "fr30_cgen_cpu_open: unsupported argument `%d'\n",
1682		   arg_type);
1683	  abort (); /* ??? return NULL? */
1684	}
1685      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1686    }
1687  va_end (ap);
1688
1689  /* Mach unspecified means "all".  */
1690  if (machs == 0)
1691    machs = (1 << MAX_MACHS) - 1;
1692  /* Base mach is always selected.  */
1693  machs |= 1;
1694  if (endian == CGEN_ENDIAN_UNKNOWN)
1695    {
1696      /* ??? If target has only one, could have a default.  */
1697      fprintf (stderr, "fr30_cgen_cpu_open: no endianness specified\n");
1698      abort ();
1699    }
1700
1701  cd->isas = cgen_bitset_copy (isas);
1702  cd->machs = machs;
1703  cd->endian = endian;
1704  /* FIXME: for the sparc case we can determine insn-endianness statically.
1705     The worry here is where both data and insn endian can be independently
1706     chosen, in which case this function will need another argument.
1707     Actually, will want to allow for more arguments in the future anyway.  */
1708  cd->insn_endian = endian;
1709
1710  /* Table (re)builder.  */
1711  cd->rebuild_tables = fr30_cgen_rebuild_tables;
1712  fr30_cgen_rebuild_tables (cd);
1713
1714  /* Default to not allowing signed overflow.  */
1715  cd->signed_overflow_ok_p = 0;
1716
1717  return (CGEN_CPU_DESC) cd;
1718}
1719
1720/* Cover fn to fr30_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1721   MACH_NAME is the bfd name of the mach.  */
1722
1723CGEN_CPU_DESC
1724fr30_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1725{
1726  return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1727			       CGEN_CPU_OPEN_ENDIAN, endian,
1728			       CGEN_CPU_OPEN_END);
1729}
1730
1731/* Close a cpu table.
1732   ??? This can live in a machine independent file, but there's currently
1733   no place to put this file (there's no libcgen).  libopcodes is the wrong
1734   place as some simulator ports use this but they don't use libopcodes.  */
1735
1736void
1737fr30_cgen_cpu_close (CGEN_CPU_DESC cd)
1738{
1739  unsigned int i;
1740  const CGEN_INSN *insns;
1741
1742  if (cd->macro_insn_table.init_entries)
1743    {
1744      insns = cd->macro_insn_table.init_entries;
1745      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1746	if (CGEN_INSN_RX ((insns)))
1747	  regfree (CGEN_INSN_RX (insns));
1748    }
1749
1750  if (cd->insn_table.init_entries)
1751    {
1752      insns = cd->insn_table.init_entries;
1753      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1754	if (CGEN_INSN_RX (insns))
1755	  regfree (CGEN_INSN_RX (insns));
1756    }
1757
1758  if (cd->macro_insn_table.init_entries)
1759    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1760
1761  if (cd->insn_table.init_entries)
1762    free ((CGEN_INSN *) cd->insn_table.init_entries);
1763
1764  if (cd->hw_table.entries)
1765    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1766
1767  if (cd->operand_table.entries)
1768    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1769
1770  free (cd);
1771}
1772
1773