1 2.EXTERN MY_LABEL2; 3.section .text; 4 5// 6//14 VECTOR OPERATIONS 7// 8 9//Dreg_hi = Dreg_lo = SIGN ( Dreg_hi ) * Dreg_hi + SIGN ( Dreg_lo ) * Dreg_lo ; /* (b) */ 10 11r7.h=r7.l=sign(r2.h)*r3.h+sign(r2.l)*r3.l ; 12r0.h=r0.l=sign(r1.h)*r2.h+sign(r1.l)*r2.l ; 13r3.h=r3.l=sign(r4.h)*r5.h+sign(r4.l)*r5.l ; 14r6.h=r6.l=sign(r7.h)*r0.h+sign(r7.l)*r0.l ; 15r1.h=r1.l=sign(r2.h)*r3.h+sign(r2.l)*r3.l ; 16r4.h=r4.l=sign(r5.h)*r6.h+sign(r5.l)*r6.l ; 17r7.h=r7.l=sign(r0.h)*r1.h+sign(r0.l)*r1.l ; 18r2.h=r2.l=sign(r3.h)*r4.h+sign(r3.l)*r4.l ; 19 20//Dual 16-Bit Operation 21//Dreg = VIT_MAX ( Dreg , Dreg ) (ASL) ; /* shift history bits left (b) */ 22//Dreg = VIT_MAX ( Dreg , Dreg ) (ASR) ; /* shift history bits right (b) */ 23//Single 16-Bit Operation 24//Dreg_lo = VIT_MAX ( Dreg ) (ASL) ; /* shift history bits left (b) */ 25//Dreg_lo = VIT_MAX ( Dreg ) (ASR) ; /* shift history bits right (b) */ 26r5 = vit_max(r3, r2)(asl) ; /* shift left, dual operation */ 27r7 = vit_max (r1, r0) (asr) ; /* shift right, dual operation */ 28 29r0 = vit_max(r1, r2)(asl) ; /* shift left, dual operation */ 30r3 = vit_max (r4, r5) (asr) ; /* shift right, dual operation */ 31r6 = vit_max(r7, r0)(asl) ; /* shift left, dual operation */ 32r1 = vit_max (r2, r3) (asr) ; /* shift right, dual operation */ 33r4 = vit_max(r5, r6)(asl) ; /* shift left, dual operation */ 34r7 = vit_max (r0, r1) (asr) ; /* shift right, dual operation */ 35r2 = vit_max(r3, r4)(asl) ; /* shift left, dual operation */ 36r5 = vit_max (r6, r7) (asr) ; /* shift right, dual operation */ 37 38 39r3.l = vit_max (r1)(asl) ; /* shift left, single operation */ 40r3.l = vit_max (r1)(asr) ; /* shift right, single operation */ 41 42r0.l = vit_max (r1)(asl) ; /* shift left, single operation */ 43r2.l = vit_max (r3)(asr) ; /* shift right, single operation */ 44r4.l = vit_max (r5)(asl) ; /* shift left, single operation */ 45r6.l = vit_max (r7)(asr) ; /* shift right, single operation */ 46r1.l = vit_max (r2)(asl) ; /* shift left, single operation */ 47r3.l = vit_max (r4)(asr) ; /* shift right, single operation */ 48r5.l = vit_max (r6)(asl) ; /* shift left, single operation */ 49r7.l = vit_max (r0)(asr) ; /* shift right, single operation */ 50 51//Dreg = ABS Dreg (V) ; /* (b) */ 52r3 = abs r1 (v) ; 53 54r0 = abs r0 (v) ; 55r0 = abs r1 (v) ; 56r2 = abs r3 (v) ; 57r4 = abs r5 (v) ; 58r6 = abs r7 (v) ; 59r1 = abs r0 (v) ; 60r3 = abs r2 (v) ; 61r5 = abs r4 (v) ; 62r7 = abs r6 (v) ; 63 64//Dual 16-Bit Operations 65//Dreg = Dreg +|+ Dreg (opt_mode_0) ; /* add | add (b) */ 66r5=r3 +|+ r4 ; /* dual 16-bit operations, add|add */ 67 68r0=r1 +|+ r2 ; 69r3=r4 +|+ r5 ; 70r6=r7 +|+ r0 ; 71r1=r2 +|+ r3 ; 72r4=r3 +|+ r5 ; 73r6=r3 +|+ r7 ; 74 75r0=r1 +|+ r2 (S); 76r3=r4 +|+ r5 (S); 77r6=r7 +|+ r0 (S); 78r1=r2 +|+ r3 (S); 79r4=r3 +|+ r5 (S); 80r6=r3 +|+ r7 (S); 81 82r0=r1 +|+ r2 (CO); 83r3=r4 +|+ r5 (CO); 84r6=r7 +|+ r0 (CO) ; 85r1=r2 +|+ r3 (CO); 86r4=r3 +|+ r5 (CO); 87r6=r3 +|+ r7 (CO); 88 89r0=r1 +|+ r2 (SCO); 90r3=r4 +|+ r5 (SCO); 91r6=r7 +|+ r0 (SCO); 92r1=r2 +|+ r3 (SCO); 93r4=r3 +|+ r5 (SCO); 94r6=r3 +|+ r7 (SCO); 95 96//Dreg = Dreg �|+ Dreg (opt_mode_0) ; /* subtract | add (b) */ 97r6=r0 -|+ r1(s) ; /* same as above, subtract|add with saturation */ 98 99r0=r1 -|+ r2 ; 100r3=r4 -|+ r5 ; 101r6=r7 -|+ r0 ; 102r1=r2 -|+ r3 ; 103r4=r3 -|+ r5 ; 104r6=r3 -|+ r7 ; 105 106r0=r1 -|+ r2 (S); 107r3=r4 -|+ r5 (S); 108r6=r7 -|+ r0 (S); 109r1=r2 -|+ r3 (S); 110r4=r3 -|+ r5 (S); 111r6=r3 -|+ r7 (S); 112 113r0=r1 -|+ r2 (CO); 114r3=r4 -|+ r5 (CO); 115r6=r7 -|+ r0 (CO) ; 116r1=r2 -|+ r3 (CO); 117r4=r3 -|+ r5 (CO); 118r6=r3 -|+ r7 (CO); 119 120r0=r1 -|+ r2 (SCO); 121r3=r4 -|+ r5 (SCO); 122r6=r7 -|+ r0 (SCO); 123r1=r2 -|+ r3 (SCO); 124r4=r3 -|+ r5 (SCO); 125r6=r3 -|+ r7 (SCO); 126 127 128//Dreg = Dreg +|� Dreg (opt_mode_0) ; /* add | subtract (b) */ 129r0=r2 +|- r1(co) ; /* add|subtract with half-word results crossed over in the destination register */ 130 131r0=r1 +|- r2 ; 132r3=r4 +|- r5 ; 133r6=r7 +|- r0 ; 134r1=r2 +|- r3 ; 135r4=r3 +|- r5 ; 136r6=r3 +|- r7 ; 137 138r0=r1 +|- r2 (S); 139r3=r4 +|- r5 (S); 140r6=r7 +|- r0 (S); 141r1=r2 +|- r3 (S); 142r4=r3 +|- r5 (S); 143r6=r3 +|- r7 (S); 144 145r0=r1 +|- r2 (CO); 146r3=r4 +|- r5 (CO); 147r6=r7 +|- r0 (CO) ; 148r1=r2 +|- r3 (CO); 149r4=r3 +|- r5 (CO); 150r6=r3 +|- r7 (CO); 151 152r0=r1 +|- r2 (SCO); 153r3=r4 +|- r5 (SCO); 154r6=r7 +|- r0 (SCO); 155r1=r2 +|- r3 (SCO); 156r4=r3 +|- r5 (SCO); 157r6=r3 +|- r7 (SCO); 158 159//Dreg = Dreg �|� Dreg (opt_mode_0) ; /* subtract | subtract (b) */ 160r7=r3 -|- r6(sco) ; /* subtract|subtract with saturation and half-word results crossed over in the destination register */ 161 162r0=r1 -|- r2 ; 163r3=r4 -|- r5 ; 164r6=r7 -|- r0 ; 165r1=r2 -|- r3 ; 166r4=r3 -|- r5 ; 167r6=r3 -|- r7 ; 168 169r0=r1 -|- r2 (S); 170r3=r4 -|- r5 (S); 171r6=r7 -|- r0 (S); 172r1=r2 -|- r3 (S); 173r4=r3 -|- r5 (S); 174r6=r3 -|- r7 (S); 175 176r0=r1 -|- r2 (CO); 177r3=r4 -|- r5 (CO); 178r6=r7 -|- r0 (CO) ; 179r1=r2 -|- r3 (CO); 180r4=r3 -|- r5 (CO); 181r6=r3 -|- r7 (CO); 182 183r0=r1 -|- r2 (SCO); 184r3=r4 -|- r5 (SCO); 185r6=r7 -|- r0 (SCO); 186r1=r2 -|- r3 (SCO); 187r4=r3 -|- r5 (SCO); 188r6=r3 -|- r7 (SCO); 189 190//Quad 16-Bit Operations 191//Dreg = Dreg +|+ Dreg, Dreg = Dreg �|� Dreg (opt_mode_0,opt_mode_2) ; /* add | add, subtract | subtract; the set of source registers must be the same for each operation (b) */ 192r5=r3 +|+ r4, r7=r3-|-r4 ; /* quad 16-bit operations, add|add, subtract|subtract */ 193 194r0=r1 +|+ r2, r7=r1 -|- r2; 195r3=r4 +|+ r5, r6=r4 -|- r5; 196r6=r7 +|+ r0, r5=r7 -|- r0; 197r1=r2 +|+ r3, r4=r2 -|- r3; 198r4=r3 +|+ r5, r3=r3 -|- r5; 199r6=r3 +|+ r7, r2=r3 -|- r7; 200 201r0=r1 +|+ r2, r7=r1 -|- r2(S); 202r3=r4 +|+ r5, r6=r4 -|- r5(S); 203r6=r7 +|+ r0, r5=r7 -|- r0(S); 204r1=r2 +|+ r3, r4=r2 -|- r3(S); 205r4=r3 +|+ r5, r3=r3 -|- r5(S); 206r6=r3 +|+ r7, r2=r3 -|- r7(S); 207 208 209r0=r1 +|+ r2, r7=r1 -|- r2(CO); 210r3=r4 +|+ r5, r6=r4 -|- r5(CO); 211r6=r7 +|+ r0, r5=r7 -|- r0(CO); 212r1=r2 +|+ r3, r4=r2 -|- r3(CO); 213r4=r3 +|+ r5, r3=r3 -|- r5(CO); 214r6=r3 +|+ r7, r2=r3 -|- r7(CO); 215 216 217r0=r1 +|+ r2, r7=r1 -|- r2(SCO); 218r3=r4 +|+ r5, r6=r4 -|- r5(SCO); 219r6=r7 +|+ r0, r5=r7 -|- r0(SCO); 220r1=r2 +|+ r3, r4=r2 -|- r3(SCO); 221r4=r3 +|+ r5, r3=r3 -|- r5(SCO); 222r6=r3 +|+ r7, r2=r3 -|- r7(SCO); 223 224r0=r1 +|+ r2, r7=r1 -|- r2(ASR); 225r3=r4 +|+ r5, r6=r4 -|- r5(ASR); 226r6=r7 +|+ r0, r5=r7 -|- r0(ASR); 227r1=r2 +|+ r3, r4=r2 -|- r3(ASR); 228r4=r3 +|+ r5, r3=r3 -|- r5(ASR); 229r6=r3 +|+ r7, r2=r3 -|- r7(ASR); 230 231 232r0=r1 +|+ r2, r7=r1 -|- r2(ASL); 233r3=r4 +|+ r5, r6=r4 -|- r5(ASL); 234r6=r7 +|+ r0, r5=r7 -|- r0(ASL); 235r1=r2 +|+ r3, r4=r2 -|- r3(ASL); 236r4=r3 +|+ r5, r3=r3 -|- r5(ASL); 237r6=r3 +|+ r7, r2=r3 -|- r7(ASL); 238 239 240r0=r1 +|+ r2, r7=r1 -|- r2(S,ASR); 241r3=r4 +|+ r5, r6=r4 -|- r5(S,ASR); 242r6=r7 +|+ r0, r5=r7 -|- r0(S,ASR); 243r1=r2 +|+ r3, r4=r2 -|- r3(S,ASR); 244r4=r3 +|+ r5, r3=r3 -|- r5(S,ASR); 245r6=r3 +|+ r7, r2=r3 -|- r7(S,ASR); 246 247 248r0=r1 +|+ r2, r7=r1 -|- r2(CO,ASR); 249r3=r4 +|+ r5, r6=r4 -|- r5(CO,ASR); 250r6=r7 +|+ r0, r5=r7 -|- r0(CO,ASR); 251r1=r2 +|+ r3, r4=r2 -|- r3(CO,ASR); 252r4=r3 +|+ r5, r3=r3 -|- r5(CO,ASR); 253r6=r3 +|+ r7, r2=r3 -|- r7(CO,ASR); 254 255 256r0=r1 +|+ r2, r7=r1 -|- r2(SCO,ASR); 257r3=r4 +|+ r5, r6=r4 -|- r5(SCO,ASR); 258r6=r7 +|+ r0, r5=r7 -|- r0(SCO,ASR); 259r1=r2 +|+ r3, r4=r2 -|- r3(SCO,ASR); 260r4=r3 +|+ r5, r3=r3 -|- r5(SCO,ASR); 261r6=r3 +|+ r7, r2=r3 -|- r7(SCO,ASR); 262 263r0=r1 +|+ r2, r7=r1 -|- r2(S,ASL); 264r3=r4 +|+ r5, r6=r4 -|- r5(S,ASL); 265r6=r7 +|+ r0, r5=r7 -|- r0(S,ASL); 266r1=r2 +|+ r3, r4=r2 -|- r3(S,ASL); 267r4=r3 +|+ r5, r3=r3 -|- r5(S,ASL); 268r6=r3 +|+ r7, r2=r3 -|- r7(S,ASL); 269 270 271r0=r1 +|+ r2, r7=r1 -|- r2(CO,ASL); 272r3=r4 +|+ r5, r6=r4 -|- r5(CO,ASL); 273r6=r7 +|+ r0, r5=r7 -|- r0(CO,ASL); 274r1=r2 +|+ r3, r4=r2 -|- r3(CO,ASL); 275r4=r3 +|+ r5, r3=r3 -|- r5(CO,ASL); 276r6=r3 +|+ r7, r2=r3 -|- r7(CO,ASL); 277 278 279r0=r1 +|+ r2, r7=r1 -|- r2(SCO,ASL); 280r3=r4 +|+ r5, r6=r4 -|- r5(SCO,ASL); 281r6=r7 +|+ r0, r5=r7 -|- r0(SCO,ASL); 282r1=r2 +|+ r3, r4=r2 -|- r3(SCO,ASL); 283r4=r3 +|+ r5, r3=r3 -|- r5(SCO,ASL); 284r6=r3 +|+ r7, r2=r3 -|- r7(SCO,ASL); 285 286 287//Dreg = Dreg +|� Dreg, Dreg = Dreg �|+ Dreg (opt_mode_0,opt_mode_2) ; /* add | subtract, subtract | add; the set of source registers must be the same for each operation (b) */ 288r5=r3 +|- r4, r7=r3 -|+ r4 ; /* quad 16-bit operations, add|subtract, subtract|add */ 289 290r0=r1 +|- r2, r7=r1 -|+ r2; 291r3=r4 +|- r5, r6=r4 -|+ r5; 292r6=r7 +|- r0, r5=r7 -|+ r0; 293r1=r2 +|- r3, r4=r2 -|+ r3; 294r4=r3 +|- r5, r3=r3 -|+ r5; 295r6=r3 +|- r7, r2=r3 -|+ r7; 296 297r0=r1 +|- r2, r7=r1 -|+ r2(S); 298r3=r4 +|- r5, r6=r4 -|+ r5(S); 299r6=r7 +|- r0, r5=r7 -|+ r0(S); 300r1=r2 +|- r3, r4=r2 -|+ r3(S); 301r4=r3 +|- r5, r3=r3 -|+ r5(S); 302r6=r3 +|- r7, r2=r3 -|+ r7(S); 303 304 305r0=r1 +|- r2, r7=r1 -|+ r2(CO); 306r3=r4 +|- r5, r6=r4 -|+ r5(CO); 307r6=r7 +|- r0, r5=r7 -|+ r0(CO); 308r1=r2 +|- r3, r4=r2 -|+ r3(CO); 309r4=r3 +|- r5, r3=r3 -|+ r5(CO); 310r6=r3 +|- r7, r2=r3 -|+ r7(CO); 311 312 313r0=r1 +|- r2, r7=r1 -|+ r2(SCO); 314r3=r4 +|- r5, r6=r4 -|+ r5(SCO); 315r6=r7 +|- r0, r5=r7 -|+ r0(SCO); 316r1=r2 +|- r3, r4=r2 -|+ r3(SCO); 317r4=r3 +|- r5, r3=r3 -|+ r5(SCO); 318r6=r3 +|- r7, r2=r3 -|+ r7(SCO); 319 320r0=r1 +|- r2, r7=r1 -|+ r2(ASR); 321r3=r4 +|- r5, r6=r4 -|+ r5(ASR); 322r6=r7 +|- r0, r5=r7 -|+ r0(ASR); 323r1=r2 +|- r3, r4=r2 -|+ r3(ASR); 324r4=r3 +|- r5, r3=r3 -|+ r5(ASR); 325r6=r3 +|- r7, r2=r3 -|+ r7(ASR); 326 327 328r0=r1 +|- r2, r7=r1 -|+ r2(ASL); 329r3=r4 +|- r5, r6=r4 -|+ r5(ASL); 330r6=r7 +|- r0, r5=r7 -|+ r0(ASL); 331r1=r2 +|- r3, r4=r2 -|+ r3(ASL); 332r4=r3 +|- r5, r3=r3 -|+ r5(ASL); 333r6=r3 +|- r7, r2=r3 -|+ r7(ASL); 334 335 336r0=r1 +|- r2, r7=r1 -|+ r2(S,ASR); 337r3=r4 +|- r5, r6=r4 -|+ r5(S,ASR); 338r6=r7 +|- r0, r5=r7 -|+ r0(S,ASR); 339r1=r2 +|- r3, r4=r2 -|+ r3(S,ASR); 340r4=r3 +|- r5, r3=r3 -|+ r5(S,ASR); 341r6=r3 +|- r7, r2=r3 -|+ r7(S,ASR); 342 343 344r0=r1 +|- r2, r7=r1 -|+ r2(CO,ASR); 345r3=r4 +|- r5, r6=r4 -|+ r5(CO,ASR); 346r6=r7 +|- r0, r5=r7 -|+ r0(CO,ASR); 347r1=r2 +|- r3, r4=r2 -|+ r3(CO,ASR); 348r4=r3 +|- r5, r3=r3 -|+ r5(CO,ASR); 349r6=r3 +|- r7, r2=r3 -|+ r7(CO,ASR); 350 351 352r0=r1 +|- r2, r7=r1 -|+ r2(SCO,ASR); 353r3=r4 +|- r5, r6=r4 -|+ r5(SCO,ASR); 354r6=r7 +|- r0, r5=r7 -|+ r0(SCO,ASR); 355r1=r2 +|- r3, r4=r2 -|+ r3(SCO,ASR); 356r4=r3 +|- r5, r3=r3 -|+ r5(SCO,ASR); 357r6=r3 +|- r7, r2=r3 -|+ r7(SCO,ASR); 358 359r0=r1 +|- r2, r7=r1 -|+ r2(S,ASL); 360r3=r4 +|- r5, r6=r4 -|+ r5(S,ASL); 361r6=r7 +|- r0, r5=r7 -|+ r0(S,ASL); 362r1=r2 +|- r3, r4=r2 -|+ r3(S,ASL); 363r4=r3 +|- r5, r3=r3 -|+ r5(S,ASL); 364r6=r3 +|- r7, r2=r3 -|+ r7(S,ASL); 365 366 367r0=r1 +|- r2, r7=r1 -|+ r2(CO,ASL); 368r3=r4 +|- r5, r6=r4 -|+ r5(CO,ASL); 369r6=r7 +|- r0, r5=r7 -|+ r0(CO,ASL); 370r1=r2 +|- r3, r4=r2 -|+ r3(CO,ASL); 371r4=r3 +|- r5, r3=r3 -|+ r5(CO,ASL); 372r6=r3 +|- r7, r2=r3 -|+ r7(CO,ASL); 373 374 375r0=r1 +|- r2, r7=r1 -|+ r2(SCO,ASL); 376r3=r4 +|- r5, r6=r4 -|+ r5(SCO,ASL); 377r6=r7 +|- r0, r5=r7 -|+ r0(SCO,ASL); 378r1=r2 +|- r3, r4=r2 -|+ r3(SCO,ASL); 379r4=r3 +|- r5, r3=r3 -|+ r5(SCO,ASL); 380r6=r3 +|- r7, r2=r3 -|+ r7(SCO,ASL); 381 382 383 384//Dual 32-Bit Operations 385//Dreg = Dreg + Dreg, Dreg = Dreg - Dreg (opt_mode_1) ; /* add, subtract; the set of source registers must be the same for each operation (b) */ 386r2=r0+r1, r3=r0-r1 ; /* 32-bit operations */ 387 388r7=r0+r1, r0=r0-r1 ; /* 32-bit operations */ 389r6=r1+r2, r1=r1-r2 ; /* 32-bit operations */ 390r5=r2+r3, r2=r2-r3 ; /* 32-bit operations */ 391r4=r3+r4, r3=r3-r4 ; /* 32-bit operations */ 392r3=r4+r5, r4=r4-r5 ; /* 32-bit operations */ 393r2=r5+r6, r5=r5-r6 ; /* 32-bit operations */ 394r1=r6+r7, r6=r6-r7 ; /* 32-bit operations */ 395r0=r7+r0, r7=r7-r0 ; /* 32-bit operations */ 396 397r2=r0+r1, r3=r0-r1(s) ; /* dual 32-bit operations with saturation */ 398r7=r0+r1, r0=r0-r1 (s); /* 32-bit operations */ 399r6=r1+r2, r1=r1-r2 (s); /* 32-bit operations */ 400r5=r2+r3, r2=r2-r3 (s); /* 32-bit operations */ 401r4=r3+r4, r3=r3-r4(s) ; /* 32-bit operations */ 402r3=r4+r5, r4=r4-r5 (s); /* 32-bit operations */ 403r2=r5+r6, r5=r5-r6 (s); /* 32-bit operations */ 404r1=r6+r7, r6=r6-r7 (s); /* 32-bit operations */ 405r0=r7+r0, r7=r7-r0 (s); /* 32-bit operations */ 406 407 408 409//Dual 40-Bit Accumulator Operations 410//Dreg = A1 + A0, Dreg = A1 - A0 (opt_mode_1) ; /* add, subtract Accumulators; subtract A0 from A1 (b) */ 411r0=a1+a0, r1=a1-a0 ; 412r2=a1+a0, r3=a1-a0 ; 413r4=a1+a0, r5=a1-a0 ; 414r6=a1+a0, r7=a1-a0 ; 415r1=a1+a0, r0=a1-a0 ; 416r3=a1+a0, r2=a1-a0 ; 417r5=a1+a0, r4=a1-a0 ; 418 419r0=a1+a0, r1=a1-a0 (s); 420r2=a1+a0, r3=a1-a0 (s); 421r4=a1+a0, r5=a1-a0 (s); 422r6=a1+a0, r7=a1-a0 (s); 423r1=a1+a0, r0=a1-a0 (s); 424r3=a1+a0, r2=a1-a0 (s); 425r5=a1+a0, r4=a1-a0 (s); 426 427//Dreg = A0 + A1, Dreg = A0 - A1 (opt_mode_1) ; /* add, subtract Accumulators; subtract A1 from A0 (b) */ 428r4=a0+a1, r6=a0-a1(s); 429 430r0=a0+a1, r1=a0-a1 ; 431r2=a0+a1, r3=a0-a1 ; 432r4=a0+a1, r5=a0-a1 ; 433r6=a0+a1, r7=a0-a1 ; 434r1=a0+a1, r0=a0-a1 ; 435r3=a0+a1, r2=a0-a1 ; 436r5=a0+a1, r4=a0-a1 ; 437 438r0=a0+a1, r1=a0-a1 (s); 439r2=a0+a1, r3=a0-a1 (s); 440r4=a0+a1, r5=a0-a1 (s); 441r6=a0+a1, r7=a0-a1 (s); 442r1=a0+a1, r0=a0-a1 (s); 443r3=a0+a1, r2=a0-a1 (s); 444r5=a0+a1, r4=a0-a1 (s); 445 446//Constant Shift Magnitude 447//Dreg = Dreg >>> uimm4 (V) ; /* arithmetic shift right, immediate (b) */ 448R0 = R0 >>> 5(V); 449 450R0 = R1 >>> 5(V); 451R2 = R3 >>> 5(V); 452R4 = R5 >>> 5(V); 453R6 = R7 >>> 5(V); 454R1 = R0 >>> 5(V); 455R3 = R2 >>> 5(V); 456R5 = R4 >>> 5(V); 457R7 = R6 >>> 5(V); 458 459 460//Dreg = Dreg << uimm4 (V,S) ; /* arithmetic shift left, immediate with saturation (b) */ 461 462R0 = R1 << 5(V,S); 463R2 = R3 << 5(V,S); 464R4 = R5 << 5(V,S); 465R6 = R7 << 5(V,S); 466R1 = R0 << 5(V,S); 467R3 = R2 << 5(V,S); 468R5 = R4 << 5(V,S); 469R7 = R6 << 5(V,S); 470 471//Registered Shift Magnitude 472//Dreg = ASHIFT Dreg BY Dreg_lo (V) ; /* arithmetic shift (b) */ 473r2=ashift r7 by r5.l (v) ; 474 475R0 = ASHIFT R1 BY R2.L (V); 476R3 = ASHIFT R4 BY R5.L (V); 477R6 = ASHIFT R7 BY R0.L (V); 478R1 = ASHIFT R2 BY R3.L (V); 479R4 = ASHIFT R5 BY R6.L (V); 480R7 = ASHIFT R0 BY R1.L (V); 481R2 = ASHIFT R3 BY R4.L (V); 482R5 = ASHIFT R6 BY R7.L (V); 483 484 485//Dreg = ASHIFT Dreg BY Dreg_lo (V, S) ; /* arithmetic shift with saturation (b) */ 486R0 = ASHIFT R1 BY R2.L (V,S); 487R3 = ASHIFT R4 BY R5.L (V,S); 488R6 = ASHIFT R7 BY R0.L (V,S); 489R1 = ASHIFT R2 BY R3.L (V,S); 490R4 = ASHIFT R5 BY R6.L (V,S); 491R7 = ASHIFT R0 BY R1.L (V,S); 492R2 = ASHIFT R3 BY R4.L (V,S); 493R5 = ASHIFT R6 BY R7.L (V,S); 494 495//Constant Shift Magnitude 496//Dreg = Dreg >> uimm4 (V) ; /* logical shift right, immediate (b) */ 497R0 = R1 >> 5(V); 498R2 = R3 >> 5(V); 499R4 = R5 >> 5(V); 500R6 = R7 >> 5(V); 501R1 = R0 >> 5(V); 502R3 = R2 >> 5(V); 503R5 = R4 >> 5(V); 504R7 = R6 >> 5(V); 505 506//Dreg = Dreg << uimm4 (V) ; /* logical shift left, immediate (b) */ 507R0 = R1 << 5(V); 508R2 = R3 << 5(V); 509R4 = R5 << 5(V); 510R6 = R7 << 5(V); 511R1 = R0 << 5(V); 512R3 = R2 << 5(V); 513R5 = R4 << 5(V); 514R7 = R6 << 5(V); 515 516 517//Registered Shift Magnitude 518//Dreg = LSHIFT Dreg BY Dreg_lo (V) ; /* logical shift (b) */ 519 520R0 = LSHIFT R1 BY R2.L (V); 521R3 = LSHIFT R4 BY R5.L (V); 522R6 = LSHIFT R7 BY R0.L (V); 523R1 = LSHIFT R2 BY R3.L (V); 524R4 = LSHIFT R5 BY R6.L (V); 525R7 = LSHIFT R0 BY R1.L (V); 526R2 = LSHIFT R3 BY R4.L (V); 527R5 = LSHIFT R6 BY R7.L (V); 528 529//Dreg = MAX ( Dreg , Dreg ) (V) ; /* dual 16-bit operations (b) */ 530r7 = max (r1, r0) (v) ; 531 532R0 = MAX (R1, R2) (V); 533R3 = MAX (R4, R5) (V); 534R6 = MAX (R7, R0) (V); 535R1 = MAX (R2, R3) (V); 536R4 = MAX (R5, R6) (V); 537R7 = MAX (R0, R1) (V); 538R2 = MAX (R3, R4) (V); 539R5 = MAX (R6, R7) (V); 540 541//Dreg = MIN ( Dreg , Dreg ) (V) ; /* dual 16-bit operation (b) */ 542R0 = MIN (R1, R2) (V); 543R3 = MIN (R4, R5) (V); 544R6 = MIN (R7, R0) (V); 545R1 = MIN (R2, R3) (V); 546R4 = MIN (R5, R6) (V); 547R7 = MIN (R0, R1) (V); 548R2 = MIN (R3, R4) (V); 549R5 = MIN (R6, R7) (V); 550 551r2.h=r7.l*r6.h, r2.l=r7.h*r6.h ; 552/* simultaneous MAC0 and MAC1 execution, 16-bit results. Both 553results are signed fractions. */ 554r4.l=r1.l*r0.l, r4.h=r1.h*r0.h ; 555/* same as above. MAC order is arbitrary. */ 556r0.h=r3.h*r2.l (m), r0.l=r3.l*r2.l ; 557 558a1=r2.l*r3.h, a0=r2.h*r3.h ; 559/* both multiply signed fractions into separate Accumulators */ 560a0=r1.l*r0.l, a1+=r1.h*r0.h ; 561/* same as above, but sum result into A1. MAC order is arbitrary. 562*/ 563a1+=r3.h*r3.l, a0-=r3.h*r3.h ; 564/* sum product into A1, subtract product from A0 */ 565a1=r3.h*r2.l (m), a0+=r3.l*r2.l ; 566/* MAC1 multiplies a signed fraction in r3.h by an unsigned fraction 567in r2.l. MAC0 multiplies two signed fractions. */ 568a1=r7.h*r4.h (m), a0+=r7.l*r4.l (fu) ; 569/* MAC1 multiplies signed fraction by unsigned fraction. MAC0 570multiplies and accumulates two unsigned fractions. */ 571a1+=r3.h*r2.h, a0=r3.l*r2.l (is) ; 572/* both MACs perform signed integer multiplication */ 573a1=r6.h*r7.h, a0+=r6.l*r7.l (w32) ; 574/* both MACs multiply signed fractions, sign extended, and saturate 575both Accumulators at bit 31 */ 576r2.h=(a1=r7.l*r6.h), r2.l=(a0=r7.h*r6.h) ; /* simultaneous MAC0 577and MAC1 execution, both are signed fractions, both products load 578into the Accumulators,MAC1 into half-word registers. */ 579r4.l=(a0=r1.l*r0.l), r4.h=(a1+=r1.h*r0.h) ; /* same as above, 580but sum result into A1. ; MAC order is arbitrary. */ 581r7.h=(a1+=r6.h*r5.l), r7.l=(a0=r6.h*r5.h) ; /* sum into A1, 582subtract into A0 */ 583r0.h=(a1=r7.h*r4.l) (m), r0.l=(a0+=r7.l*r4.l) ; /* MAC1 multiplies 584a signed fraction by an unsigned fraction. MAC0 multiplies 585two signed fractions. */ 586r5.h=(a1=r3.h*r2.h) (m), r5.l=(a0+=r3.l*r2.l) (fu) ; /* MAC1 587multiplies signed fraction by unsigned fraction. MAC0 multiplies 588two unsigned fractions. */ 589r0.h=(a1+=r3.h*r2.h), r0.l=(a0=r3.l*r2.l) (is) ; /* both MACs 590perform signed integer multiplication. */ 591r5.h=(a1=r2.h*r1.h), a0+=r2.l*r1.l ; /* both MACs multiply 592signed fractions. MAC0 does not copy the accum result. */ 593r3.h=(a1=r2.h*r1.h) (m), a0=r2.l*r1.l ; /* MAC1 multiplies 594signed fraction by unsigned fraction and uses all 40 bits of A1. 595MAC0 multiplies two signed fractions. */ 596r3.h=a1, r3.l=(a0+=r0.l*r1.l) (s2rnd) ; /* MAC1 copies Accumulator 597to register half. MAC0 multiplies signed fractions. Both 598scale the result and round on the way to the destination register. 599*/ 600r0.l=(a0+=r7.l*r6.l), r0.h=(a1+=r7.h*r6.h) (iss2) ; /* both 601MACs process signed integer the way to the destination half-registers. 602*/ 603r3=(a1=r6.h*r7.h), r2=(a0=r6.l*r7.l) ; /* simultaneous MAC0 and 604MAC1 execution, both are signed fractions, both products load 605into the Accumulators */ 606r4=(a0=r6.l*r7.l), r5=(a1+=r6.h*r7.h) ; /* same as above, but 607sum result into A1. MAC order is arbitrary. */ 608r7=(a1+=r3.h*r5.h), r6=(a0-=r3.l*r5.l) ; /* sum into A1, subtract 609into A0 */ 610r1=(a1=r7.l*r4.l) (m), r0=(a0+=r7.h*r4.h) ; /* MAC1 multiplies 611a signed fraction by an unsigned fraction. MAC0 multiplies two 612signed fractions. */ 613r5=(a1=r3.h*r7.h) (m), r4=(a0+=r3.l*r7.l) (fu) ; /* MAC1 multiplies 614signed fraction by unsigned fraction. MAC0 multiplies two 615unsigned fractions. */ 616r1=(a1+=r3.h*r2.h), r0=(a0=r3.l*r2.l) (is) ; /* both MACs perform 617signed integer multiplication */ 618r5=(a1-=r6.h*r7.h), a0+=r6.l*r7.l ; /* both MACs multiply 619signed fractions. MAC0 does not copy the accum result */ 620r3=(a1=r6.h*r7.h) (m), a0-=r6.l*r7.l ; /* MAC1 multiplies 621signed fraction by unsigned fraction and uses all 40 bits of A1. 622MAC0 multiplies two signed fractions. */ 623r3=a1, r2=(a0+=r0.l*r1.l) (s2rnd) ; /* MAC1 moves Accumulator 624to register. MAC0 multiplies signed fractions. Both scale the 625result and round on the way to the destination register. */ 626r0=(a0+=r7.l*r6.l), r1=(a1+=r7.h*r6.h) (iss2) ; /* both MACs 627process signed integer operands and scale the result on the way 628to the destination registers. */ 629 630r5 =-r3 (v) ; /* R5.H becomes the negative of R3.H and R5.L 631becomes the negative of R3.L If r3 = 0x0004 7FFF the result is r5 632= 0xFFFC 8001 */ 633 634r3=pack(r4.l, r5.l) ; /* pack low / low half-words */ 635r1=pack(r6.l, r4.h) ; /* pack low / high half-words */ 636r0=pack(r2.h, r4.l) ; /* pack high / low half-words */ 637r5=pack(r7.h, r2.h) ; /* pack high / high half-words */ 638 639(r1,r0) = SEARCH R2 (LE) || R2=[P0++]; 640/* search for the last minimum in all but the 641last element of the array */ 642(r1,r0) = SEARCH R2 (LE); 643 644saa (r1:0, r3:2) || r0=[i0++] || r2=[i1++] ; 645saa (r1:0, r3:2)(r) || r1=[i0++] || r3=[i1++] ; 646mnop || r1 = [i0++] || r3 = [i1++] ; 647r7.h=r7.l=sign(r2.h)*r3.h + sign(r2.l)*r3.l || i0+=m3 || r0=[i0] 648; 649 650/* Add/subtract two vector values while incrementing an Ireg and 651loading a data register. */ 652R2 = R2 +|+ R4, R4 = R2 -|- R4 (ASR) || I0 += M0 (BREV) || R1 = [I0] ; 653/* Multiply and accumulate to Accumulator while loading a data 654register and storing a data register using an Ireg pointer. */ 655A1=R2.L*R1.L, A0=R2.H*R1.H || R2.H=W[I2++] || [I3++]=R3 ; 656/* Multiply and accumulate while loading two data registers. One 657load uses an Ireg pointer. */ 658A1+=R0.L*R2.H,A0+=R0.L*R2.L || R2.L=W[I2++] || R0=[I1--] ; 659R3.H=(A1+=R0.L*R1.H), R3.L=(A0+=R0.L*R1.L) || R0=[P0++] || R1=[I0] ; 660/* Pack two vector values while storing a data register using an 661Ireg pointer and loading another data register. */ 662R1=PACK(R1.H,R0.H) || [I0++]=R0 || R2.L=W[I2++] ; 663 664/* Multiply-Accumulate to a Data register while incrementing an 665Ireg. */ 666r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 ; 667/* which the assembler expands into: 668r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 || nop ; */ 669