1/* i386.c -- Assemble code for the Intel 80386 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004, 2005, 2006 4 Free Software Foundation, Inc. 5 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS; see the file COPYING. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 21 02110-1301, USA. */ 22 23/* Intel 80386 machine specific gas. 24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu). 25 x86_64 support by Jan Hubicka (jh@suse.cz) 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz) 27 Bugs & suggestions are completely welcome. This is free software. 28 Please help us make it better. */ 29 30#include "as.h" 31#include "safe-ctype.h" 32#include "subsegs.h" 33#include "dwarf2dbg.h" 34#include "dw2gencfi.h" 35#include "opcode/i386.h" 36#include "elf/x86-64.h" 37 38#ifndef REGISTER_WARNINGS 39#define REGISTER_WARNINGS 1 40#endif 41 42#ifndef INFER_ADDR_PREFIX 43#define INFER_ADDR_PREFIX 1 44#endif 45 46#ifndef SCALE1_WHEN_NO_INDEX 47/* Specifying a scale factor besides 1 when there is no index is 48 futile. eg. `mov (%ebx,2),%al' does exactly the same as 49 `mov (%ebx),%al'. To slavishly follow what the programmer 50 specified, set SCALE1_WHEN_NO_INDEX to 0. */ 51#define SCALE1_WHEN_NO_INDEX 1 52#endif 53 54#ifndef DEFAULT_ARCH 55#define DEFAULT_ARCH "i386" 56#endif 57 58#ifndef INLINE 59#if __GNUC__ >= 2 60#define INLINE __inline__ 61#else 62#define INLINE 63#endif 64#endif 65 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int)); 67static INLINE int fits_in_signed_byte PARAMS ((offsetT)); 68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT)); 69static INLINE int fits_in_unsigned_word PARAMS ((offsetT)); 70static INLINE int fits_in_signed_word PARAMS ((offsetT)); 71static INLINE int fits_in_unsigned_long PARAMS ((offsetT)); 72static INLINE int fits_in_signed_long PARAMS ((offsetT)); 73static int smallest_imm_type PARAMS ((offsetT)); 74static offsetT offset_in_range PARAMS ((offsetT, int)); 75static int add_prefix PARAMS ((unsigned int)); 76static void set_code_flag PARAMS ((int)); 77static void set_16bit_gcc_code_flag PARAMS ((int)); 78static void set_intel_syntax PARAMS ((int)); 79static void set_cpu_arch PARAMS ((int)); 80#ifdef TE_PE 81static void pe_directive_secrel PARAMS ((int)); 82#endif 83static void signed_cons PARAMS ((int)); 84static char *output_invalid PARAMS ((int c)); 85static int i386_operand PARAMS ((char *operand_string)); 86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); 87static const reg_entry *parse_register PARAMS ((char *reg_string, 88 char **end_op)); 89static char *parse_insn PARAMS ((char *, char *)); 90static char *parse_operands PARAMS ((char *, const char *)); 91static void swap_operands PARAMS ((void)); 92static void optimize_imm PARAMS ((void)); 93static void optimize_disp PARAMS ((void)); 94static int match_template PARAMS ((void)); 95static int check_string PARAMS ((void)); 96static int process_suffix PARAMS ((void)); 97static int check_byte_reg PARAMS ((void)); 98static int check_long_reg PARAMS ((void)); 99static int check_qword_reg PARAMS ((void)); 100static int check_word_reg PARAMS ((void)); 101static int finalize_imm PARAMS ((void)); 102static int process_operands PARAMS ((void)); 103static const seg_entry *build_modrm_byte PARAMS ((void)); 104static void output_insn PARAMS ((void)); 105static void output_branch PARAMS ((void)); 106static void output_jump PARAMS ((void)); 107static void output_interseg_jump PARAMS ((void)); 108static void output_imm PARAMS ((fragS *insn_start_frag, 109 offsetT insn_start_off)); 110static void output_disp PARAMS ((fragS *insn_start_frag, 111 offsetT insn_start_off)); 112#ifndef I386COFF 113static void s_bss PARAMS ((int)); 114#endif 115#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 116static void handle_large_common (int small ATTRIBUTE_UNUSED); 117#endif 118 119static const char *default_arch = DEFAULT_ARCH; 120 121/* 'md_assemble ()' gathers together information and puts it into a 122 i386_insn. */ 123 124union i386_op 125 { 126 expressionS *disps; 127 expressionS *imms; 128 const reg_entry *regs; 129 }; 130 131struct _i386_insn 132 { 133 /* TM holds the template for the insn were currently assembling. */ 134 template tm; 135 136 /* SUFFIX holds the instruction mnemonic suffix if given. 137 (e.g. 'l' for 'movl') */ 138 char suffix; 139 140 /* OPERANDS gives the number of given operands. */ 141 unsigned int operands; 142 143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number 144 of given register, displacement, memory operands and immediate 145 operands. */ 146 unsigned int reg_operands, disp_operands, mem_operands, imm_operands; 147 148 /* TYPES [i] is the type (see above #defines) which tells us how to 149 use OP[i] for the corresponding operand. */ 150 unsigned int types[MAX_OPERANDS]; 151 152 /* Displacement expression, immediate expression, or register for each 153 operand. */ 154 union i386_op op[MAX_OPERANDS]; 155 156 /* Flags for operands. */ 157 unsigned int flags[MAX_OPERANDS]; 158#define Operand_PCrel 1 159 160 /* Relocation type for operand */ 161 enum bfd_reloc_code_real reloc[MAX_OPERANDS]; 162 163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode 164 the base index byte below. */ 165 const reg_entry *base_reg; 166 const reg_entry *index_reg; 167 unsigned int log2_scale_factor; 168 169 /* SEG gives the seg_entries of this insn. They are zero unless 170 explicit segment overrides are given. */ 171 const seg_entry *seg[2]; 172 173 /* PREFIX holds all the given prefix opcodes (usually null). 174 PREFIXES is the number of prefix opcodes. */ 175 unsigned int prefixes; 176 unsigned char prefix[MAX_PREFIXES]; 177 178 /* RM and SIB are the modrm byte and the sib byte where the 179 addressing modes of this insn are encoded. */ 180 181 modrm_byte rm; 182 rex_byte rex; 183 sib_byte sib; 184 }; 185 186typedef struct _i386_insn i386_insn; 187 188/* List of chars besides those in app.c:symbol_chars that can start an 189 operand. Used to prevent the scrubber eating vital white-space. */ 190const char extra_symbol_chars[] = "*%-([" 191#ifdef LEX_AT 192 "@" 193#endif 194#ifdef LEX_QM 195 "?" 196#endif 197 ; 198 199#if (defined (TE_I386AIX) \ 200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ 201 && !defined (TE_GNU) \ 202 && !defined (TE_LINUX) \ 203 && !defined (TE_NETWARE) \ 204 && !defined (TE_FreeBSD) \ 205 && !defined (TE_NetBSD) \ 206 && !defined (TE_BeOS) \ 207 && !defined (TE_HAIKU))) 208/* This array holds the chars that always start a comment. If the 209 pre-processor is disabled, these aren't very useful. The option 210 --divide will remove '/' from this list. */ 211const char *i386_comment_chars = "#/"; 212#define SVR4_COMMENT_CHARS 1 213#define PREFIX_SEPARATOR '\\' 214 215#else 216const char *i386_comment_chars = "#"; 217#define PREFIX_SEPARATOR '/' 218#endif 219 220/* This array holds the chars that only start a comment at the beginning of 221 a line. If the line seems to have the form '# 123 filename' 222 .line and .file directives will appear in the pre-processed output. 223 Note that input_file.c hand checks for '#' at the beginning of the 224 first line of the input file. This is because the compiler outputs 225 #NO_APP at the beginning of its output. 226 Also note that comments started like this one will always work if 227 '/' isn't otherwise defined. */ 228const char line_comment_chars[] = "#/"; 229 230const char line_separator_chars[] = ";"; 231 232/* Chars that can be used to separate mant from exp in floating point 233 nums. */ 234const char EXP_CHARS[] = "eE"; 235 236/* Chars that mean this number is a floating point constant 237 As in 0f12.456 238 or 0d1.2345e12. */ 239const char FLT_CHARS[] = "fFdDxX"; 240 241/* Tables for lexical analysis. */ 242static char mnemonic_chars[256]; 243static char register_chars[256]; 244static char operand_chars[256]; 245static char identifier_chars[256]; 246static char digit_chars[256]; 247 248/* Lexical macros. */ 249#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) 250#define is_operand_char(x) (operand_chars[(unsigned char) x]) 251#define is_register_char(x) (register_chars[(unsigned char) x]) 252#define is_space_char(x) ((x) == ' ') 253#define is_identifier_char(x) (identifier_chars[(unsigned char) x]) 254#define is_digit_char(x) (digit_chars[(unsigned char) x]) 255 256/* All non-digit non-letter characters that may occur in an operand. */ 257static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; 258 259/* md_assemble() always leaves the strings it's passed unaltered. To 260 effect this we maintain a stack of saved characters that we've smashed 261 with '\0's (indicating end of strings for various sub-fields of the 262 assembler instruction). */ 263static char save_stack[32]; 264static char *save_stack_p; 265#define END_STRING_AND_SAVE(s) \ 266 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) 267#define RESTORE_END_STRING(s) \ 268 do { *(s) = *--save_stack_p; } while (0) 269 270/* The instruction we're assembling. */ 271static i386_insn i; 272 273/* Possible templates for current insn. */ 274static const templates *current_templates; 275 276/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ 277static expressionS disp_expressions[2], im_expressions[2]; 278 279/* Current operand we are working on. */ 280static int this_operand; 281 282/* We support four different modes. FLAG_CODE variable is used to distinguish 283 these. */ 284 285enum flag_code { 286 CODE_32BIT, 287 CODE_16BIT, 288 CODE_64BIT }; 289#define NUM_FLAG_CODE ((int) CODE_64BIT + 1) 290 291static enum flag_code flag_code; 292static unsigned int object_64bit; 293static int use_rela_relocations = 0; 294 295/* The names used to print error messages. */ 296static const char *flag_code_names[] = 297 { 298 "32", 299 "16", 300 "64" 301 }; 302 303/* 1 for intel syntax, 304 0 if att syntax. */ 305static int intel_syntax = 0; 306 307/* 1 if register prefix % not required. */ 308static int allow_naked_reg = 0; 309 310/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, 311 leave, push, and pop instructions so that gcc has the same stack 312 frame as in 32 bit mode. */ 313static char stackop_size = '\0'; 314 315/* Non-zero to optimize code alignment. */ 316int optimize_align_code = 1; 317 318/* Non-zero to quieten some warnings. */ 319static int quiet_warnings = 0; 320 321/* CPU name. */ 322static const char *cpu_arch_name = NULL; 323static const char *cpu_sub_arch_name = NULL; 324 325/* CPU feature flags. */ 326static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64; 327 328/* If set, conditional jumps are not automatically promoted to handle 329 larger than a byte offset. */ 330static unsigned int no_cond_jump_promotion = 0; 331 332/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ 333static symbolS *GOT_symbol; 334 335/* The dwarf2 return column, adjusted for 32 or 64 bit. */ 336unsigned int x86_dwarf2_return_column; 337 338/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 339int x86_cie_data_alignment; 340 341/* Interface to relax_segment. 342 There are 3 major relax states for 386 jump insns because the 343 different types of jumps add different sizes to frags when we're 344 figuring out what sort of jump to choose to reach a given label. */ 345 346/* Types. */ 347#define UNCOND_JUMP 0 348#define COND_JUMP 1 349#define COND_JUMP86 2 350 351/* Sizes. */ 352#define CODE16 1 353#define SMALL 0 354#define SMALL16 (SMALL | CODE16) 355#define BIG 2 356#define BIG16 (BIG | CODE16) 357 358#ifndef INLINE 359#ifdef __GNUC__ 360#define INLINE __inline__ 361#else 362#define INLINE 363#endif 364#endif 365 366#define ENCODE_RELAX_STATE(type, size) \ 367 ((relax_substateT) (((type) << 2) | (size))) 368#define TYPE_FROM_RELAX_STATE(s) \ 369 ((s) >> 2) 370#define DISP_SIZE_FROM_RELAX_STATE(s) \ 371 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) 372 373/* This table is used by relax_frag to promote short jumps to long 374 ones where necessary. SMALL (short) jumps may be promoted to BIG 375 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We 376 don't allow a short jump in a 32 bit code segment to be promoted to 377 a 16 bit offset jump because it's slower (requires data size 378 prefix), and doesn't work, unless the destination is in the bottom 379 64k of the code segment (The top 16 bits of eip are zeroed). */ 380 381const relax_typeS md_relax_table[] = 382{ 383 /* The fields are: 384 1) most positive reach of this state, 385 2) most negative reach of this state, 386 3) how many bytes this mode will have in the variable part of the frag 387 4) which index into the table to try if we can't fit into this one. */ 388 389 /* UNCOND_JUMP states. */ 390 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, 391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, 392 /* dword jmp adds 4 bytes to frag: 393 0 extra opcode bytes, 4 displacement bytes. */ 394 {0, 0, 4, 0}, 395 /* word jmp adds 2 byte2 to frag: 396 0 extra opcode bytes, 2 displacement bytes. */ 397 {0, 0, 2, 0}, 398 399 /* COND_JUMP states. */ 400 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, 401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, 402 /* dword conditionals adds 5 bytes to frag: 403 1 extra opcode byte, 4 displacement bytes. */ 404 {0, 0, 5, 0}, 405 /* word conditionals add 3 bytes to frag: 406 1 extra opcode byte, 2 displacement bytes. */ 407 {0, 0, 3, 0}, 408 409 /* COND_JUMP86 states. */ 410 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, 411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, 412 /* dword conditionals adds 5 bytes to frag: 413 1 extra opcode byte, 4 displacement bytes. */ 414 {0, 0, 5, 0}, 415 /* word conditionals add 4 bytes to frag: 416 1 displacement byte and a 3 byte long branch insn. */ 417 {0, 0, 4, 0} 418}; 419 420static const arch_entry cpu_arch[] = { 421 {"i8086", Cpu086 }, 422 {"i186", Cpu086|Cpu186 }, 423 {"i286", Cpu086|Cpu186|Cpu286 }, 424 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, 425 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, 426 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 }, 427 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 }, 428 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 }, 429 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 }, 430 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX }, 431 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE }, 432 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 }, 433 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI }, 434 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX }, 435 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow }, 436 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA }, 437 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 }, 438 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 }, 439 {".mmx", CpuMMX }, 440 {".sse", CpuMMX|CpuMMX2|CpuSSE }, 441 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 }, 442 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 }, 443 {".3dnow", CpuMMX|Cpu3dnow }, 444 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA }, 445 {".padlock", CpuPadLock }, 446 {".pacifica", CpuSVME }, 447 {".svme", CpuSVME }, 448 {NULL, 0 } 449}; 450 451const pseudo_typeS md_pseudo_table[] = 452{ 453#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) 454 {"align", s_align_bytes, 0}, 455#else 456 {"align", s_align_ptwo, 0}, 457#endif 458 {"arch", set_cpu_arch, 0}, 459#ifndef I386COFF 460 {"bss", s_bss, 0}, 461#endif 462 {"ffloat", float_cons, 'f'}, 463 {"dfloat", float_cons, 'd'}, 464 {"tfloat", float_cons, 'x'}, 465 {"value", cons, 2}, 466 {"slong", signed_cons, 4}, 467 {"noopt", s_ignore, 0}, 468 {"optim", s_ignore, 0}, 469 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, 470 {"code16", set_code_flag, CODE_16BIT}, 471 {"code32", set_code_flag, CODE_32BIT}, 472 {"code64", set_code_flag, CODE_64BIT}, 473 {"intel_syntax", set_intel_syntax, 1}, 474 {"att_syntax", set_intel_syntax, 0}, 475#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 476 {"largecomm", handle_large_common, 0}, 477#else 478 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0}, 479 {"loc", dwarf2_directive_loc, 0}, 480 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, 481#endif 482#ifdef TE_PE 483 {"secrel32", pe_directive_secrel, 0}, 484#endif 485 {0, 0, 0} 486}; 487 488/* For interface with expression (). */ 489extern char *input_line_pointer; 490 491/* Hash table for instruction mnemonic lookup. */ 492static struct hash_control *op_hash; 493 494/* Hash table for register lookup. */ 495static struct hash_control *reg_hash; 496 497void 498i386_align_code (fragP, count) 499 fragS *fragP; 500 int count; 501{ 502 /* Various efficient no-op patterns for aligning code labels. 503 Note: Don't try to assemble the instructions in the comments. 504 0L and 0w are not legal. */ 505 static const char f32_1[] = 506 {0x90}; /* nop */ 507 static const char f32_2[] = 508 {0x89,0xf6}; /* movl %esi,%esi */ 509 static const char f32_3[] = 510 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ 511 static const char f32_4[] = 512 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 513 static const char f32_5[] = 514 {0x90, /* nop */ 515 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 516 static const char f32_6[] = 517 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ 518 static const char f32_7[] = 519 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 520 static const char f32_8[] = 521 {0x90, /* nop */ 522 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 523 static const char f32_9[] = 524 {0x89,0xf6, /* movl %esi,%esi */ 525 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 526 static const char f32_10[] = 527 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ 528 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 529 static const char f32_11[] = 530 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ 531 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 532 static const char f32_12[] = 533 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 534 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ 535 static const char f32_13[] = 536 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 537 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 538 static const char f32_14[] = 539 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ 540 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 541 static const char f32_15[] = 542 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ 543 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; 544 static const char f16_3[] = 545 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ 546 static const char f16_4[] = 547 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 548 static const char f16_5[] = 549 {0x90, /* nop */ 550 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 551 static const char f16_6[] = 552 {0x89,0xf6, /* mov %si,%si */ 553 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 554 static const char f16_7[] = 555 {0x8d,0x74,0x00, /* lea 0(%si),%si */ 556 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 557 static const char f16_8[] = 558 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ 559 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 560 static const char *const f32_patt[] = { 561 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, 562 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 563 }; 564 static const char *const f16_patt[] = { 565 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, 566 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 567 }; 568 569 if (count <= 0 || count > 15) 570 return; 571 572 /* The recommended way to pad 64bit code is to use NOPs preceded by 573 maximally four 0x66 prefixes. Balance the size of nops. */ 574 if (flag_code == CODE_64BIT) 575 { 576 int i; 577 int nnops = (count + 3) / 4; 578 int len = count / nnops; 579 int remains = count - nnops * len; 580 int pos = 0; 581 582 for (i = 0; i < remains; i++) 583 { 584 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len); 585 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90; 586 pos += len + 1; 587 } 588 for (; i < nnops; i++) 589 { 590 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1); 591 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90; 592 pos += len; 593 } 594 } 595 else 596 if (flag_code == CODE_16BIT) 597 { 598 memcpy (fragP->fr_literal + fragP->fr_fix, 599 f16_patt[count - 1], count); 600 if (count > 8) 601 /* Adjust jump offset. */ 602 fragP->fr_literal[fragP->fr_fix + 1] = count - 2; 603 } 604 else 605 memcpy (fragP->fr_literal + fragP->fr_fix, 606 f32_patt[count - 1], count); 607 fragP->fr_var = count; 608} 609 610static INLINE unsigned int 611mode_from_disp_size (t) 612 unsigned int t; 613{ 614 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0; 615} 616 617static INLINE int 618fits_in_signed_byte (num) 619 offsetT num; 620{ 621 return (num >= -128) && (num <= 127); 622} 623 624static INLINE int 625fits_in_unsigned_byte (num) 626 offsetT num; 627{ 628 return (num & 0xff) == num; 629} 630 631static INLINE int 632fits_in_unsigned_word (num) 633 offsetT num; 634{ 635 return (num & 0xffff) == num; 636} 637 638static INLINE int 639fits_in_signed_word (num) 640 offsetT num; 641{ 642 return (-32768 <= num) && (num <= 32767); 643} 644static INLINE int 645fits_in_signed_long (num) 646 offsetT num ATTRIBUTE_UNUSED; 647{ 648#ifndef BFD64 649 return 1; 650#else 651 return (!(((offsetT) -1 << 31) & num) 652 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); 653#endif 654} /* fits_in_signed_long() */ 655static INLINE int 656fits_in_unsigned_long (num) 657 offsetT num ATTRIBUTE_UNUSED; 658{ 659#ifndef BFD64 660 return 1; 661#else 662 return (num & (((offsetT) 2 << 31) - 1)) == num; 663#endif 664} /* fits_in_unsigned_long() */ 665 666static int 667smallest_imm_type (num) 668 offsetT num; 669{ 670 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)) 671 { 672 /* This code is disabled on the 486 because all the Imm1 forms 673 in the opcode table are slower on the i486. They're the 674 versions with the implicitly specified single-position 675 displacement, which has another syntax if you really want to 676 use that form. */ 677 if (num == 1) 678 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64; 679 } 680 return (fits_in_signed_byte (num) 681 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64) 682 : fits_in_unsigned_byte (num) 683 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64) 684 : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) 685 ? (Imm16 | Imm32 | Imm32S | Imm64) 686 : fits_in_signed_long (num) 687 ? (Imm32 | Imm32S | Imm64) 688 : fits_in_unsigned_long (num) 689 ? (Imm32 | Imm64) 690 : Imm64); 691} 692 693static offsetT 694offset_in_range (val, size) 695 offsetT val; 696 int size; 697{ 698 addressT mask; 699 700 switch (size) 701 { 702 case 1: mask = ((addressT) 1 << 8) - 1; break; 703 case 2: mask = ((addressT) 1 << 16) - 1; break; 704 case 4: mask = ((addressT) 2 << 31) - 1; break; 705#ifdef BFD64 706 case 8: mask = ((addressT) 2 << 63) - 1; break; 707#endif 708 default: abort (); 709 } 710 711 /* If BFD64, sign extend val. */ 712 if (!use_rela_relocations) 713 if ((val & ~(((addressT) 2 << 31) - 1)) == 0) 714 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); 715 716 if ((val & ~mask) != 0 && (val & ~mask) != ~mask) 717 { 718 char buf1[40], buf2[40]; 719 720 sprint_value (buf1, val); 721 sprint_value (buf2, val & mask); 722 as_warn (_("%s shortened to %s"), buf1, buf2); 723 } 724 return val & mask; 725} 726 727/* Returns 0 if attempting to add a prefix where one from the same 728 class already exists, 1 if non rep/repne added, 2 if rep/repne 729 added. */ 730static int 731add_prefix (prefix) 732 unsigned int prefix; 733{ 734 int ret = 1; 735 unsigned int q; 736 737 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 738 && flag_code == CODE_64BIT) 739 { 740 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64) 741 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ)) 742 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ)))) 743 ret = 0; 744 q = REX_PREFIX; 745 } 746 else 747 { 748 switch (prefix) 749 { 750 default: 751 abort (); 752 753 case CS_PREFIX_OPCODE: 754 case DS_PREFIX_OPCODE: 755 case ES_PREFIX_OPCODE: 756 case FS_PREFIX_OPCODE: 757 case GS_PREFIX_OPCODE: 758 case SS_PREFIX_OPCODE: 759 q = SEG_PREFIX; 760 break; 761 762 case REPNE_PREFIX_OPCODE: 763 case REPE_PREFIX_OPCODE: 764 ret = 2; 765 /* fall thru */ 766 case LOCK_PREFIX_OPCODE: 767 q = LOCKREP_PREFIX; 768 break; 769 770 case FWAIT_OPCODE: 771 q = WAIT_PREFIX; 772 break; 773 774 case ADDR_PREFIX_OPCODE: 775 q = ADDR_PREFIX; 776 break; 777 778 case DATA_PREFIX_OPCODE: 779 q = DATA_PREFIX; 780 break; 781 } 782 if (i.prefix[q] != 0) 783 ret = 0; 784 } 785 786 if (ret) 787 { 788 if (!i.prefix[q]) 789 ++i.prefixes; 790 i.prefix[q] |= prefix; 791 } 792 else 793 as_bad (_("same type of prefix used twice")); 794 795 return ret; 796} 797 798static void 799set_code_flag (value) 800 int value; 801{ 802 flag_code = value; 803 cpu_arch_flags &= ~(Cpu64 | CpuNo64); 804 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); 805 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer)) 806 { 807 as_bad (_("64bit mode not supported on this CPU.")); 808 } 809 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386)) 810 { 811 as_bad (_("32bit mode not supported on this CPU.")); 812 } 813 stackop_size = '\0'; 814} 815 816static void 817set_16bit_gcc_code_flag (new_code_flag) 818 int new_code_flag; 819{ 820 flag_code = new_code_flag; 821 cpu_arch_flags &= ~(Cpu64 | CpuNo64); 822 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); 823 stackop_size = LONG_MNEM_SUFFIX; 824} 825 826static void 827set_intel_syntax (syntax_flag) 828 int syntax_flag; 829{ 830 /* Find out if register prefixing is specified. */ 831 int ask_naked_reg = 0; 832 833 SKIP_WHITESPACE (); 834 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 835 { 836 char *string = input_line_pointer; 837 int e = get_symbol_end (); 838 839 if (strcmp (string, "prefix") == 0) 840 ask_naked_reg = 1; 841 else if (strcmp (string, "noprefix") == 0) 842 ask_naked_reg = -1; 843 else 844 as_bad (_("bad argument to syntax directive.")); 845 *input_line_pointer = e; 846 } 847 demand_empty_rest_of_line (); 848 849 intel_syntax = syntax_flag; 850 851 if (ask_naked_reg == 0) 852 allow_naked_reg = (intel_syntax 853 && (bfd_get_symbol_leading_char (stdoutput) != '\0')); 854 else 855 allow_naked_reg = (ask_naked_reg < 0); 856 857 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; 858 identifier_chars['$'] = intel_syntax ? '$' : 0; 859} 860 861static void 862set_cpu_arch (dummy) 863 int dummy ATTRIBUTE_UNUSED; 864{ 865 SKIP_WHITESPACE (); 866 867 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 868 { 869 char *string = input_line_pointer; 870 int e = get_symbol_end (); 871 int i; 872 873 for (i = 0; cpu_arch[i].name; i++) 874 { 875 if (strcmp (string, cpu_arch[i].name) == 0) 876 { 877 if (*string != '.') 878 { 879 cpu_arch_name = cpu_arch[i].name; 880 cpu_sub_arch_name = NULL; 881 cpu_arch_flags = (cpu_arch[i].flags 882 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64)); 883 break; 884 } 885 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags) 886 { 887 cpu_sub_arch_name = cpu_arch[i].name; 888 cpu_arch_flags |= cpu_arch[i].flags; 889 } 890 *input_line_pointer = e; 891 demand_empty_rest_of_line (); 892 return; 893 } 894 } 895 if (!cpu_arch[i].name) 896 as_bad (_("no such architecture: `%s'"), string); 897 898 *input_line_pointer = e; 899 } 900 else 901 as_bad (_("missing cpu architecture")); 902 903 no_cond_jump_promotion = 0; 904 if (*input_line_pointer == ',' 905 && !is_end_of_line[(unsigned char) input_line_pointer[1]]) 906 { 907 char *string = ++input_line_pointer; 908 int e = get_symbol_end (); 909 910 if (strcmp (string, "nojumps") == 0) 911 no_cond_jump_promotion = 1; 912 else if (strcmp (string, "jumps") == 0) 913 ; 914 else 915 as_bad (_("no such architecture modifier: `%s'"), string); 916 917 *input_line_pointer = e; 918 } 919 920 demand_empty_rest_of_line (); 921} 922 923unsigned long 924i386_mach () 925{ 926 if (!strcmp (default_arch, "x86_64")) 927 return bfd_mach_x86_64; 928 else if (!strcmp (default_arch, "i386")) 929 return bfd_mach_i386_i386; 930 else 931 as_fatal (_("Unknown architecture")); 932} 933 934void 935md_begin () 936{ 937 const char *hash_err; 938 939 /* Initialize op_hash hash table. */ 940 op_hash = hash_new (); 941 942 { 943 const template *optab; 944 templates *core_optab; 945 946 /* Setup for loop. */ 947 optab = i386_optab; 948 core_optab = (templates *) xmalloc (sizeof (templates)); 949 core_optab->start = optab; 950 951 while (1) 952 { 953 ++optab; 954 if (optab->name == NULL 955 || strcmp (optab->name, (optab - 1)->name) != 0) 956 { 957 /* different name --> ship out current template list; 958 add to hash table; & begin anew. */ 959 core_optab->end = optab; 960 hash_err = hash_insert (op_hash, 961 (optab - 1)->name, 962 (PTR) core_optab); 963 if (hash_err) 964 { 965 as_fatal (_("Internal Error: Can't hash %s: %s"), 966 (optab - 1)->name, 967 hash_err); 968 } 969 if (optab->name == NULL) 970 break; 971 core_optab = (templates *) xmalloc (sizeof (templates)); 972 core_optab->start = optab; 973 } 974 } 975 } 976 977 /* Initialize reg_hash hash table. */ 978 reg_hash = hash_new (); 979 { 980 const reg_entry *regtab; 981 982 for (regtab = i386_regtab; 983 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); 984 regtab++) 985 { 986 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); 987 if (hash_err) 988 as_fatal (_("Internal Error: Can't hash %s: %s"), 989 regtab->reg_name, 990 hash_err); 991 } 992 } 993 994 /* Fill in lexical tables: mnemonic_chars, operand_chars. */ 995 { 996 int c; 997 char *p; 998 999 for (c = 0; c < 256; c++) 1000 { 1001 if (ISDIGIT (c)) 1002 { 1003 digit_chars[c] = c; 1004 mnemonic_chars[c] = c; 1005 register_chars[c] = c; 1006 operand_chars[c] = c; 1007 } 1008 else if (ISLOWER (c)) 1009 { 1010 mnemonic_chars[c] = c; 1011 register_chars[c] = c; 1012 operand_chars[c] = c; 1013 } 1014 else if (ISUPPER (c)) 1015 { 1016 mnemonic_chars[c] = TOLOWER (c); 1017 register_chars[c] = mnemonic_chars[c]; 1018 operand_chars[c] = c; 1019 } 1020 1021 if (ISALPHA (c) || ISDIGIT (c)) 1022 identifier_chars[c] = c; 1023 else if (c >= 128) 1024 { 1025 identifier_chars[c] = c; 1026 operand_chars[c] = c; 1027 } 1028 } 1029 1030#ifdef LEX_AT 1031 identifier_chars['@'] = '@'; 1032#endif 1033#ifdef LEX_QM 1034 identifier_chars['?'] = '?'; 1035 operand_chars['?'] = '?'; 1036#endif 1037 digit_chars['-'] = '-'; 1038 mnemonic_chars['-'] = '-'; 1039 identifier_chars['_'] = '_'; 1040 identifier_chars['.'] = '.'; 1041 1042 for (p = operand_special_chars; *p != '\0'; p++) 1043 operand_chars[(unsigned char) *p] = *p; 1044 } 1045 1046#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 1047 if (IS_ELF) 1048 { 1049 record_alignment (text_section, 2); 1050 record_alignment (data_section, 2); 1051 record_alignment (bss_section, 2); 1052 } 1053#endif 1054 1055 if (flag_code == CODE_64BIT) 1056 { 1057 x86_dwarf2_return_column = 16; 1058 x86_cie_data_alignment = -8; 1059 } 1060 else 1061 { 1062 x86_dwarf2_return_column = 8; 1063 x86_cie_data_alignment = -4; 1064 } 1065} 1066 1067void 1068i386_print_statistics (file) 1069 FILE *file; 1070{ 1071 hash_print_statistics (file, "i386 opcode", op_hash); 1072 hash_print_statistics (file, "i386 register", reg_hash); 1073} 1074 1075#ifdef DEBUG386 1076 1077/* Debugging routines for md_assemble. */ 1078static void pi PARAMS ((char *, i386_insn *)); 1079static void pte PARAMS ((template *)); 1080static void pt PARAMS ((unsigned int)); 1081static void pe PARAMS ((expressionS *)); 1082static void ps PARAMS ((symbolS *)); 1083 1084static void 1085pi (line, x) 1086 char *line; 1087 i386_insn *x; 1088{ 1089 unsigned int i; 1090 1091 fprintf (stdout, "%s: template ", line); 1092 pte (&x->tm); 1093 fprintf (stdout, " address: base %s index %s scale %x\n", 1094 x->base_reg ? x->base_reg->reg_name : "none", 1095 x->index_reg ? x->index_reg->reg_name : "none", 1096 x->log2_scale_factor); 1097 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", 1098 x->rm.mode, x->rm.reg, x->rm.regmem); 1099 fprintf (stdout, " sib: base %x index %x scale %x\n", 1100 x->sib.base, x->sib.index, x->sib.scale); 1101 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", 1102 (x->rex & REX_MODE64) != 0, 1103 (x->rex & REX_EXTX) != 0, 1104 (x->rex & REX_EXTY) != 0, 1105 (x->rex & REX_EXTZ) != 0); 1106 for (i = 0; i < x->operands; i++) 1107 { 1108 fprintf (stdout, " #%d: ", i + 1); 1109 pt (x->types[i]); 1110 fprintf (stdout, "\n"); 1111 if (x->types[i] 1112 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) 1113 fprintf (stdout, "%s\n", x->op[i].regs->reg_name); 1114 if (x->types[i] & Imm) 1115 pe (x->op[i].imms); 1116 if (x->types[i] & Disp) 1117 pe (x->op[i].disps); 1118 } 1119} 1120 1121static void 1122pte (t) 1123 template *t; 1124{ 1125 unsigned int i; 1126 fprintf (stdout, " %d operands ", t->operands); 1127 fprintf (stdout, "opcode %x ", t->base_opcode); 1128 if (t->extension_opcode != None) 1129 fprintf (stdout, "ext %x ", t->extension_opcode); 1130 if (t->opcode_modifier & D) 1131 fprintf (stdout, "D"); 1132 if (t->opcode_modifier & W) 1133 fprintf (stdout, "W"); 1134 fprintf (stdout, "\n"); 1135 for (i = 0; i < t->operands; i++) 1136 { 1137 fprintf (stdout, " #%d type ", i + 1); 1138 pt (t->operand_types[i]); 1139 fprintf (stdout, "\n"); 1140 } 1141} 1142 1143static void 1144pe (e) 1145 expressionS *e; 1146{ 1147 fprintf (stdout, " operation %d\n", e->X_op); 1148 fprintf (stdout, " add_number %ld (%lx)\n", 1149 (long) e->X_add_number, (long) e->X_add_number); 1150 if (e->X_add_symbol) 1151 { 1152 fprintf (stdout, " add_symbol "); 1153 ps (e->X_add_symbol); 1154 fprintf (stdout, "\n"); 1155 } 1156 if (e->X_op_symbol) 1157 { 1158 fprintf (stdout, " op_symbol "); 1159 ps (e->X_op_symbol); 1160 fprintf (stdout, "\n"); 1161 } 1162} 1163 1164static void 1165ps (s) 1166 symbolS *s; 1167{ 1168 fprintf (stdout, "%s type %s%s", 1169 S_GET_NAME (s), 1170 S_IS_EXTERNAL (s) ? "EXTERNAL " : "", 1171 segment_name (S_GET_SEGMENT (s))); 1172} 1173 1174static struct type_name 1175 { 1176 unsigned int mask; 1177 char *tname; 1178 } 1179const type_names[] = 1180{ 1181 { Reg8, "r8" }, 1182 { Reg16, "r16" }, 1183 { Reg32, "r32" }, 1184 { Reg64, "r64" }, 1185 { Imm8, "i8" }, 1186 { Imm8S, "i8s" }, 1187 { Imm16, "i16" }, 1188 { Imm32, "i32" }, 1189 { Imm32S, "i32s" }, 1190 { Imm64, "i64" }, 1191 { Imm1, "i1" }, 1192 { BaseIndex, "BaseIndex" }, 1193 { Disp8, "d8" }, 1194 { Disp16, "d16" }, 1195 { Disp32, "d32" }, 1196 { Disp32S, "d32s" }, 1197 { Disp64, "d64" }, 1198 { InOutPortReg, "InOutPortReg" }, 1199 { ShiftCount, "ShiftCount" }, 1200 { Control, "control reg" }, 1201 { Test, "test reg" }, 1202 { Debug, "debug reg" }, 1203 { FloatReg, "FReg" }, 1204 { FloatAcc, "FAcc" }, 1205 { SReg2, "SReg2" }, 1206 { SReg3, "SReg3" }, 1207 { Acc, "Acc" }, 1208 { JumpAbsolute, "Jump Absolute" }, 1209 { RegMMX, "rMMX" }, 1210 { RegXMM, "rXMM" }, 1211 { EsSeg, "es" }, 1212 { 0, "" } 1213}; 1214 1215static void 1216pt (t) 1217 unsigned int t; 1218{ 1219 const struct type_name *ty; 1220 1221 for (ty = type_names; ty->mask; ty++) 1222 if (t & ty->mask) 1223 fprintf (stdout, "%s, ", ty->tname); 1224 fflush (stdout); 1225} 1226 1227#endif /* DEBUG386 */ 1228 1229static bfd_reloc_code_real_type 1230reloc (unsigned int size, 1231 int pcrel, 1232 int sign, 1233 bfd_reloc_code_real_type other) 1234{ 1235 if (other != NO_RELOC) 1236 { 1237 reloc_howto_type *reloc; 1238 1239 if (size == 8) 1240 switch (other) 1241 { 1242 case BFD_RELOC_X86_64_GOT32: 1243 return BFD_RELOC_X86_64_GOT64; 1244 break; 1245 case BFD_RELOC_X86_64_PLTOFF64: 1246 return BFD_RELOC_X86_64_PLTOFF64; 1247 break; 1248 case BFD_RELOC_X86_64_GOTPC32: 1249 other = BFD_RELOC_X86_64_GOTPC64; 1250 break; 1251 case BFD_RELOC_X86_64_GOTPCREL: 1252 other = BFD_RELOC_X86_64_GOTPCREL64; 1253 break; 1254 case BFD_RELOC_X86_64_TPOFF32: 1255 other = BFD_RELOC_X86_64_TPOFF64; 1256 break; 1257 case BFD_RELOC_X86_64_DTPOFF32: 1258 other = BFD_RELOC_X86_64_DTPOFF64; 1259 break; 1260 default: 1261 break; 1262 } 1263 1264 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ 1265 if (size == 4 && flag_code != CODE_64BIT) 1266 sign = -1; 1267 1268 reloc = bfd_reloc_type_lookup (stdoutput, other); 1269 if (!reloc) 1270 as_bad (_("unknown relocation (%u)"), other); 1271 else if (size != bfd_get_reloc_size (reloc)) 1272 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), 1273 bfd_get_reloc_size (reloc), 1274 size); 1275 else if (pcrel && !reloc->pc_relative) 1276 as_bad (_("non-pc-relative relocation for pc-relative field")); 1277 else if ((reloc->complain_on_overflow == complain_overflow_signed 1278 && !sign) 1279 || (reloc->complain_on_overflow == complain_overflow_unsigned 1280 && sign > 0)) 1281 as_bad (_("relocated field and relocation type differ in signedness")); 1282 else 1283 return other; 1284 return NO_RELOC; 1285 } 1286 1287 if (pcrel) 1288 { 1289 if (!sign) 1290 as_bad (_("there are no unsigned pc-relative relocations")); 1291 switch (size) 1292 { 1293 case 1: return BFD_RELOC_8_PCREL; 1294 case 2: return BFD_RELOC_16_PCREL; 1295 case 4: return BFD_RELOC_32_PCREL; 1296 case 8: return BFD_RELOC_64_PCREL; 1297 } 1298 as_bad (_("cannot do %u byte pc-relative relocation"), size); 1299 } 1300 else 1301 { 1302 if (sign > 0) 1303 switch (size) 1304 { 1305 case 4: return BFD_RELOC_X86_64_32S; 1306 } 1307 else 1308 switch (size) 1309 { 1310 case 1: return BFD_RELOC_8; 1311 case 2: return BFD_RELOC_16; 1312 case 4: return BFD_RELOC_32; 1313 case 8: return BFD_RELOC_64; 1314 } 1315 as_bad (_("cannot do %s %u byte relocation"), 1316 sign > 0 ? "signed" : "unsigned", size); 1317 } 1318 1319 abort (); 1320 return BFD_RELOC_NONE; 1321} 1322 1323/* Here we decide which fixups can be adjusted to make them relative to 1324 the beginning of the section instead of the symbol. Basically we need 1325 to make sure that the dynamic relocations are done correctly, so in 1326 some cases we force the original symbol to be used. */ 1327 1328int 1329tc_i386_fix_adjustable (fixP) 1330 fixS *fixP ATTRIBUTE_UNUSED; 1331{ 1332#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 1333 if (!IS_ELF) 1334 return 1; 1335 1336 /* Don't adjust pc-relative references to merge sections in 64-bit 1337 mode. */ 1338 if (use_rela_relocations 1339 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 1340 && fixP->fx_pcrel) 1341 return 0; 1342 1343 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations 1344 and changed later by validate_fix. */ 1345 if (GOT_symbol && fixP->fx_subsy == GOT_symbol 1346 && fixP->fx_r_type == BFD_RELOC_32_PCREL) 1347 return 0; 1348 1349 /* adjust_reloc_syms doesn't know about the GOT. */ 1350 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF 1351 || fixP->fx_r_type == BFD_RELOC_386_PLT32 1352 || fixP->fx_r_type == BFD_RELOC_386_GOT32 1353 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD 1354 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM 1355 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 1356 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 1357 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE 1358 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE 1359 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 1360 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE 1361 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC 1362 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL 1363 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 1364 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 1365 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL 1366 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD 1367 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD 1368 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 1369 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 1370 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF 1371 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 1372 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 1373 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 1374 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC 1375 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL 1376 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 1377 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 1378 return 0; 1379#endif 1380 return 1; 1381} 1382 1383static int intel_float_operand PARAMS ((const char *mnemonic)); 1384 1385static int 1386intel_float_operand (mnemonic) 1387 const char *mnemonic; 1388{ 1389 /* Note that the value returned is meaningful only for opcodes with (memory) 1390 operands, hence the code here is free to improperly handle opcodes that 1391 have no operands (for better performance and smaller code). */ 1392 1393 if (mnemonic[0] != 'f') 1394 return 0; /* non-math */ 1395 1396 switch (mnemonic[1]) 1397 { 1398 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and 1399 the fs segment override prefix not currently handled because no 1400 call path can make opcodes without operands get here */ 1401 case 'i': 1402 return 2 /* integer op */; 1403 case 'l': 1404 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) 1405 return 3; /* fldcw/fldenv */ 1406 break; 1407 case 'n': 1408 if (mnemonic[2] != 'o' /* fnop */) 1409 return 3; /* non-waiting control op */ 1410 break; 1411 case 'r': 1412 if (mnemonic[2] == 's') 1413 return 3; /* frstor/frstpm */ 1414 break; 1415 case 's': 1416 if (mnemonic[2] == 'a') 1417 return 3; /* fsave */ 1418 if (mnemonic[2] == 't') 1419 { 1420 switch (mnemonic[3]) 1421 { 1422 case 'c': /* fstcw */ 1423 case 'd': /* fstdw */ 1424 case 'e': /* fstenv */ 1425 case 's': /* fsts[gw] */ 1426 return 3; 1427 } 1428 } 1429 break; 1430 case 'x': 1431 if (mnemonic[2] == 'r' || mnemonic[2] == 's') 1432 return 0; /* fxsave/fxrstor are not really math ops */ 1433 break; 1434 } 1435 1436 return 1; 1437} 1438 1439/* This is the guts of the machine-dependent assembler. LINE points to a 1440 machine dependent instruction. This function is supposed to emit 1441 the frags/bytes it assembles to. */ 1442 1443void 1444md_assemble (line) 1445 char *line; 1446{ 1447 int j; 1448 char mnemonic[MAX_MNEM_SIZE]; 1449 1450 /* Initialize globals. */ 1451 memset (&i, '\0', sizeof (i)); 1452 for (j = 0; j < MAX_OPERANDS; j++) 1453 i.reloc[j] = NO_RELOC; 1454 memset (disp_expressions, '\0', sizeof (disp_expressions)); 1455 memset (im_expressions, '\0', sizeof (im_expressions)); 1456 save_stack_p = save_stack; 1457 1458 /* First parse an instruction mnemonic & call i386_operand for the operands. 1459 We assume that the scrubber has arranged it so that line[0] is the valid 1460 start of a (possibly prefixed) mnemonic. */ 1461 1462 line = parse_insn (line, mnemonic); 1463 if (line == NULL) 1464 return; 1465 1466 line = parse_operands (line, mnemonic); 1467 if (line == NULL) 1468 return; 1469 1470 /* Now we've parsed the mnemonic into a set of templates, and have the 1471 operands at hand. */ 1472 1473 /* All intel opcodes have reversed operands except for "bound" and 1474 "enter". We also don't reverse intersegment "jmp" and "call" 1475 instructions with 2 immediate operands so that the immediate segment 1476 precedes the offset, as it does when in AT&T mode. "enter" and the 1477 intersegment "jmp" and "call" instructions are the only ones that 1478 have two immediate operands. */ 1479 if (intel_syntax && i.operands > 1 1480 && (strcmp (mnemonic, "bound") != 0) 1481 && (strcmp (mnemonic, "invlpga") != 0) 1482 && !((i.types[0] & Imm) && (i.types[1] & Imm))) 1483 swap_operands (); 1484 1485 if (i.imm_operands) 1486 optimize_imm (); 1487 1488 /* Don't optimize displacement for movabs since it only takes 64bit 1489 displacement. */ 1490 if (i.disp_operands 1491 && (flag_code != CODE_64BIT 1492 || strcmp (mnemonic, "movabs") != 0)) 1493 optimize_disp (); 1494 1495 /* Next, we find a template that matches the given insn, 1496 making sure the overlap of the given operands types is consistent 1497 with the template operand types. */ 1498 1499 if (!match_template ()) 1500 return; 1501 1502 if (intel_syntax) 1503 { 1504 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ 1505 if (SYSV386_COMPAT 1506 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) 1507 i.tm.base_opcode ^= FloatR; 1508 1509 /* Zap movzx and movsx suffix. The suffix may have been set from 1510 "word ptr" or "byte ptr" on the source operand, but we'll use 1511 the suffix later to choose the destination register. */ 1512 if ((i.tm.base_opcode & ~9) == 0x0fb6) 1513 { 1514 if (i.reg_operands < 2 1515 && !i.suffix 1516 && (~i.tm.opcode_modifier 1517 & (No_bSuf 1518 | No_wSuf 1519 | No_lSuf 1520 | No_sSuf 1521 | No_xSuf 1522 | No_qSuf))) 1523 as_bad (_("ambiguous operand size for `%s'"), i.tm.name); 1524 1525 i.suffix = 0; 1526 } 1527 } 1528 1529 if (i.tm.opcode_modifier & FWait) 1530 if (!add_prefix (FWAIT_OPCODE)) 1531 return; 1532 1533 /* Check string instruction segment overrides. */ 1534 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) 1535 { 1536 if (!check_string ()) 1537 return; 1538 } 1539 1540 if (!process_suffix ()) 1541 return; 1542 1543 /* Make still unresolved immediate matches conform to size of immediate 1544 given in i.suffix. */ 1545 if (!finalize_imm ()) 1546 return; 1547 1548 if (i.types[0] & Imm1) 1549 i.imm_operands = 0; /* kludge for shift insns. */ 1550 if (i.types[0] & ImplicitRegister) 1551 i.reg_operands--; 1552 if (i.types[1] & ImplicitRegister) 1553 i.reg_operands--; 1554 if (i.types[2] & ImplicitRegister) 1555 i.reg_operands--; 1556 1557 if (i.tm.opcode_modifier & ImmExt) 1558 { 1559 expressionS *exp; 1560 1561 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0) 1562 { 1563 /* These Intel Prescott New Instructions have the fixed 1564 operands with an opcode suffix which is coded in the same 1565 place as an 8-bit immediate field would be. Here we check 1566 those operands and remove them afterwards. */ 1567 unsigned int x; 1568 1569 for (x = 0; x < i.operands; x++) 1570 if (i.op[x].regs->reg_num != x) 1571 as_bad (_("can't use register '%%%s' as operand %d in '%s'."), 1572 i.op[x].regs->reg_name, x + 1, i.tm.name); 1573 i.operands = 0; 1574 } 1575 1576 /* These AMD 3DNow! and Intel Katmai New Instructions have an 1577 opcode suffix which is coded in the same place as an 8-bit 1578 immediate field would be. Here we fake an 8-bit immediate 1579 operand from the opcode suffix stored in tm.extension_opcode. */ 1580 1581 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); 1582 1583 exp = &im_expressions[i.imm_operands++]; 1584 i.op[i.operands].imms = exp; 1585 i.types[i.operands++] = Imm8; 1586 exp->X_op = O_constant; 1587 exp->X_add_number = i.tm.extension_opcode; 1588 i.tm.extension_opcode = None; 1589 } 1590 1591 /* For insns with operands there are more diddles to do to the opcode. */ 1592 if (i.operands) 1593 { 1594 if (!process_operands ()) 1595 return; 1596 } 1597 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) 1598 { 1599 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ 1600 as_warn (_("translating to `%sp'"), i.tm.name); 1601 } 1602 1603 /* Handle conversion of 'int $3' --> special int3 insn. */ 1604 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) 1605 { 1606 i.tm.base_opcode = INT3_OPCODE; 1607 i.imm_operands = 0; 1608 } 1609 1610 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) 1611 && i.op[0].disps->X_op == O_constant) 1612 { 1613 /* Convert "jmp constant" (and "call constant") to a jump (call) to 1614 the absolute address given by the constant. Since ix86 jumps and 1615 calls are pc relative, we need to generate a reloc. */ 1616 i.op[0].disps->X_add_symbol = &abs_symbol; 1617 i.op[0].disps->X_op = O_symbol; 1618 } 1619 1620 if ((i.tm.opcode_modifier & Rex64) != 0) 1621 i.rex |= REX_MODE64; 1622 1623 /* For 8 bit registers we need an empty rex prefix. Also if the 1624 instruction already has a prefix, we need to convert old 1625 registers to new ones. */ 1626 1627 if (((i.types[0] & Reg8) != 0 1628 && (i.op[0].regs->reg_flags & RegRex64) != 0) 1629 || ((i.types[1] & Reg8) != 0 1630 && (i.op[1].regs->reg_flags & RegRex64) != 0) 1631 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0) 1632 && i.rex != 0)) 1633 { 1634 int x; 1635 1636 i.rex |= REX_OPCODE; 1637 for (x = 0; x < 2; x++) 1638 { 1639 /* Look for 8 bit operand that uses old registers. */ 1640 if ((i.types[x] & Reg8) != 0 1641 && (i.op[x].regs->reg_flags & RegRex64) == 0) 1642 { 1643 /* In case it is "hi" register, give up. */ 1644 if (i.op[x].regs->reg_num > 3) 1645 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."), 1646 i.op[x].regs->reg_name); 1647 1648 /* Otherwise it is equivalent to the extended register. 1649 Since the encoding doesn't change this is merely 1650 cosmetic cleanup for debug output. */ 1651 1652 i.op[x].regs = i.op[x].regs + 8; 1653 } 1654 } 1655 } 1656 1657 if (i.rex != 0) 1658 add_prefix (REX_OPCODE | i.rex); 1659 1660 /* We are ready to output the insn. */ 1661 output_insn (); 1662} 1663 1664static char * 1665parse_insn (line, mnemonic) 1666 char *line; 1667 char *mnemonic; 1668{ 1669 char *l = line; 1670 char *token_start = l; 1671 char *mnem_p; 1672 int supported; 1673 const template *t; 1674 1675 /* Non-zero if we found a prefix only acceptable with string insns. */ 1676 const char *expecting_string_instruction = NULL; 1677 1678 while (1) 1679 { 1680 mnem_p = mnemonic; 1681 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) 1682 { 1683 mnem_p++; 1684 if (mnem_p >= mnemonic + MAX_MNEM_SIZE) 1685 { 1686 as_bad (_("no such instruction: `%s'"), token_start); 1687 return NULL; 1688 } 1689 l++; 1690 } 1691 if (!is_space_char (*l) 1692 && *l != END_OF_INSN 1693 && (intel_syntax 1694 || (*l != PREFIX_SEPARATOR 1695 && *l != ','))) 1696 { 1697 as_bad (_("invalid character %s in mnemonic"), 1698 output_invalid (*l)); 1699 return NULL; 1700 } 1701 if (token_start == l) 1702 { 1703 if (!intel_syntax && *l == PREFIX_SEPARATOR) 1704 as_bad (_("expecting prefix; got nothing")); 1705 else 1706 as_bad (_("expecting mnemonic; got nothing")); 1707 return NULL; 1708 } 1709 1710 /* Look up instruction (or prefix) via hash table. */ 1711 current_templates = hash_find (op_hash, mnemonic); 1712 1713 if (*l != END_OF_INSN 1714 && (!is_space_char (*l) || l[1] != END_OF_INSN) 1715 && current_templates 1716 && (current_templates->start->opcode_modifier & IsPrefix)) 1717 { 1718 if (current_templates->start->cpu_flags 1719 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64)) 1720 { 1721 as_bad ((flag_code != CODE_64BIT 1722 ? _("`%s' is only supported in 64-bit mode") 1723 : _("`%s' is not supported in 64-bit mode")), 1724 current_templates->start->name); 1725 return NULL; 1726 } 1727 /* If we are in 16-bit mode, do not allow addr16 or data16. 1728 Similarly, in 32-bit mode, do not allow addr32 or data32. */ 1729 if ((current_templates->start->opcode_modifier & (Size16 | Size32)) 1730 && flag_code != CODE_64BIT 1731 && (((current_templates->start->opcode_modifier & Size32) != 0) 1732 ^ (flag_code == CODE_16BIT))) 1733 { 1734 as_bad (_("redundant %s prefix"), 1735 current_templates->start->name); 1736 return NULL; 1737 } 1738 /* Add prefix, checking for repeated prefixes. */ 1739 switch (add_prefix (current_templates->start->base_opcode)) 1740 { 1741 case 0: 1742 return NULL; 1743 case 2: 1744 expecting_string_instruction = current_templates->start->name; 1745 break; 1746 } 1747 /* Skip past PREFIX_SEPARATOR and reset token_start. */ 1748 token_start = ++l; 1749 } 1750 else 1751 break; 1752 } 1753 1754 if (!current_templates) 1755 { 1756 /* See if we can get a match by trimming off a suffix. */ 1757 switch (mnem_p[-1]) 1758 { 1759 case WORD_MNEM_SUFFIX: 1760 if (intel_syntax && (intel_float_operand (mnemonic) & 2)) 1761 i.suffix = SHORT_MNEM_SUFFIX; 1762 else 1763 case BYTE_MNEM_SUFFIX: 1764 case QWORD_MNEM_SUFFIX: 1765 i.suffix = mnem_p[-1]; 1766 mnem_p[-1] = '\0'; 1767 current_templates = hash_find (op_hash, mnemonic); 1768 break; 1769 case SHORT_MNEM_SUFFIX: 1770 case LONG_MNEM_SUFFIX: 1771 if (!intel_syntax) 1772 { 1773 i.suffix = mnem_p[-1]; 1774 mnem_p[-1] = '\0'; 1775 current_templates = hash_find (op_hash, mnemonic); 1776 } 1777 break; 1778 1779 /* Intel Syntax. */ 1780 case 'd': 1781 if (intel_syntax) 1782 { 1783 if (intel_float_operand (mnemonic) == 1) 1784 i.suffix = SHORT_MNEM_SUFFIX; 1785 else 1786 i.suffix = LONG_MNEM_SUFFIX; 1787 mnem_p[-1] = '\0'; 1788 current_templates = hash_find (op_hash, mnemonic); 1789 } 1790 break; 1791 } 1792 if (!current_templates) 1793 { 1794 as_bad (_("no such instruction: `%s'"), token_start); 1795 return NULL; 1796 } 1797 } 1798 1799 if (current_templates->start->opcode_modifier & (Jump | JumpByte)) 1800 { 1801 /* Check for a branch hint. We allow ",pt" and ",pn" for 1802 predict taken and predict not taken respectively. 1803 I'm not sure that branch hints actually do anything on loop 1804 and jcxz insns (JumpByte) for current Pentium4 chips. They 1805 may work in the future and it doesn't hurt to accept them 1806 now. */ 1807 if (l[0] == ',' && l[1] == 'p') 1808 { 1809 if (l[2] == 't') 1810 { 1811 if (!add_prefix (DS_PREFIX_OPCODE)) 1812 return NULL; 1813 l += 3; 1814 } 1815 else if (l[2] == 'n') 1816 { 1817 if (!add_prefix (CS_PREFIX_OPCODE)) 1818 return NULL; 1819 l += 3; 1820 } 1821 } 1822 } 1823 /* Any other comma loses. */ 1824 if (*l == ',') 1825 { 1826 as_bad (_("invalid character %s in mnemonic"), 1827 output_invalid (*l)); 1828 return NULL; 1829 } 1830 1831 /* Check if instruction is supported on specified architecture. */ 1832 supported = 0; 1833 for (t = current_templates->start; t < current_templates->end; ++t) 1834 { 1835 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64)) 1836 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))) 1837 supported |= 1; 1838 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64))) 1839 supported |= 2; 1840 } 1841 if (!(supported & 2)) 1842 { 1843 as_bad (flag_code == CODE_64BIT 1844 ? _("`%s' is not supported in 64-bit mode") 1845 : _("`%s' is only supported in 64-bit mode"), 1846 current_templates->start->name); 1847 return NULL; 1848 } 1849 if (!(supported & 1)) 1850 { 1851 as_warn (_("`%s' is not supported on `%s%s'"), 1852 current_templates->start->name, 1853 cpu_arch_name, 1854 cpu_sub_arch_name ? cpu_sub_arch_name : ""); 1855 } 1856 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT)) 1857 { 1858 as_warn (_("use .code16 to ensure correct addressing mode")); 1859 } 1860 1861 /* Check for rep/repne without a string instruction. */ 1862 if (expecting_string_instruction) 1863 { 1864 static templates override; 1865 1866 for (t = current_templates->start; t < current_templates->end; ++t) 1867 if (t->opcode_modifier & IsString) 1868 break; 1869 if (t >= current_templates->end) 1870 { 1871 as_bad (_("expecting string instruction after `%s'"), 1872 expecting_string_instruction); 1873 return NULL; 1874 } 1875 for (override.start = t; t < current_templates->end; ++t) 1876 if (!(t->opcode_modifier & IsString)) 1877 break; 1878 override.end = t; 1879 current_templates = &override; 1880 } 1881 1882 return l; 1883} 1884 1885static char * 1886parse_operands (l, mnemonic) 1887 char *l; 1888 const char *mnemonic; 1889{ 1890 char *token_start; 1891 1892 /* 1 if operand is pending after ','. */ 1893 unsigned int expecting_operand = 0; 1894 1895 /* Non-zero if operand parens not balanced. */ 1896 unsigned int paren_not_balanced; 1897 1898 while (*l != END_OF_INSN) 1899 { 1900 /* Skip optional white space before operand. */ 1901 if (is_space_char (*l)) 1902 ++l; 1903 if (!is_operand_char (*l) && *l != END_OF_INSN) 1904 { 1905 as_bad (_("invalid character %s before operand %d"), 1906 output_invalid (*l), 1907 i.operands + 1); 1908 return NULL; 1909 } 1910 token_start = l; /* after white space */ 1911 paren_not_balanced = 0; 1912 while (paren_not_balanced || *l != ',') 1913 { 1914 if (*l == END_OF_INSN) 1915 { 1916 if (paren_not_balanced) 1917 { 1918 if (!intel_syntax) 1919 as_bad (_("unbalanced parenthesis in operand %d."), 1920 i.operands + 1); 1921 else 1922 as_bad (_("unbalanced brackets in operand %d."), 1923 i.operands + 1); 1924 return NULL; 1925 } 1926 else 1927 break; /* we are done */ 1928 } 1929 else if (!is_operand_char (*l) && !is_space_char (*l)) 1930 { 1931 as_bad (_("invalid character %s in operand %d"), 1932 output_invalid (*l), 1933 i.operands + 1); 1934 return NULL; 1935 } 1936 if (!intel_syntax) 1937 { 1938 if (*l == '(') 1939 ++paren_not_balanced; 1940 if (*l == ')') 1941 --paren_not_balanced; 1942 } 1943 else 1944 { 1945 if (*l == '[') 1946 ++paren_not_balanced; 1947 if (*l == ']') 1948 --paren_not_balanced; 1949 } 1950 l++; 1951 } 1952 if (l != token_start) 1953 { /* Yes, we've read in another operand. */ 1954 unsigned int operand_ok; 1955 this_operand = i.operands++; 1956 if (i.operands > MAX_OPERANDS) 1957 { 1958 as_bad (_("spurious operands; (%d operands/instruction max)"), 1959 MAX_OPERANDS); 1960 return NULL; 1961 } 1962 /* Now parse operand adding info to 'i' as we go along. */ 1963 END_STRING_AND_SAVE (l); 1964 1965 if (intel_syntax) 1966 operand_ok = 1967 i386_intel_operand (token_start, 1968 intel_float_operand (mnemonic)); 1969 else 1970 operand_ok = i386_operand (token_start); 1971 1972 RESTORE_END_STRING (l); 1973 if (!operand_ok) 1974 return NULL; 1975 } 1976 else 1977 { 1978 if (expecting_operand) 1979 { 1980 expecting_operand_after_comma: 1981 as_bad (_("expecting operand after ','; got nothing")); 1982 return NULL; 1983 } 1984 if (*l == ',') 1985 { 1986 as_bad (_("expecting operand before ','; got nothing")); 1987 return NULL; 1988 } 1989 } 1990 1991 /* Now *l must be either ',' or END_OF_INSN. */ 1992 if (*l == ',') 1993 { 1994 if (*++l == END_OF_INSN) 1995 { 1996 /* Just skip it, if it's \n complain. */ 1997 goto expecting_operand_after_comma; 1998 } 1999 expecting_operand = 1; 2000 } 2001 } 2002 return l; 2003} 2004 2005static void 2006swap_operands () 2007{ 2008 union i386_op temp_op; 2009 unsigned int temp_type; 2010 enum bfd_reloc_code_real temp_reloc; 2011 int xchg1 = 0; 2012 int xchg2 = 0; 2013 2014 if (i.operands == 2) 2015 { 2016 xchg1 = 0; 2017 xchg2 = 1; 2018 } 2019 else if (i.operands == 3) 2020 { 2021 xchg1 = 0; 2022 xchg2 = 2; 2023 } 2024 temp_type = i.types[xchg2]; 2025 i.types[xchg2] = i.types[xchg1]; 2026 i.types[xchg1] = temp_type; 2027 temp_op = i.op[xchg2]; 2028 i.op[xchg2] = i.op[xchg1]; 2029 i.op[xchg1] = temp_op; 2030 temp_reloc = i.reloc[xchg2]; 2031 i.reloc[xchg2] = i.reloc[xchg1]; 2032 i.reloc[xchg1] = temp_reloc; 2033 2034 if (i.mem_operands == 2) 2035 { 2036 const seg_entry *temp_seg; 2037 temp_seg = i.seg[0]; 2038 i.seg[0] = i.seg[1]; 2039 i.seg[1] = temp_seg; 2040 } 2041} 2042 2043/* Try to ensure constant immediates are represented in the smallest 2044 opcode possible. */ 2045static void 2046optimize_imm () 2047{ 2048 char guess_suffix = 0; 2049 int op; 2050 2051 if (i.suffix) 2052 guess_suffix = i.suffix; 2053 else if (i.reg_operands) 2054 { 2055 /* Figure out a suffix from the last register operand specified. 2056 We can't do this properly yet, ie. excluding InOutPortReg, 2057 but the following works for instructions with immediates. 2058 In any case, we can't set i.suffix yet. */ 2059 for (op = i.operands; --op >= 0;) 2060 if (i.types[op] & Reg) 2061 { 2062 if (i.types[op] & Reg8) 2063 guess_suffix = BYTE_MNEM_SUFFIX; 2064 else if (i.types[op] & Reg16) 2065 guess_suffix = WORD_MNEM_SUFFIX; 2066 else if (i.types[op] & Reg32) 2067 guess_suffix = LONG_MNEM_SUFFIX; 2068 else if (i.types[op] & Reg64) 2069 guess_suffix = QWORD_MNEM_SUFFIX; 2070 break; 2071 } 2072 } 2073 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) 2074 guess_suffix = WORD_MNEM_SUFFIX; 2075 2076 for (op = i.operands; --op >= 0;) 2077 if (i.types[op] & Imm) 2078 { 2079 switch (i.op[op].imms->X_op) 2080 { 2081 case O_constant: 2082 /* If a suffix is given, this operand may be shortened. */ 2083 switch (guess_suffix) 2084 { 2085 case LONG_MNEM_SUFFIX: 2086 i.types[op] |= Imm32 | Imm64; 2087 break; 2088 case WORD_MNEM_SUFFIX: 2089 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64; 2090 break; 2091 case BYTE_MNEM_SUFFIX: 2092 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64; 2093 break; 2094 } 2095 2096 /* If this operand is at most 16 bits, convert it 2097 to a signed 16 bit number before trying to see 2098 whether it will fit in an even smaller size. 2099 This allows a 16-bit operand such as $0xffe0 to 2100 be recognised as within Imm8S range. */ 2101 if ((i.types[op] & Imm16) 2102 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) 2103 { 2104 i.op[op].imms->X_add_number = 2105 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); 2106 } 2107 if ((i.types[op] & Imm32) 2108 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) 2109 == 0)) 2110 { 2111 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number 2112 ^ ((offsetT) 1 << 31)) 2113 - ((offsetT) 1 << 31)); 2114 } 2115 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number); 2116 2117 /* We must avoid matching of Imm32 templates when 64bit 2118 only immediate is available. */ 2119 if (guess_suffix == QWORD_MNEM_SUFFIX) 2120 i.types[op] &= ~Imm32; 2121 break; 2122 2123 case O_absent: 2124 case O_register: 2125 abort (); 2126 2127 /* Symbols and expressions. */ 2128 default: 2129 /* Convert symbolic operand to proper sizes for matching, but don't 2130 prevent matching a set of insns that only supports sizes other 2131 than those matching the insn suffix. */ 2132 { 2133 unsigned int mask, allowed = 0; 2134 const template *t; 2135 2136 for (t = current_templates->start; t < current_templates->end; ++t) 2137 allowed |= t->operand_types[op]; 2138 switch (guess_suffix) 2139 { 2140 case QWORD_MNEM_SUFFIX: 2141 mask = Imm64 | Imm32S; 2142 break; 2143 case LONG_MNEM_SUFFIX: 2144 mask = Imm32; 2145 break; 2146 case WORD_MNEM_SUFFIX: 2147 mask = Imm16; 2148 break; 2149 case BYTE_MNEM_SUFFIX: 2150 mask = Imm8; 2151 break; 2152 default: 2153 mask = 0; 2154 break; 2155 } 2156 if (mask & allowed) 2157 i.types[op] &= mask; 2158 } 2159 break; 2160 } 2161 } 2162} 2163 2164/* Try to use the smallest displacement type too. */ 2165static void 2166optimize_disp () 2167{ 2168 int op; 2169 2170 for (op = i.operands; --op >= 0;) 2171 if (i.types[op] & Disp) 2172 { 2173 if (i.op[op].disps->X_op == O_constant) 2174 { 2175 offsetT disp = i.op[op].disps->X_add_number; 2176 2177 if ((i.types[op] & Disp16) 2178 && (disp & ~(offsetT) 0xffff) == 0) 2179 { 2180 /* If this operand is at most 16 bits, convert 2181 to a signed 16 bit number and don't use 64bit 2182 displacement. */ 2183 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); 2184 i.types[op] &= ~Disp64; 2185 } 2186 if ((i.types[op] & Disp32) 2187 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0) 2188 { 2189 /* If this operand is at most 32 bits, convert 2190 to a signed 32 bit number and don't use 64bit 2191 displacement. */ 2192 disp &= (((offsetT) 2 << 31) - 1); 2193 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); 2194 i.types[op] &= ~Disp64; 2195 } 2196 if (!disp && (i.types[op] & BaseIndex)) 2197 { 2198 i.types[op] &= ~Disp; 2199 i.op[op].disps = 0; 2200 i.disp_operands--; 2201 } 2202 else if (flag_code == CODE_64BIT) 2203 { 2204 if (fits_in_signed_long (disp)) 2205 { 2206 i.types[op] &= ~Disp64; 2207 i.types[op] |= Disp32S; 2208 } 2209 if (fits_in_unsigned_long (disp)) 2210 i.types[op] |= Disp32; 2211 } 2212 if ((i.types[op] & (Disp32 | Disp32S | Disp16)) 2213 && fits_in_signed_byte (disp)) 2214 i.types[op] |= Disp8; 2215 } 2216 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL 2217 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) 2218 { 2219 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, 2220 i.op[op].disps, 0, i.reloc[op]); 2221 i.types[op] &= ~Disp; 2222 } 2223 else 2224 /* We only support 64bit displacement on constants. */ 2225 i.types[op] &= ~Disp64; 2226 } 2227} 2228 2229static int 2230match_template () 2231{ 2232 /* Points to template once we've found it. */ 2233 const template *t; 2234 unsigned int overlap0, overlap1, overlap2; 2235 unsigned int found_reverse_match; 2236 int suffix_check; 2237 2238#define MATCH(overlap, given, template) \ 2239 ((overlap & ~JumpAbsolute) \ 2240 && (((given) & (BaseIndex | JumpAbsolute)) \ 2241 == ((overlap) & (BaseIndex | JumpAbsolute)))) 2242 2243 /* If given types r0 and r1 are registers they must be of the same type 2244 unless the expected operand type register overlap is null. 2245 Note that Acc in a template matches every size of reg. */ 2246#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ 2247 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \ 2248 || ((g0) & Reg) == ((g1) & Reg) \ 2249 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) 2250 2251 overlap0 = 0; 2252 overlap1 = 0; 2253 overlap2 = 0; 2254 found_reverse_match = 0; 2255 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX 2256 ? No_bSuf 2257 : (i.suffix == WORD_MNEM_SUFFIX 2258 ? No_wSuf 2259 : (i.suffix == SHORT_MNEM_SUFFIX 2260 ? No_sSuf 2261 : (i.suffix == LONG_MNEM_SUFFIX 2262 ? No_lSuf 2263 : (i.suffix == QWORD_MNEM_SUFFIX 2264 ? No_qSuf 2265 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX 2266 ? No_xSuf : 0)))))); 2267 2268 for (t = current_templates->start; t < current_templates->end; t++) 2269 { 2270 /* Must have right number of operands. */ 2271 if (i.operands != t->operands) 2272 continue; 2273 2274 /* Check the suffix, except for some instructions in intel mode. */ 2275 if ((t->opcode_modifier & suffix_check) 2276 && !(intel_syntax 2277 && (t->opcode_modifier & IgnoreSize))) 2278 continue; 2279 2280 /* In general, don't allow 64-bit operands in 32-bit mode. */ 2281 if (i.suffix == QWORD_MNEM_SUFFIX 2282 && flag_code != CODE_64BIT 2283 && (intel_syntax 2284 ? (!(t->opcode_modifier & IgnoreSize) 2285 && !intel_float_operand (t->name)) 2286 : intel_float_operand (t->name) != 2) 2287 && (!(t->operand_types[0] & (RegMMX | RegXMM)) 2288 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM))) 2289 && (t->base_opcode != 0x0fc7 2290 || t->extension_opcode != 1 /* cmpxchg8b */)) 2291 continue; 2292 2293 /* Do not verify operands when there are none. */ 2294 else if (!t->operands) 2295 { 2296 if (t->cpu_flags & ~cpu_arch_flags) 2297 continue; 2298 /* We've found a match; break out of loop. */ 2299 break; 2300 } 2301 2302 overlap0 = i.types[0] & t->operand_types[0]; 2303 switch (t->operands) 2304 { 2305 case 1: 2306 if (!MATCH (overlap0, i.types[0], t->operand_types[0])) 2307 continue; 2308 break; 2309 case 2: 2310 case 3: 2311 overlap1 = i.types[1] & t->operand_types[1]; 2312 if (!MATCH (overlap0, i.types[0], t->operand_types[0]) 2313 || !MATCH (overlap1, i.types[1], t->operand_types[1]) 2314 /* monitor in SSE3 is a very special case. The first 2315 register and the second register may have differnet 2316 sizes. */ 2317 || !((t->base_opcode == 0x0f01 2318 && t->extension_opcode == 0xc8) 2319 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], 2320 t->operand_types[0], 2321 overlap1, i.types[1], 2322 t->operand_types[1]))) 2323 { 2324 /* Check if other direction is valid ... */ 2325 if ((t->opcode_modifier & (D | FloatD)) == 0) 2326 continue; 2327 2328 /* Try reversing direction of operands. */ 2329 overlap0 = i.types[0] & t->operand_types[1]; 2330 overlap1 = i.types[1] & t->operand_types[0]; 2331 if (!MATCH (overlap0, i.types[0], t->operand_types[1]) 2332 || !MATCH (overlap1, i.types[1], t->operand_types[0]) 2333 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], 2334 t->operand_types[1], 2335 overlap1, i.types[1], 2336 t->operand_types[0])) 2337 { 2338 /* Does not match either direction. */ 2339 continue; 2340 } 2341 /* found_reverse_match holds which of D or FloatDR 2342 we've found. */ 2343 found_reverse_match = t->opcode_modifier & (D | FloatDR); 2344 } 2345 /* Found a forward 2 operand match here. */ 2346 else if (t->operands == 3) 2347 { 2348 /* Here we make use of the fact that there are no 2349 reverse match 3 operand instructions, and all 3 2350 operand instructions only need to be checked for 2351 register consistency between operands 2 and 3. */ 2352 overlap2 = i.types[2] & t->operand_types[2]; 2353 if (!MATCH (overlap2, i.types[2], t->operand_types[2]) 2354 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], 2355 t->operand_types[1], 2356 overlap2, i.types[2], 2357 t->operand_types[2])) 2358 2359 continue; 2360 } 2361 /* Found either forward/reverse 2 or 3 operand match here: 2362 slip through to break. */ 2363 } 2364 if (t->cpu_flags & ~cpu_arch_flags) 2365 { 2366 found_reverse_match = 0; 2367 continue; 2368 } 2369 /* We've found a match; break out of loop. */ 2370 break; 2371 } 2372 2373 if (t == current_templates->end) 2374 { 2375 /* We found no match. */ 2376 as_bad (_("suffix or operands invalid for `%s'"), 2377 current_templates->start->name); 2378 return 0; 2379 } 2380 2381 if (!quiet_warnings) 2382 { 2383 if (!intel_syntax 2384 && ((i.types[0] & JumpAbsolute) 2385 != (t->operand_types[0] & JumpAbsolute))) 2386 { 2387 as_warn (_("indirect %s without `*'"), t->name); 2388 } 2389 2390 if ((t->opcode_modifier & (IsPrefix | IgnoreSize)) 2391 == (IsPrefix | IgnoreSize)) 2392 { 2393 /* Warn them that a data or address size prefix doesn't 2394 affect assembly of the next line of code. */ 2395 as_warn (_("stand-alone `%s' prefix"), t->name); 2396 } 2397 } 2398 2399 /* Copy the template we found. */ 2400 i.tm = *t; 2401 if (found_reverse_match) 2402 { 2403 /* If we found a reverse match we must alter the opcode 2404 direction bit. found_reverse_match holds bits to change 2405 (different for int & float insns). */ 2406 2407 i.tm.base_opcode ^= found_reverse_match; 2408 2409 i.tm.operand_types[0] = t->operand_types[1]; 2410 i.tm.operand_types[1] = t->operand_types[0]; 2411 } 2412 2413 return 1; 2414} 2415 2416static int 2417check_string () 2418{ 2419 int mem_op = (i.types[0] & AnyMem) ? 0 : 1; 2420 if ((i.tm.operand_types[mem_op] & EsSeg) != 0) 2421 { 2422 if (i.seg[0] != NULL && i.seg[0] != &es) 2423 { 2424 as_bad (_("`%s' operand %d must use `%%es' segment"), 2425 i.tm.name, 2426 mem_op + 1); 2427 return 0; 2428 } 2429 /* There's only ever one segment override allowed per instruction. 2430 This instruction possibly has a legal segment override on the 2431 second operand, so copy the segment to where non-string 2432 instructions store it, allowing common code. */ 2433 i.seg[0] = i.seg[1]; 2434 } 2435 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) 2436 { 2437 if (i.seg[1] != NULL && i.seg[1] != &es) 2438 { 2439 as_bad (_("`%s' operand %d must use `%%es' segment"), 2440 i.tm.name, 2441 mem_op + 2); 2442 return 0; 2443 } 2444 } 2445 return 1; 2446} 2447 2448static int 2449process_suffix (void) 2450{ 2451 /* If matched instruction specifies an explicit instruction mnemonic 2452 suffix, use it. */ 2453 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64)) 2454 { 2455 if (i.tm.opcode_modifier & Size16) 2456 i.suffix = WORD_MNEM_SUFFIX; 2457 else if (i.tm.opcode_modifier & Size64) 2458 i.suffix = QWORD_MNEM_SUFFIX; 2459 else 2460 i.suffix = LONG_MNEM_SUFFIX; 2461 } 2462 else if (i.reg_operands) 2463 { 2464 /* If there's no instruction mnemonic suffix we try to invent one 2465 based on register operands. */ 2466 if (!i.suffix) 2467 { 2468 /* We take i.suffix from the last register operand specified, 2469 Destination register type is more significant than source 2470 register type. */ 2471 int op; 2472 2473 for (op = i.operands; --op >= 0;) 2474 if ((i.types[op] & Reg) 2475 && !(i.tm.operand_types[op] & InOutPortReg)) 2476 { 2477 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : 2478 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : 2479 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : 2480 LONG_MNEM_SUFFIX); 2481 break; 2482 } 2483 } 2484 else if (i.suffix == BYTE_MNEM_SUFFIX) 2485 { 2486 if (!check_byte_reg ()) 2487 return 0; 2488 } 2489 else if (i.suffix == LONG_MNEM_SUFFIX) 2490 { 2491 if (!check_long_reg ()) 2492 return 0; 2493 } 2494 else if (i.suffix == QWORD_MNEM_SUFFIX) 2495 { 2496 if (!check_qword_reg ()) 2497 return 0; 2498 } 2499 else if (i.suffix == WORD_MNEM_SUFFIX) 2500 { 2501 if (!check_word_reg ()) 2502 return 0; 2503 } 2504 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) 2505 /* Do nothing if the instruction is going to ignore the prefix. */ 2506 ; 2507 else 2508 abort (); 2509 } 2510 else if ((i.tm.opcode_modifier & DefaultSize) 2511 && !i.suffix 2512 /* exclude fldenv/frstor/fsave/fstenv */ 2513 && (i.tm.opcode_modifier & No_sSuf)) 2514 { 2515 i.suffix = stackop_size; 2516 } 2517 else if (intel_syntax 2518 && !i.suffix 2519 && ((i.tm.operand_types[0] & JumpAbsolute) 2520 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment)) 2521 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ 2522 && i.tm.extension_opcode <= 3))) 2523 { 2524 switch (flag_code) 2525 { 2526 case CODE_64BIT: 2527 if (!(i.tm.opcode_modifier & No_qSuf)) 2528 { 2529 i.suffix = QWORD_MNEM_SUFFIX; 2530 break; 2531 } 2532 case CODE_32BIT: 2533 if (!(i.tm.opcode_modifier & No_lSuf)) 2534 i.suffix = LONG_MNEM_SUFFIX; 2535 break; 2536 case CODE_16BIT: 2537 if (!(i.tm.opcode_modifier & No_wSuf)) 2538 i.suffix = WORD_MNEM_SUFFIX; 2539 break; 2540 } 2541 } 2542 2543 if (!i.suffix) 2544 { 2545 if (!intel_syntax) 2546 { 2547 if (i.tm.opcode_modifier & W) 2548 { 2549 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); 2550 return 0; 2551 } 2552 } 2553 else 2554 { 2555 unsigned int suffixes = ~i.tm.opcode_modifier 2556 & (No_bSuf 2557 | No_wSuf 2558 | No_lSuf 2559 | No_sSuf 2560 | No_xSuf 2561 | No_qSuf); 2562 2563 if ((i.tm.opcode_modifier & W) 2564 || ((suffixes & (suffixes - 1)) 2565 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize)))) 2566 { 2567 as_bad (_("ambiguous operand size for `%s'"), i.tm.name); 2568 return 0; 2569 } 2570 } 2571 } 2572 2573 /* Change the opcode based on the operand size given by i.suffix; 2574 We don't need to change things for byte insns. */ 2575 2576 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) 2577 { 2578 /* It's not a byte, select word/dword operation. */ 2579 if (i.tm.opcode_modifier & W) 2580 { 2581 if (i.tm.opcode_modifier & ShortForm) 2582 i.tm.base_opcode |= 8; 2583 else 2584 i.tm.base_opcode |= 1; 2585 } 2586 2587 /* Now select between word & dword operations via the operand 2588 size prefix, except for instructions that will ignore this 2589 prefix anyway. */ 2590 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8) 2591 { 2592 /* monitor in SSE3 is a very special case. The default size 2593 of AX is the size of mode. The address size override 2594 prefix will change the size of AX. */ 2595 if (i.op->regs[0].reg_type & 2596 (flag_code == CODE_32BIT ? Reg16 : Reg32)) 2597 if (!add_prefix (ADDR_PREFIX_OPCODE)) 2598 return 0; 2599 } 2600 else if (i.suffix != QWORD_MNEM_SUFFIX 2601 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX 2602 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF)) 2603 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) 2604 || (flag_code == CODE_64BIT 2605 && (i.tm.opcode_modifier & JumpByte)))) 2606 { 2607 unsigned int prefix = DATA_PREFIX_OPCODE; 2608 2609 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ 2610 prefix = ADDR_PREFIX_OPCODE; 2611 2612 if (!add_prefix (prefix)) 2613 return 0; 2614 } 2615 2616 /* Set mode64 for an operand. */ 2617 if (i.suffix == QWORD_MNEM_SUFFIX 2618 && flag_code == CODE_64BIT 2619 && (i.tm.opcode_modifier & NoRex64) == 0) 2620 i.rex |= REX_MODE64; 2621 2622 /* Size floating point instruction. */ 2623 if (i.suffix == LONG_MNEM_SUFFIX) 2624 if (i.tm.opcode_modifier & FloatMF) 2625 i.tm.base_opcode ^= 4; 2626 } 2627 2628 return 1; 2629} 2630 2631static int 2632check_byte_reg (void) 2633{ 2634 int op; 2635 2636 for (op = i.operands; --op >= 0;) 2637 { 2638 /* If this is an eight bit register, it's OK. If it's the 16 or 2639 32 bit version of an eight bit register, we will just use the 2640 low portion, and that's OK too. */ 2641 if (i.types[op] & Reg8) 2642 continue; 2643 2644 /* movzx and movsx should not generate this warning. */ 2645 if (intel_syntax 2646 && (i.tm.base_opcode == 0xfb7 2647 || i.tm.base_opcode == 0xfb6 2648 || i.tm.base_opcode == 0x63 2649 || i.tm.base_opcode == 0xfbe 2650 || i.tm.base_opcode == 0xfbf)) 2651 continue; 2652 2653 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4) 2654 { 2655 /* Prohibit these changes in the 64bit mode, since the 2656 lowering is more complicated. */ 2657 if (flag_code == CODE_64BIT 2658 && (i.tm.operand_types[op] & InOutPortReg) == 0) 2659 { 2660 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2661 i.op[op].regs->reg_name, 2662 i.suffix); 2663 return 0; 2664 } 2665#if REGISTER_WARNINGS 2666 if (!quiet_warnings 2667 && (i.tm.operand_types[op] & InOutPortReg) == 0) 2668 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), 2669 (i.op[op].regs + (i.types[op] & Reg16 2670 ? REGNAM_AL - REGNAM_AX 2671 : REGNAM_AL - REGNAM_EAX))->reg_name, 2672 i.op[op].regs->reg_name, 2673 i.suffix); 2674#endif 2675 continue; 2676 } 2677 /* Any other register is bad. */ 2678 if (i.types[op] & (Reg | RegMMX | RegXMM 2679 | SReg2 | SReg3 2680 | Control | Debug | Test 2681 | FloatReg | FloatAcc)) 2682 { 2683 as_bad (_("`%%%s' not allowed with `%s%c'"), 2684 i.op[op].regs->reg_name, 2685 i.tm.name, 2686 i.suffix); 2687 return 0; 2688 } 2689 } 2690 return 1; 2691} 2692 2693static int 2694check_long_reg () 2695{ 2696 int op; 2697 2698 for (op = i.operands; --op >= 0;) 2699 /* Reject eight bit registers, except where the template requires 2700 them. (eg. movzb) */ 2701 if ((i.types[op] & Reg8) != 0 2702 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) 2703 { 2704 as_bad (_("`%%%s' not allowed with `%s%c'"), 2705 i.op[op].regs->reg_name, 2706 i.tm.name, 2707 i.suffix); 2708 return 0; 2709 } 2710 /* Warn if the e prefix on a general reg is missing. */ 2711 else if ((!quiet_warnings || flag_code == CODE_64BIT) 2712 && (i.types[op] & Reg16) != 0 2713 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) 2714 { 2715 /* Prohibit these changes in the 64bit mode, since the 2716 lowering is more complicated. */ 2717 if (flag_code == CODE_64BIT) 2718 { 2719 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2720 i.op[op].regs->reg_name, 2721 i.suffix); 2722 return 0; 2723 } 2724#if REGISTER_WARNINGS 2725 else 2726 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), 2727 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, 2728 i.op[op].regs->reg_name, 2729 i.suffix); 2730#endif 2731 } 2732 /* Warn if the r prefix on a general reg is missing. */ 2733 else if ((i.types[op] & Reg64) != 0 2734 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) 2735 { 2736 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2737 i.op[op].regs->reg_name, 2738 i.suffix); 2739 return 0; 2740 } 2741 return 1; 2742} 2743 2744static int 2745check_qword_reg () 2746{ 2747 int op; 2748 2749 for (op = i.operands; --op >= 0; ) 2750 /* Reject eight bit registers, except where the template requires 2751 them. (eg. movzb) */ 2752 if ((i.types[op] & Reg8) != 0 2753 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) 2754 { 2755 as_bad (_("`%%%s' not allowed with `%s%c'"), 2756 i.op[op].regs->reg_name, 2757 i.tm.name, 2758 i.suffix); 2759 return 0; 2760 } 2761 /* Warn if the e prefix on a general reg is missing. */ 2762 else if (((i.types[op] & Reg16) != 0 2763 || (i.types[op] & Reg32) != 0) 2764 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) 2765 { 2766 /* Prohibit these changes in the 64bit mode, since the 2767 lowering is more complicated. */ 2768 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2769 i.op[op].regs->reg_name, 2770 i.suffix); 2771 return 0; 2772 } 2773 return 1; 2774} 2775 2776static int 2777check_word_reg () 2778{ 2779 int op; 2780 for (op = i.operands; --op >= 0;) 2781 /* Reject eight bit registers, except where the template requires 2782 them. (eg. movzb) */ 2783 if ((i.types[op] & Reg8) != 0 2784 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) 2785 { 2786 as_bad (_("`%%%s' not allowed with `%s%c'"), 2787 i.op[op].regs->reg_name, 2788 i.tm.name, 2789 i.suffix); 2790 return 0; 2791 } 2792 /* Warn if the e prefix on a general reg is present. */ 2793 else if ((!quiet_warnings || flag_code == CODE_64BIT) 2794 && (i.types[op] & Reg32) != 0 2795 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0) 2796 { 2797 /* Prohibit these changes in the 64bit mode, since the 2798 lowering is more complicated. */ 2799 if (flag_code == CODE_64BIT) 2800 { 2801 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2802 i.op[op].regs->reg_name, 2803 i.suffix); 2804 return 0; 2805 } 2806 else 2807#if REGISTER_WARNINGS 2808 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), 2809 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, 2810 i.op[op].regs->reg_name, 2811 i.suffix); 2812#endif 2813 } 2814 return 1; 2815} 2816 2817static int 2818finalize_imm () 2819{ 2820 unsigned int overlap0, overlap1, overlap2; 2821 2822 overlap0 = i.types[0] & i.tm.operand_types[0]; 2823 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64)) 2824 && overlap0 != Imm8 && overlap0 != Imm8S 2825 && overlap0 != Imm16 && overlap0 != Imm32S 2826 && overlap0 != Imm32 && overlap0 != Imm64) 2827 { 2828 if (i.suffix) 2829 { 2830 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX 2831 ? Imm8 | Imm8S 2832 : (i.suffix == WORD_MNEM_SUFFIX 2833 ? Imm16 2834 : (i.suffix == QWORD_MNEM_SUFFIX 2835 ? Imm64 | Imm32S 2836 : Imm32))); 2837 } 2838 else if (overlap0 == (Imm16 | Imm32S | Imm32) 2839 || overlap0 == (Imm16 | Imm32) 2840 || overlap0 == (Imm16 | Imm32S)) 2841 { 2842 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) 2843 ? Imm16 : Imm32S); 2844 } 2845 if (overlap0 != Imm8 && overlap0 != Imm8S 2846 && overlap0 != Imm16 && overlap0 != Imm32S 2847 && overlap0 != Imm32 && overlap0 != Imm64) 2848 { 2849 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); 2850 return 0; 2851 } 2852 } 2853 i.types[0] = overlap0; 2854 2855 overlap1 = i.types[1] & i.tm.operand_types[1]; 2856 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64)) 2857 && overlap1 != Imm8 && overlap1 != Imm8S 2858 && overlap1 != Imm16 && overlap1 != Imm32S 2859 && overlap1 != Imm32 && overlap1 != Imm64) 2860 { 2861 if (i.suffix) 2862 { 2863 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX 2864 ? Imm8 | Imm8S 2865 : (i.suffix == WORD_MNEM_SUFFIX 2866 ? Imm16 2867 : (i.suffix == QWORD_MNEM_SUFFIX 2868 ? Imm64 | Imm32S 2869 : Imm32))); 2870 } 2871 else if (overlap1 == (Imm16 | Imm32 | Imm32S) 2872 || overlap1 == (Imm16 | Imm32) 2873 || overlap1 == (Imm16 | Imm32S)) 2874 { 2875 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) 2876 ? Imm16 : Imm32S); 2877 } 2878 if (overlap1 != Imm8 && overlap1 != Imm8S 2879 && overlap1 != Imm16 && overlap1 != Imm32S 2880 && overlap1 != Imm32 && overlap1 != Imm64) 2881 { 2882 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix); 2883 return 0; 2884 } 2885 } 2886 i.types[1] = overlap1; 2887 2888 overlap2 = i.types[2] & i.tm.operand_types[2]; 2889 assert ((overlap2 & Imm) == 0); 2890 i.types[2] = overlap2; 2891 2892 return 1; 2893} 2894 2895static int 2896process_operands () 2897{ 2898 /* Default segment register this instruction will use for memory 2899 accesses. 0 means unknown. This is only for optimizing out 2900 unnecessary segment overrides. */ 2901 const seg_entry *default_seg = 0; 2902 2903 /* The imul $imm, %reg instruction is converted into 2904 imul $imm, %reg, %reg, and the clr %reg instruction 2905 is converted into xor %reg, %reg. */ 2906 if (i.tm.opcode_modifier & regKludge) 2907 { 2908 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; 2909 /* Pretend we saw the extra register operand. */ 2910 assert (i.op[first_reg_op + 1].regs == 0); 2911 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; 2912 i.types[first_reg_op + 1] = i.types[first_reg_op]; 2913 i.reg_operands = 2; 2914 } 2915 2916 if (i.tm.opcode_modifier & ShortForm) 2917 { 2918 /* The register or float register operand is in operand 0 or 1. */ 2919 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; 2920 /* Register goes in low 3 bits of opcode. */ 2921 i.tm.base_opcode |= i.op[op].regs->reg_num; 2922 if ((i.op[op].regs->reg_flags & RegRex) != 0) 2923 i.rex |= REX_EXTZ; 2924 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) 2925 { 2926 /* Warn about some common errors, but press on regardless. 2927 The first case can be generated by gcc (<= 2.8.1). */ 2928 if (i.operands == 2) 2929 { 2930 /* Reversed arguments on faddp, fsubp, etc. */ 2931 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, 2932 i.op[1].regs->reg_name, 2933 i.op[0].regs->reg_name); 2934 } 2935 else 2936 { 2937 /* Extraneous `l' suffix on fp insn. */ 2938 as_warn (_("translating to `%s %%%s'"), i.tm.name, 2939 i.op[0].regs->reg_name); 2940 } 2941 } 2942 } 2943 else if (i.tm.opcode_modifier & Modrm) 2944 { 2945 /* The opcode is completed (modulo i.tm.extension_opcode which 2946 must be put into the modrm byte). Now, we make the modrm and 2947 index base bytes based on all the info we've collected. */ 2948 2949 default_seg = build_modrm_byte (); 2950 } 2951 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) 2952 { 2953 if (i.tm.base_opcode == POP_SEG_SHORT 2954 && i.op[0].regs->reg_num == 1) 2955 { 2956 as_bad (_("you can't `pop %%cs'")); 2957 return 0; 2958 } 2959 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); 2960 if ((i.op[0].regs->reg_flags & RegRex) != 0) 2961 i.rex |= REX_EXTZ; 2962 } 2963 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32) 2964 { 2965 default_seg = &ds; 2966 } 2967 else if ((i.tm.opcode_modifier & IsString) != 0) 2968 { 2969 /* For the string instructions that allow a segment override 2970 on one of their operands, the default segment is ds. */ 2971 default_seg = &ds; 2972 } 2973 2974 if ((i.tm.base_opcode == 0x8d /* lea */ 2975 || (i.tm.cpu_flags & CpuSVME)) 2976 && i.seg[0] && !quiet_warnings) 2977 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); 2978 2979 /* If a segment was explicitly specified, and the specified segment 2980 is not the default, use an opcode prefix to select it. If we 2981 never figured out what the default segment is, then default_seg 2982 will be zero at this point, and the specified segment prefix will 2983 always be used. */ 2984 if ((i.seg[0]) && (i.seg[0] != default_seg)) 2985 { 2986 if (!add_prefix (i.seg[0]->seg_prefix)) 2987 return 0; 2988 } 2989 return 1; 2990} 2991 2992static const seg_entry * 2993build_modrm_byte () 2994{ 2995 const seg_entry *default_seg = 0; 2996 2997 /* i.reg_operands MUST be the number of real register operands; 2998 implicit registers do not count. */ 2999 if (i.reg_operands == 2) 3000 { 3001 unsigned int source, dest; 3002 source = ((i.types[0] 3003 & (Reg | RegMMX | RegXMM 3004 | SReg2 | SReg3 3005 | Control | Debug | Test)) 3006 ? 0 : 1); 3007 dest = source + 1; 3008 3009 i.rm.mode = 3; 3010 /* One of the register operands will be encoded in the i.tm.reg 3011 field, the other in the combined i.tm.mode and i.tm.regmem 3012 fields. If no form of this instruction supports a memory 3013 destination operand, then we assume the source operand may 3014 sometimes be a memory operand and so we need to store the 3015 destination in the i.rm.reg field. */ 3016 if ((i.tm.operand_types[dest] & AnyMem) == 0) 3017 { 3018 i.rm.reg = i.op[dest].regs->reg_num; 3019 i.rm.regmem = i.op[source].regs->reg_num; 3020 if ((i.op[dest].regs->reg_flags & RegRex) != 0) 3021 i.rex |= REX_EXTX; 3022 if ((i.op[source].regs->reg_flags & RegRex) != 0) 3023 i.rex |= REX_EXTZ; 3024 } 3025 else 3026 { 3027 i.rm.reg = i.op[source].regs->reg_num; 3028 i.rm.regmem = i.op[dest].regs->reg_num; 3029 if ((i.op[dest].regs->reg_flags & RegRex) != 0) 3030 i.rex |= REX_EXTZ; 3031 if ((i.op[source].regs->reg_flags & RegRex) != 0) 3032 i.rex |= REX_EXTX; 3033 } 3034 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ))) 3035 { 3036 if (!((i.types[0] | i.types[1]) & Control)) 3037 abort (); 3038 i.rex &= ~(REX_EXTX | REX_EXTZ); 3039 add_prefix (LOCK_PREFIX_OPCODE); 3040 } 3041 } 3042 else 3043 { /* If it's not 2 reg operands... */ 3044 if (i.mem_operands) 3045 { 3046 unsigned int fake_zero_displacement = 0; 3047 unsigned int op = ((i.types[0] & AnyMem) 3048 ? 0 3049 : (i.types[1] & AnyMem) ? 1 : 2); 3050 3051 default_seg = &ds; 3052 3053 if (i.base_reg == 0) 3054 { 3055 i.rm.mode = 0; 3056 if (!i.disp_operands) 3057 fake_zero_displacement = 1; 3058 if (i.index_reg == 0) 3059 { 3060 /* Operand is just <disp> */ 3061 if (flag_code == CODE_64BIT) 3062 { 3063 /* 64bit mode overwrites the 32bit absolute 3064 addressing by RIP relative addressing and 3065 absolute addressing is encoded by one of the 3066 redundant SIB forms. */ 3067 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 3068 i.sib.base = NO_BASE_REGISTER; 3069 i.sib.index = NO_INDEX_REGISTER; 3070 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32); 3071 } 3072 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) 3073 { 3074 i.rm.regmem = NO_BASE_REGISTER_16; 3075 i.types[op] = Disp16; 3076 } 3077 else 3078 { 3079 i.rm.regmem = NO_BASE_REGISTER; 3080 i.types[op] = Disp32; 3081 } 3082 } 3083 else /* !i.base_reg && i.index_reg */ 3084 { 3085 i.sib.index = i.index_reg->reg_num; 3086 i.sib.base = NO_BASE_REGISTER; 3087 i.sib.scale = i.log2_scale_factor; 3088 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 3089 i.types[op] &= ~Disp; 3090 if (flag_code != CODE_64BIT) 3091 i.types[op] |= Disp32; /* Must be 32 bit */ 3092 else 3093 i.types[op] |= Disp32S; 3094 if ((i.index_reg->reg_flags & RegRex) != 0) 3095 i.rex |= REX_EXTY; 3096 } 3097 } 3098 /* RIP addressing for 64bit mode. */ 3099 else if (i.base_reg->reg_type == BaseIndex) 3100 { 3101 i.rm.regmem = NO_BASE_REGISTER; 3102 i.types[op] &= ~ Disp; 3103 i.types[op] |= Disp32S; 3104 i.flags[op] = Operand_PCrel; 3105 if (! i.disp_operands) 3106 fake_zero_displacement = 1; 3107 } 3108 else if (i.base_reg->reg_type & Reg16) 3109 { 3110 switch (i.base_reg->reg_num) 3111 { 3112 case 3: /* (%bx) */ 3113 if (i.index_reg == 0) 3114 i.rm.regmem = 7; 3115 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ 3116 i.rm.regmem = i.index_reg->reg_num - 6; 3117 break; 3118 case 5: /* (%bp) */ 3119 default_seg = &ss; 3120 if (i.index_reg == 0) 3121 { 3122 i.rm.regmem = 6; 3123 if ((i.types[op] & Disp) == 0) 3124 { 3125 /* fake (%bp) into 0(%bp) */ 3126 i.types[op] |= Disp8; 3127 fake_zero_displacement = 1; 3128 } 3129 } 3130 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ 3131 i.rm.regmem = i.index_reg->reg_num - 6 + 2; 3132 break; 3133 default: /* (%si) -> 4 or (%di) -> 5 */ 3134 i.rm.regmem = i.base_reg->reg_num - 6 + 4; 3135 } 3136 i.rm.mode = mode_from_disp_size (i.types[op]); 3137 } 3138 else /* i.base_reg and 32/64 bit mode */ 3139 { 3140 if (flag_code == CODE_64BIT 3141 && (i.types[op] & Disp)) 3142 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32); 3143 3144 i.rm.regmem = i.base_reg->reg_num; 3145 if ((i.base_reg->reg_flags & RegRex) != 0) 3146 i.rex |= REX_EXTZ; 3147 i.sib.base = i.base_reg->reg_num; 3148 /* x86-64 ignores REX prefix bit here to avoid decoder 3149 complications. */ 3150 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) 3151 { 3152 default_seg = &ss; 3153 if (i.disp_operands == 0) 3154 { 3155 fake_zero_displacement = 1; 3156 i.types[op] |= Disp8; 3157 } 3158 } 3159 else if (i.base_reg->reg_num == ESP_REG_NUM) 3160 { 3161 default_seg = &ss; 3162 } 3163 i.sib.scale = i.log2_scale_factor; 3164 if (i.index_reg == 0) 3165 { 3166 /* <disp>(%esp) becomes two byte modrm with no index 3167 register. We've already stored the code for esp 3168 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. 3169 Any base register besides %esp will not use the 3170 extra modrm byte. */ 3171 i.sib.index = NO_INDEX_REGISTER; 3172#if !SCALE1_WHEN_NO_INDEX 3173 /* Another case where we force the second modrm byte. */ 3174 if (i.log2_scale_factor) 3175 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 3176#endif 3177 } 3178 else 3179 { 3180 i.sib.index = i.index_reg->reg_num; 3181 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 3182 if ((i.index_reg->reg_flags & RegRex) != 0) 3183 i.rex |= REX_EXTY; 3184 } 3185 3186 if (i.disp_operands 3187 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL 3188 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) 3189 i.rm.mode = 0; 3190 else 3191 i.rm.mode = mode_from_disp_size (i.types[op]); 3192 } 3193 3194 if (fake_zero_displacement) 3195 { 3196 /* Fakes a zero displacement assuming that i.types[op] 3197 holds the correct displacement size. */ 3198 expressionS *exp; 3199 3200 assert (i.op[op].disps == 0); 3201 exp = &disp_expressions[i.disp_operands++]; 3202 i.op[op].disps = exp; 3203 exp->X_op = O_constant; 3204 exp->X_add_number = 0; 3205 exp->X_add_symbol = (symbolS *) 0; 3206 exp->X_op_symbol = (symbolS *) 0; 3207 } 3208 } 3209 3210 /* Fill in i.rm.reg or i.rm.regmem field with register operand 3211 (if any) based on i.tm.extension_opcode. Again, we must be 3212 careful to make sure that segment/control/debug/test/MMX 3213 registers are coded into the i.rm.reg field. */ 3214 if (i.reg_operands) 3215 { 3216 unsigned int op = 3217 ((i.types[0] 3218 & (Reg | RegMMX | RegXMM 3219 | SReg2 | SReg3 3220 | Control | Debug | Test)) 3221 ? 0 3222 : ((i.types[1] 3223 & (Reg | RegMMX | RegXMM 3224 | SReg2 | SReg3 3225 | Control | Debug | Test)) 3226 ? 1 3227 : 2)); 3228 /* If there is an extension opcode to put here, the register 3229 number must be put into the regmem field. */ 3230 if (i.tm.extension_opcode != None) 3231 { 3232 i.rm.regmem = i.op[op].regs->reg_num; 3233 if ((i.op[op].regs->reg_flags & RegRex) != 0) 3234 i.rex |= REX_EXTZ; 3235 } 3236 else 3237 { 3238 i.rm.reg = i.op[op].regs->reg_num; 3239 if ((i.op[op].regs->reg_flags & RegRex) != 0) 3240 i.rex |= REX_EXTX; 3241 } 3242 3243 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we 3244 must set it to 3 to indicate this is a register operand 3245 in the regmem field. */ 3246 if (!i.mem_operands) 3247 i.rm.mode = 3; 3248 } 3249 3250 /* Fill in i.rm.reg field with extension opcode (if any). */ 3251 if (i.tm.extension_opcode != None) 3252 i.rm.reg = i.tm.extension_opcode; 3253 } 3254 return default_seg; 3255} 3256 3257static void 3258output_branch () 3259{ 3260 char *p; 3261 int code16; 3262 int prefix; 3263 relax_substateT subtype; 3264 symbolS *sym; 3265 offsetT off; 3266 3267 code16 = 0; 3268 if (flag_code == CODE_16BIT) 3269 code16 = CODE16; 3270 3271 prefix = 0; 3272 if (i.prefix[DATA_PREFIX] != 0) 3273 { 3274 prefix = 1; 3275 i.prefixes -= 1; 3276 code16 ^= CODE16; 3277 } 3278 /* Pentium4 branch hints. */ 3279 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ 3280 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) 3281 { 3282 prefix++; 3283 i.prefixes--; 3284 } 3285 if (i.prefix[REX_PREFIX] != 0) 3286 { 3287 prefix++; 3288 i.prefixes--; 3289 } 3290 3291 if (i.prefixes != 0 && !intel_syntax) 3292 as_warn (_("skipping prefixes on this instruction")); 3293 3294 /* It's always a symbol; End frag & setup for relax. 3295 Make sure there is enough room in this frag for the largest 3296 instruction we may generate in md_convert_frag. This is 2 3297 bytes for the opcode and room for the prefix and largest 3298 displacement. */ 3299 frag_grow (prefix + 2 + 4); 3300 /* Prefix and 1 opcode byte go in fr_fix. */ 3301 p = frag_more (prefix + 1); 3302 if (i.prefix[DATA_PREFIX] != 0) 3303 *p++ = DATA_PREFIX_OPCODE; 3304 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE 3305 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) 3306 *p++ = i.prefix[SEG_PREFIX]; 3307 if (i.prefix[REX_PREFIX] != 0) 3308 *p++ = i.prefix[REX_PREFIX]; 3309 *p = i.tm.base_opcode; 3310 3311 if ((unsigned char) *p == JUMP_PC_RELATIVE) 3312 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); 3313 else if ((cpu_arch_flags & Cpu386) != 0) 3314 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); 3315 else 3316 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); 3317 subtype |= code16; 3318 3319 sym = i.op[0].disps->X_add_symbol; 3320 off = i.op[0].disps->X_add_number; 3321 3322 if (i.op[0].disps->X_op != O_constant 3323 && i.op[0].disps->X_op != O_symbol) 3324 { 3325 /* Handle complex expressions. */ 3326 sym = make_expr_symbol (i.op[0].disps); 3327 off = 0; 3328 } 3329 3330 /* 1 possible extra opcode + 4 byte displacement go in var part. 3331 Pass reloc in fr_var. */ 3332 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); 3333} 3334 3335static void 3336output_jump () 3337{ 3338 char *p; 3339 int size; 3340 fixS *fixP; 3341 3342 if (i.tm.opcode_modifier & JumpByte) 3343 { 3344 /* This is a loop or jecxz type instruction. */ 3345 size = 1; 3346 if (i.prefix[ADDR_PREFIX] != 0) 3347 { 3348 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); 3349 i.prefixes -= 1; 3350 } 3351 /* Pentium4 branch hints. */ 3352 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ 3353 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) 3354 { 3355 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); 3356 i.prefixes--; 3357 } 3358 } 3359 else 3360 { 3361 int code16; 3362 3363 code16 = 0; 3364 if (flag_code == CODE_16BIT) 3365 code16 = CODE16; 3366 3367 if (i.prefix[DATA_PREFIX] != 0) 3368 { 3369 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); 3370 i.prefixes -= 1; 3371 code16 ^= CODE16; 3372 } 3373 3374 size = 4; 3375 if (code16) 3376 size = 2; 3377 } 3378 3379 if (i.prefix[REX_PREFIX] != 0) 3380 { 3381 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); 3382 i.prefixes -= 1; 3383 } 3384 3385 if (i.prefixes != 0 && !intel_syntax) 3386 as_warn (_("skipping prefixes on this instruction")); 3387 3388 p = frag_more (1 + size); 3389 *p++ = i.tm.base_opcode; 3390 3391 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, 3392 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); 3393 3394 /* All jumps handled here are signed, but don't use a signed limit 3395 check for 32 and 16 bit jumps as we want to allow wrap around at 3396 4G and 64k respectively. */ 3397 if (size == 1) 3398 fixP->fx_signed = 1; 3399} 3400 3401static void 3402output_interseg_jump () 3403{ 3404 char *p; 3405 int size; 3406 int prefix; 3407 int code16; 3408 3409 code16 = 0; 3410 if (flag_code == CODE_16BIT) 3411 code16 = CODE16; 3412 3413 prefix = 0; 3414 if (i.prefix[DATA_PREFIX] != 0) 3415 { 3416 prefix = 1; 3417 i.prefixes -= 1; 3418 code16 ^= CODE16; 3419 } 3420 if (i.prefix[REX_PREFIX] != 0) 3421 { 3422 prefix++; 3423 i.prefixes -= 1; 3424 } 3425 3426 size = 4; 3427 if (code16) 3428 size = 2; 3429 3430 if (i.prefixes != 0 && !intel_syntax) 3431 as_warn (_("skipping prefixes on this instruction")); 3432 3433 /* 1 opcode; 2 segment; offset */ 3434 p = frag_more (prefix + 1 + 2 + size); 3435 3436 if (i.prefix[DATA_PREFIX] != 0) 3437 *p++ = DATA_PREFIX_OPCODE; 3438 3439 if (i.prefix[REX_PREFIX] != 0) 3440 *p++ = i.prefix[REX_PREFIX]; 3441 3442 *p++ = i.tm.base_opcode; 3443 if (i.op[1].imms->X_op == O_constant) 3444 { 3445 offsetT n = i.op[1].imms->X_add_number; 3446 3447 if (size == 2 3448 && !fits_in_unsigned_word (n) 3449 && !fits_in_signed_word (n)) 3450 { 3451 as_bad (_("16-bit jump out of range")); 3452 return; 3453 } 3454 md_number_to_chars (p, n, size); 3455 } 3456 else 3457 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 3458 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); 3459 if (i.op[0].imms->X_op != O_constant) 3460 as_bad (_("can't handle non absolute segment in `%s'"), 3461 i.tm.name); 3462 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); 3463} 3464 3465static void 3466output_insn () 3467{ 3468 fragS *insn_start_frag; 3469 offsetT insn_start_off; 3470 3471 /* Tie dwarf2 debug info to the address at the start of the insn. 3472 We can't do this after the insn has been output as the current 3473 frag may have been closed off. eg. by frag_var. */ 3474 dwarf2_emit_insn (0); 3475 3476 insn_start_frag = frag_now; 3477 insn_start_off = frag_now_fix (); 3478 3479 /* Output jumps. */ 3480 if (i.tm.opcode_modifier & Jump) 3481 output_branch (); 3482 else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) 3483 output_jump (); 3484 else if (i.tm.opcode_modifier & JumpInterSegment) 3485 output_interseg_jump (); 3486 else 3487 { 3488 /* Output normal instructions here. */ 3489 char *p; 3490 unsigned char *q; 3491 unsigned int prefix; 3492 3493 /* All opcodes on i386 have either 1 or 2 bytes. Merom New 3494 Instructions have 3 bytes. We may use one more higher byte 3495 to specify a prefix the instruction requires. */ 3496 if ((i.tm.cpu_flags & CpuMNI) != 0) 3497 { 3498 if (i.tm.base_opcode & 0xff000000) 3499 { 3500 prefix = (i.tm.base_opcode >> 24) & 0xff; 3501 goto check_prefix; 3502 } 3503 } 3504 else if ((i.tm.base_opcode & 0xff0000) != 0) 3505 { 3506 prefix = (i.tm.base_opcode >> 16) & 0xff; 3507 if ((i.tm.cpu_flags & CpuPadLock) != 0) 3508 { 3509check_prefix: 3510 if (prefix != REPE_PREFIX_OPCODE 3511 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE) 3512 add_prefix (prefix); 3513 } 3514 else 3515 add_prefix (prefix); 3516 } 3517 3518 /* The prefix bytes. */ 3519 for (q = i.prefix; 3520 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); 3521 q++) 3522 { 3523 if (*q) 3524 { 3525 p = frag_more (1); 3526 md_number_to_chars (p, (valueT) *q, 1); 3527 } 3528 } 3529 3530 /* Now the opcode; be careful about word order here! */ 3531 if (fits_in_unsigned_byte (i.tm.base_opcode)) 3532 { 3533 FRAG_APPEND_1_CHAR (i.tm.base_opcode); 3534 } 3535 else 3536 { 3537 if ((i.tm.cpu_flags & CpuMNI) != 0) 3538 { 3539 p = frag_more (3); 3540 *p++ = (i.tm.base_opcode >> 16) & 0xff; 3541 } 3542 else 3543 p = frag_more (2); 3544 3545 /* Put out high byte first: can't use md_number_to_chars! */ 3546 *p++ = (i.tm.base_opcode >> 8) & 0xff; 3547 *p = i.tm.base_opcode & 0xff; 3548 } 3549 3550 /* Now the modrm byte and sib byte (if present). */ 3551 if (i.tm.opcode_modifier & Modrm) 3552 { 3553 p = frag_more (1); 3554 md_number_to_chars (p, 3555 (valueT) (i.rm.regmem << 0 3556 | i.rm.reg << 3 3557 | i.rm.mode << 6), 3558 1); 3559 /* If i.rm.regmem == ESP (4) 3560 && i.rm.mode != (Register mode) 3561 && not 16 bit 3562 ==> need second modrm byte. */ 3563 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING 3564 && i.rm.mode != 3 3565 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) 3566 { 3567 p = frag_more (1); 3568 md_number_to_chars (p, 3569 (valueT) (i.sib.base << 0 3570 | i.sib.index << 3 3571 | i.sib.scale << 6), 3572 1); 3573 } 3574 } 3575 3576 if (i.disp_operands) 3577 output_disp (insn_start_frag, insn_start_off); 3578 3579 if (i.imm_operands) 3580 output_imm (insn_start_frag, insn_start_off); 3581 } 3582 3583#ifdef DEBUG386 3584 if (flag_debug) 3585 { 3586 pi ("" /*line*/, &i); 3587 } 3588#endif /* DEBUG386 */ 3589} 3590 3591static void 3592output_disp (insn_start_frag, insn_start_off) 3593 fragS *insn_start_frag; 3594 offsetT insn_start_off; 3595{ 3596 char *p; 3597 unsigned int n; 3598 3599 for (n = 0; n < i.operands; n++) 3600 { 3601 if (i.types[n] & Disp) 3602 { 3603 if (i.op[n].disps->X_op == O_constant) 3604 { 3605 int size; 3606 offsetT val; 3607 3608 size = 4; 3609 if (i.types[n] & (Disp8 | Disp16 | Disp64)) 3610 { 3611 size = 2; 3612 if (i.types[n] & Disp8) 3613 size = 1; 3614 if (i.types[n] & Disp64) 3615 size = 8; 3616 } 3617 val = offset_in_range (i.op[n].disps->X_add_number, 3618 size); 3619 p = frag_more (size); 3620 md_number_to_chars (p, val, size); 3621 } 3622 else 3623 { 3624 enum bfd_reloc_code_real reloc_type; 3625 int size = 4; 3626 int sign = 0; 3627 int pcrel = (i.flags[n] & Operand_PCrel) != 0; 3628 3629 /* The PC relative address is computed relative 3630 to the instruction boundary, so in case immediate 3631 fields follows, we need to adjust the value. */ 3632 if (pcrel && i.imm_operands) 3633 { 3634 int imm_size = 4; 3635 unsigned int n1; 3636 3637 for (n1 = 0; n1 < i.operands; n1++) 3638 if (i.types[n1] & Imm) 3639 { 3640 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64)) 3641 { 3642 imm_size = 2; 3643 if (i.types[n1] & (Imm8 | Imm8S)) 3644 imm_size = 1; 3645 if (i.types[n1] & Imm64) 3646 imm_size = 8; 3647 } 3648 break; 3649 } 3650 /* We should find the immediate. */ 3651 if (n1 == i.operands) 3652 abort (); 3653 i.op[n].disps->X_add_number -= imm_size; 3654 } 3655 3656 if (i.types[n] & Disp32S) 3657 sign = 1; 3658 3659 if (i.types[n] & (Disp16 | Disp64)) 3660 { 3661 size = 2; 3662 if (i.types[n] & Disp64) 3663 size = 8; 3664 } 3665 3666 p = frag_more (size); 3667 reloc_type = reloc (size, pcrel, sign, i.reloc[n]); 3668 if (GOT_symbol 3669 && GOT_symbol == i.op[n].disps->X_add_symbol 3670 && (((reloc_type == BFD_RELOC_32 3671 || reloc_type == BFD_RELOC_X86_64_32S 3672 || (reloc_type == BFD_RELOC_64 3673 && object_64bit)) 3674 && (i.op[n].disps->X_op == O_symbol 3675 || (i.op[n].disps->X_op == O_add 3676 && ((symbol_get_value_expression 3677 (i.op[n].disps->X_op_symbol)->X_op) 3678 == O_subtract)))) 3679 || reloc_type == BFD_RELOC_32_PCREL)) 3680 { 3681 offsetT add; 3682 3683 if (insn_start_frag == frag_now) 3684 add = (p - frag_now->fr_literal) - insn_start_off; 3685 else 3686 { 3687 fragS *fr; 3688 3689 add = insn_start_frag->fr_fix - insn_start_off; 3690 for (fr = insn_start_frag->fr_next; 3691 fr && fr != frag_now; fr = fr->fr_next) 3692 add += fr->fr_fix; 3693 add += p - frag_now->fr_literal; 3694 } 3695 3696 if (!object_64bit) 3697 { 3698 reloc_type = BFD_RELOC_386_GOTPC; 3699 i.op[n].imms->X_add_number += add; 3700 } 3701 else if (reloc_type == BFD_RELOC_64) 3702 reloc_type = BFD_RELOC_X86_64_GOTPC64; 3703 else 3704 /* Don't do the adjustment for x86-64, as there 3705 the pcrel addressing is relative to the _next_ 3706 insn, and that is taken care of in other code. */ 3707 reloc_type = BFD_RELOC_X86_64_GOTPC32; 3708 } 3709 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 3710 i.op[n].disps, pcrel, reloc_type); 3711 } 3712 } 3713 } 3714} 3715 3716static void 3717output_imm (insn_start_frag, insn_start_off) 3718 fragS *insn_start_frag; 3719 offsetT insn_start_off; 3720{ 3721 char *p; 3722 unsigned int n; 3723 3724 for (n = 0; n < i.operands; n++) 3725 { 3726 if (i.types[n] & Imm) 3727 { 3728 if (i.op[n].imms->X_op == O_constant) 3729 { 3730 int size; 3731 offsetT val; 3732 3733 size = 4; 3734 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) 3735 { 3736 size = 2; 3737 if (i.types[n] & (Imm8 | Imm8S)) 3738 size = 1; 3739 else if (i.types[n] & Imm64) 3740 size = 8; 3741 } 3742 val = offset_in_range (i.op[n].imms->X_add_number, 3743 size); 3744 p = frag_more (size); 3745 md_number_to_chars (p, val, size); 3746 } 3747 else 3748 { 3749 /* Not absolute_section. 3750 Need a 32-bit fixup (don't support 8bit 3751 non-absolute imms). Try to support other 3752 sizes ... */ 3753 enum bfd_reloc_code_real reloc_type; 3754 int size = 4; 3755 int sign = 0; 3756 3757 if ((i.types[n] & (Imm32S)) 3758 && (i.suffix == QWORD_MNEM_SUFFIX 3759 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf)))) 3760 sign = 1; 3761 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) 3762 { 3763 size = 2; 3764 if (i.types[n] & (Imm8 | Imm8S)) 3765 size = 1; 3766 if (i.types[n] & Imm64) 3767 size = 8; 3768 } 3769 3770 p = frag_more (size); 3771 reloc_type = reloc (size, 0, sign, i.reloc[n]); 3772 3773 /* This is tough to explain. We end up with this one if we 3774 * have operands that look like 3775 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to 3776 * obtain the absolute address of the GOT, and it is strongly 3777 * preferable from a performance point of view to avoid using 3778 * a runtime relocation for this. The actual sequence of 3779 * instructions often look something like: 3780 * 3781 * call .L66 3782 * .L66: 3783 * popl %ebx 3784 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx 3785 * 3786 * The call and pop essentially return the absolute address 3787 * of the label .L66 and store it in %ebx. The linker itself 3788 * will ultimately change the first operand of the addl so 3789 * that %ebx points to the GOT, but to keep things simple, the 3790 * .o file must have this operand set so that it generates not 3791 * the absolute address of .L66, but the absolute address of 3792 * itself. This allows the linker itself simply treat a GOTPC 3793 * relocation as asking for a pcrel offset to the GOT to be 3794 * added in, and the addend of the relocation is stored in the 3795 * operand field for the instruction itself. 3796 * 3797 * Our job here is to fix the operand so that it would add 3798 * the correct offset so that %ebx would point to itself. The 3799 * thing that is tricky is that .-.L66 will point to the 3800 * beginning of the instruction, so we need to further modify 3801 * the operand so that it will point to itself. There are 3802 * other cases where you have something like: 3803 * 3804 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] 3805 * 3806 * and here no correction would be required. Internally in 3807 * the assembler we treat operands of this form as not being 3808 * pcrel since the '.' is explicitly mentioned, and I wonder 3809 * whether it would simplify matters to do it this way. Who 3810 * knows. In earlier versions of the PIC patches, the 3811 * pcrel_adjust field was used to store the correction, but 3812 * since the expression is not pcrel, I felt it would be 3813 * confusing to do it this way. */ 3814 3815 if ((reloc_type == BFD_RELOC_32 3816 || reloc_type == BFD_RELOC_X86_64_32S 3817 || reloc_type == BFD_RELOC_64) 3818 && GOT_symbol 3819 && GOT_symbol == i.op[n].imms->X_add_symbol 3820 && (i.op[n].imms->X_op == O_symbol 3821 || (i.op[n].imms->X_op == O_add 3822 && ((symbol_get_value_expression 3823 (i.op[n].imms->X_op_symbol)->X_op) 3824 == O_subtract)))) 3825 { 3826 offsetT add; 3827 3828 if (insn_start_frag == frag_now) 3829 add = (p - frag_now->fr_literal) - insn_start_off; 3830 else 3831 { 3832 fragS *fr; 3833 3834 add = insn_start_frag->fr_fix - insn_start_off; 3835 for (fr = insn_start_frag->fr_next; 3836 fr && fr != frag_now; fr = fr->fr_next) 3837 add += fr->fr_fix; 3838 add += p - frag_now->fr_literal; 3839 } 3840 3841 if (!object_64bit) 3842 reloc_type = BFD_RELOC_386_GOTPC; 3843 else if (size == 4) 3844 reloc_type = BFD_RELOC_X86_64_GOTPC32; 3845 else if (size == 8) 3846 reloc_type = BFD_RELOC_X86_64_GOTPC64; 3847 i.op[n].imms->X_add_number += add; 3848 } 3849 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 3850 i.op[n].imms, 0, reloc_type); 3851 } 3852 } 3853 } 3854} 3855 3856/* x86_cons_fix_new is called via the expression parsing code when a 3857 reloc is needed. We use this hook to get the correct .got reloc. */ 3858static enum bfd_reloc_code_real got_reloc = NO_RELOC; 3859static int cons_sign = -1; 3860 3861void 3862x86_cons_fix_new (fragS *frag, 3863 unsigned int off, 3864 unsigned int len, 3865 expressionS *exp) 3866{ 3867 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); 3868 3869 got_reloc = NO_RELOC; 3870 3871#ifdef TE_PE 3872 if (exp->X_op == O_secrel) 3873 { 3874 exp->X_op = O_symbol; 3875 r = BFD_RELOC_32_SECREL; 3876 } 3877#endif 3878 3879 fix_new_exp (frag, off, len, exp, 0, r); 3880} 3881 3882#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT) 3883# define lex_got(reloc, adjust, types) NULL 3884#else 3885/* Parse operands of the form 3886 <symbol>@GOTOFF+<nnn> 3887 and similar .plt or .got references. 3888 3889 If we find one, set up the correct relocation in RELOC and copy the 3890 input string, minus the `@GOTOFF' into a malloc'd buffer for 3891 parsing by the calling routine. Return this buffer, and if ADJUST 3892 is non-null set it to the length of the string we removed from the 3893 input line. Otherwise return NULL. */ 3894static char * 3895lex_got (enum bfd_reloc_code_real *reloc, 3896 int *adjust, 3897 unsigned int *types) 3898{ 3899 /* Some of the relocations depend on the size of what field is to 3900 be relocated. But in our callers i386_immediate and i386_displacement 3901 we don't yet know the operand size (this will be set by insn 3902 matching). Hence we record the word32 relocation here, 3903 and adjust the reloc according to the real size in reloc(). */ 3904 static const struct { 3905 const char *str; 3906 const enum bfd_reloc_code_real rel[2]; 3907 const unsigned int types64; 3908 } gotrel[] = { 3909 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 }, 3910 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 }, 3911 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 }, 3912 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 }, 3913 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 }, 3914 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 }, 3915 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 }, 3916 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 }, 3917 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 }, 3918 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 }, 3919 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 }, 3920 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 }, 3921 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 }, 3922 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 }, 3923 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 }, 3924 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 }, 3925 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 } 3926 }; 3927 char *cp; 3928 unsigned int j; 3929 3930 if (!IS_ELF) 3931 return NULL; 3932 3933 for (cp = input_line_pointer; *cp != '@'; cp++) 3934 if (is_end_of_line[(unsigned char) *cp]) 3935 return NULL; 3936 3937 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++) 3938 { 3939 int len; 3940 3941 len = strlen (gotrel[j].str); 3942 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) 3943 { 3944 if (gotrel[j].rel[object_64bit] != 0) 3945 { 3946 int first, second; 3947 char *tmpbuf, *past_reloc; 3948 3949 *reloc = gotrel[j].rel[object_64bit]; 3950 if (adjust) 3951 *adjust = len; 3952 3953 if (types) 3954 { 3955 if (flag_code != CODE_64BIT) 3956 *types = Imm32|Disp32; 3957 else 3958 *types = gotrel[j].types64; 3959 } 3960 3961 if (GOT_symbol == NULL) 3962 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 3963 3964 /* Replace the relocation token with ' ', so that 3965 errors like foo@GOTOFF1 will be detected. */ 3966 3967 /* The length of the first part of our input line. */ 3968 first = cp - input_line_pointer; 3969 3970 /* The second part goes from after the reloc token until 3971 (and including) an end_of_line char. Don't use strlen 3972 here as the end_of_line char may not be a NUL. */ 3973 past_reloc = cp + 1 + len; 3974 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; ) 3975 ; 3976 second = cp - past_reloc; 3977 3978 /* Allocate and copy string. The trailing NUL shouldn't 3979 be necessary, but be safe. */ 3980 tmpbuf = xmalloc (first + second + 2); 3981 memcpy (tmpbuf, input_line_pointer, first); 3982 tmpbuf[first] = ' '; 3983 memcpy (tmpbuf + first + 1, past_reloc, second); 3984 tmpbuf[first + second + 1] = '\0'; 3985 return tmpbuf; 3986 } 3987 3988 as_bad (_("@%s reloc is not supported with %d-bit output format"), 3989 gotrel[j].str, 1 << (5 + object_64bit)); 3990 return NULL; 3991 } 3992 } 3993 3994 /* Might be a symbol version string. Don't as_bad here. */ 3995 return NULL; 3996} 3997 3998void 3999x86_cons (exp, size) 4000 expressionS *exp; 4001 int size; 4002{ 4003 if (size == 4 || (object_64bit && size == 8)) 4004 { 4005 /* Handle @GOTOFF and the like in an expression. */ 4006 char *save; 4007 char *gotfree_input_line; 4008 int adjust; 4009 4010 save = input_line_pointer; 4011 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); 4012 if (gotfree_input_line) 4013 input_line_pointer = gotfree_input_line; 4014 4015 expression (exp); 4016 4017 if (gotfree_input_line) 4018 { 4019 /* expression () has merrily parsed up to the end of line, 4020 or a comma - in the wrong buffer. Transfer how far 4021 input_line_pointer has moved to the right buffer. */ 4022 input_line_pointer = (save 4023 + (input_line_pointer - gotfree_input_line) 4024 + adjust); 4025 free (gotfree_input_line); 4026 } 4027 } 4028 else 4029 expression (exp); 4030} 4031#endif 4032 4033static void signed_cons (int size) 4034{ 4035 if (flag_code == CODE_64BIT) 4036 cons_sign = 1; 4037 cons (size); 4038 cons_sign = -1; 4039} 4040 4041#ifdef TE_PE 4042static void 4043pe_directive_secrel (dummy) 4044 int dummy ATTRIBUTE_UNUSED; 4045{ 4046 expressionS exp; 4047 4048 do 4049 { 4050 expression (&exp); 4051 if (exp.X_op == O_symbol) 4052 exp.X_op = O_secrel; 4053 4054 emit_expr (&exp, 4); 4055 } 4056 while (*input_line_pointer++ == ','); 4057 4058 input_line_pointer--; 4059 demand_empty_rest_of_line (); 4060} 4061#endif 4062 4063static int i386_immediate PARAMS ((char *)); 4064 4065static int 4066i386_immediate (imm_start) 4067 char *imm_start; 4068{ 4069 char *save_input_line_pointer; 4070 char *gotfree_input_line; 4071 segT exp_seg = 0; 4072 expressionS *exp; 4073 unsigned int types = ~0U; 4074 4075 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) 4076 { 4077 as_bad (_("only 1 or 2 immediate operands are allowed")); 4078 return 0; 4079 } 4080 4081 exp = &im_expressions[i.imm_operands++]; 4082 i.op[this_operand].imms = exp; 4083 4084 if (is_space_char (*imm_start)) 4085 ++imm_start; 4086 4087 save_input_line_pointer = input_line_pointer; 4088 input_line_pointer = imm_start; 4089 4090 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); 4091 if (gotfree_input_line) 4092 input_line_pointer = gotfree_input_line; 4093 4094 exp_seg = expression (exp); 4095 4096 SKIP_WHITESPACE (); 4097 if (*input_line_pointer) 4098 as_bad (_("junk `%s' after expression"), input_line_pointer); 4099 4100 input_line_pointer = save_input_line_pointer; 4101 if (gotfree_input_line) 4102 free (gotfree_input_line); 4103 4104 if (exp->X_op == O_absent || exp->X_op == O_big) 4105 { 4106 /* Missing or bad expr becomes absolute 0. */ 4107 as_bad (_("missing or invalid immediate expression `%s' taken as 0"), 4108 imm_start); 4109 exp->X_op = O_constant; 4110 exp->X_add_number = 0; 4111 exp->X_add_symbol = (symbolS *) 0; 4112 exp->X_op_symbol = (symbolS *) 0; 4113 } 4114 else if (exp->X_op == O_constant) 4115 { 4116 /* Size it properly later. */ 4117 i.types[this_operand] |= Imm64; 4118 /* If BFD64, sign extend val. */ 4119 if (!use_rela_relocations) 4120 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) 4121 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); 4122 } 4123#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 4124 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour 4125 && exp_seg != absolute_section 4126 && exp_seg != text_section 4127 && exp_seg != data_section 4128 && exp_seg != bss_section 4129 && exp_seg != undefined_section 4130 && !bfd_is_com_section (exp_seg)) 4131 { 4132 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 4133 return 0; 4134 } 4135#endif 4136 else 4137 { 4138 /* This is an address. The size of the address will be 4139 determined later, depending on destination register, 4140 suffix, or the default for the section. */ 4141 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64; 4142 i.types[this_operand] &= types; 4143 } 4144 4145 return 1; 4146} 4147 4148static char *i386_scale PARAMS ((char *)); 4149 4150static char * 4151i386_scale (scale) 4152 char *scale; 4153{ 4154 offsetT val; 4155 char *save = input_line_pointer; 4156 4157 input_line_pointer = scale; 4158 val = get_absolute_expression (); 4159 4160 switch (val) 4161 { 4162 case 1: 4163 i.log2_scale_factor = 0; 4164 break; 4165 case 2: 4166 i.log2_scale_factor = 1; 4167 break; 4168 case 4: 4169 i.log2_scale_factor = 2; 4170 break; 4171 case 8: 4172 i.log2_scale_factor = 3; 4173 break; 4174 default: 4175 { 4176 char sep = *input_line_pointer; 4177 4178 *input_line_pointer = '\0'; 4179 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), 4180 scale); 4181 *input_line_pointer = sep; 4182 input_line_pointer = save; 4183 return NULL; 4184 } 4185 } 4186 if (i.log2_scale_factor != 0 && i.index_reg == 0) 4187 { 4188 as_warn (_("scale factor of %d without an index register"), 4189 1 << i.log2_scale_factor); 4190#if SCALE1_WHEN_NO_INDEX 4191 i.log2_scale_factor = 0; 4192#endif 4193 } 4194 scale = input_line_pointer; 4195 input_line_pointer = save; 4196 return scale; 4197} 4198 4199static int i386_displacement PARAMS ((char *, char *)); 4200 4201static int 4202i386_displacement (disp_start, disp_end) 4203 char *disp_start; 4204 char *disp_end; 4205{ 4206 expressionS *exp; 4207 segT exp_seg = 0; 4208 char *save_input_line_pointer; 4209 char *gotfree_input_line; 4210 int bigdisp, override; 4211 unsigned int types = Disp; 4212 4213 if ((i.types[this_operand] & JumpAbsolute) 4214 || !(current_templates->start->opcode_modifier & (Jump | JumpDword))) 4215 { 4216 bigdisp = Disp32; 4217 override = (i.prefix[ADDR_PREFIX] != 0); 4218 } 4219 else 4220 { 4221 /* For PC-relative branches, the width of the displacement 4222 is dependent upon data size, not address size. */ 4223 bigdisp = 0; 4224 override = (i.prefix[DATA_PREFIX] != 0); 4225 } 4226 if (flag_code == CODE_64BIT) 4227 { 4228 if (!bigdisp) 4229 bigdisp = (override || i.suffix == WORD_MNEM_SUFFIX) 4230 ? Disp16 4231 : Disp32S | Disp32; 4232 else if (!override) 4233 bigdisp = Disp64 | Disp32S | Disp32; 4234 } 4235 else 4236 { 4237 if (!bigdisp) 4238 { 4239 if (!override) 4240 override = (i.suffix == (flag_code != CODE_16BIT 4241 ? WORD_MNEM_SUFFIX 4242 : LONG_MNEM_SUFFIX)); 4243 bigdisp = Disp32; 4244 } 4245 if ((flag_code == CODE_16BIT) ^ override) 4246 bigdisp = Disp16; 4247 } 4248 i.types[this_operand] |= bigdisp; 4249 4250 exp = &disp_expressions[i.disp_operands]; 4251 i.op[this_operand].disps = exp; 4252 i.disp_operands++; 4253 save_input_line_pointer = input_line_pointer; 4254 input_line_pointer = disp_start; 4255 END_STRING_AND_SAVE (disp_end); 4256 4257#ifndef GCC_ASM_O_HACK 4258#define GCC_ASM_O_HACK 0 4259#endif 4260#if GCC_ASM_O_HACK 4261 END_STRING_AND_SAVE (disp_end + 1); 4262 if ((i.types[this_operand] & BaseIndex) != 0 4263 && displacement_string_end[-1] == '+') 4264 { 4265 /* This hack is to avoid a warning when using the "o" 4266 constraint within gcc asm statements. 4267 For instance: 4268 4269 #define _set_tssldt_desc(n,addr,limit,type) \ 4270 __asm__ __volatile__ ( \ 4271 "movw %w2,%0\n\t" \ 4272 "movw %w1,2+%0\n\t" \ 4273 "rorl $16,%1\n\t" \ 4274 "movb %b1,4+%0\n\t" \ 4275 "movb %4,5+%0\n\t" \ 4276 "movb $0,6+%0\n\t" \ 4277 "movb %h1,7+%0\n\t" \ 4278 "rorl $16,%1" \ 4279 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) 4280 4281 This works great except that the output assembler ends 4282 up looking a bit weird if it turns out that there is 4283 no offset. You end up producing code that looks like: 4284 4285 #APP 4286 movw $235,(%eax) 4287 movw %dx,2+(%eax) 4288 rorl $16,%edx 4289 movb %dl,4+(%eax) 4290 movb $137,5+(%eax) 4291 movb $0,6+(%eax) 4292 movb %dh,7+(%eax) 4293 rorl $16,%edx 4294 #NO_APP 4295 4296 So here we provide the missing zero. */ 4297 4298 *displacement_string_end = '0'; 4299 } 4300#endif 4301 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); 4302 if (gotfree_input_line) 4303 input_line_pointer = gotfree_input_line; 4304 4305 exp_seg = expression (exp); 4306 4307 SKIP_WHITESPACE (); 4308 if (*input_line_pointer) 4309 as_bad (_("junk `%s' after expression"), input_line_pointer); 4310#if GCC_ASM_O_HACK 4311 RESTORE_END_STRING (disp_end + 1); 4312#endif 4313 RESTORE_END_STRING (disp_end); 4314 input_line_pointer = save_input_line_pointer; 4315 if (gotfree_input_line) 4316 free (gotfree_input_line); 4317 4318 /* We do this to make sure that the section symbol is in 4319 the symbol table. We will ultimately change the relocation 4320 to be relative to the beginning of the section. */ 4321 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF 4322 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL 4323 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) 4324 { 4325 if (exp->X_op != O_symbol) 4326 { 4327 as_bad (_("bad expression used with @%s"), 4328 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL 4329 ? "GOTPCREL" 4330 : "GOTOFF")); 4331 return 0; 4332 } 4333 4334 if (S_IS_LOCAL (exp->X_add_symbol) 4335 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) 4336 section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); 4337 exp->X_op = O_subtract; 4338 exp->X_op_symbol = GOT_symbol; 4339 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) 4340 i.reloc[this_operand] = BFD_RELOC_32_PCREL; 4341 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) 4342 i.reloc[this_operand] = BFD_RELOC_64; 4343 else 4344 i.reloc[this_operand] = BFD_RELOC_32; 4345 } 4346 4347 if (exp->X_op == O_absent || exp->X_op == O_big) 4348 { 4349 /* Missing or bad expr becomes absolute 0. */ 4350 as_bad (_("missing or invalid displacement expression `%s' taken as 0"), 4351 disp_start); 4352 exp->X_op = O_constant; 4353 exp->X_add_number = 0; 4354 exp->X_add_symbol = (symbolS *) 0; 4355 exp->X_op_symbol = (symbolS *) 0; 4356 } 4357 4358#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 4359 if (exp->X_op != O_constant 4360 && OUTPUT_FLAVOR == bfd_target_aout_flavour 4361 && exp_seg != absolute_section 4362 && exp_seg != text_section 4363 && exp_seg != data_section 4364 && exp_seg != bss_section 4365 && exp_seg != undefined_section 4366 && !bfd_is_com_section (exp_seg)) 4367 { 4368 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 4369 return 0; 4370 } 4371#endif 4372 4373 if (!(i.types[this_operand] & ~Disp)) 4374 i.types[this_operand] &= types; 4375 4376 return 1; 4377} 4378 4379static int i386_index_check PARAMS ((const char *)); 4380 4381/* Make sure the memory operand we've been dealt is valid. 4382 Return 1 on success, 0 on a failure. */ 4383 4384static int 4385i386_index_check (operand_string) 4386 const char *operand_string; 4387{ 4388 int ok; 4389#if INFER_ADDR_PREFIX 4390 int fudged = 0; 4391 4392 tryprefix: 4393#endif 4394 ok = 1; 4395 if ((current_templates->start->cpu_flags & CpuSVME) 4396 && current_templates->end[-1].operand_types[0] == AnyMem) 4397 { 4398 /* Memory operands of SVME insns are special in that they only allow 4399 rAX as their memory address and ignore any segment override. */ 4400 unsigned RegXX; 4401 4402 /* SKINIT is even more restrictive: it always requires EAX. */ 4403 if (strcmp (current_templates->start->name, "skinit") == 0) 4404 RegXX = Reg32; 4405 else if (flag_code == CODE_64BIT) 4406 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32; 4407 else 4408 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0) 4409 ? Reg16 4410 : Reg32; 4411 if (!i.base_reg 4412 || !(i.base_reg->reg_type & Acc) 4413 || !(i.base_reg->reg_type & RegXX) 4414 || i.index_reg 4415 || (i.types[0] & Disp)) 4416 ok = 0; 4417 } 4418 else if (flag_code == CODE_64BIT) 4419 { 4420 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32); 4421 4422 if ((i.base_reg 4423 && ((i.base_reg->reg_type & RegXX) == 0) 4424 && (i.base_reg->reg_type != BaseIndex 4425 || i.index_reg)) 4426 || (i.index_reg 4427 && ((i.index_reg->reg_type & (RegXX | BaseIndex)) 4428 != (RegXX | BaseIndex)))) 4429 ok = 0; 4430 } 4431 else 4432 { 4433 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) 4434 { 4435 /* 16bit checks. */ 4436 if ((i.base_reg 4437 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex)) 4438 != (Reg16 | BaseIndex))) 4439 || (i.index_reg 4440 && (((i.index_reg->reg_type & (Reg16 | BaseIndex)) 4441 != (Reg16 | BaseIndex)) 4442 || !(i.base_reg 4443 && i.base_reg->reg_num < 6 4444 && i.index_reg->reg_num >= 6 4445 && i.log2_scale_factor == 0)))) 4446 ok = 0; 4447 } 4448 else 4449 { 4450 /* 32bit checks. */ 4451 if ((i.base_reg 4452 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) 4453 || (i.index_reg 4454 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex)) 4455 != (Reg32 | BaseIndex)))) 4456 ok = 0; 4457 } 4458 } 4459 if (!ok) 4460 { 4461#if INFER_ADDR_PREFIX 4462 if (i.prefix[ADDR_PREFIX] == 0) 4463 { 4464 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; 4465 i.prefixes += 1; 4466 /* Change the size of any displacement too. At most one of 4467 Disp16 or Disp32 is set. 4468 FIXME. There doesn't seem to be any real need for separate 4469 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. 4470 Removing them would probably clean up the code quite a lot. */ 4471 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32))) 4472 i.types[this_operand] ^= (Disp16 | Disp32); 4473 fudged = 1; 4474 goto tryprefix; 4475 } 4476 if (fudged) 4477 as_bad (_("`%s' is not a valid base/index expression"), 4478 operand_string); 4479 else 4480#endif 4481 as_bad (_("`%s' is not a valid %s bit base/index expression"), 4482 operand_string, 4483 flag_code_names[flag_code]); 4484 } 4485 return ok; 4486} 4487 4488/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero 4489 on error. */ 4490 4491static int 4492i386_operand (operand_string) 4493 char *operand_string; 4494{ 4495 const reg_entry *r; 4496 char *end_op; 4497 char *op_string = operand_string; 4498 4499 if (is_space_char (*op_string)) 4500 ++op_string; 4501 4502 /* We check for an absolute prefix (differentiating, 4503 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ 4504 if (*op_string == ABSOLUTE_PREFIX) 4505 { 4506 ++op_string; 4507 if (is_space_char (*op_string)) 4508 ++op_string; 4509 i.types[this_operand] |= JumpAbsolute; 4510 } 4511 4512 /* Check if operand is a register. */ 4513 if ((r = parse_register (op_string, &end_op)) != NULL) 4514 { 4515 /* Check for a segment override by searching for ':' after a 4516 segment register. */ 4517 op_string = end_op; 4518 if (is_space_char (*op_string)) 4519 ++op_string; 4520 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) 4521 { 4522 switch (r->reg_num) 4523 { 4524 case 0: 4525 i.seg[i.mem_operands] = &es; 4526 break; 4527 case 1: 4528 i.seg[i.mem_operands] = &cs; 4529 break; 4530 case 2: 4531 i.seg[i.mem_operands] = &ss; 4532 break; 4533 case 3: 4534 i.seg[i.mem_operands] = &ds; 4535 break; 4536 case 4: 4537 i.seg[i.mem_operands] = &fs; 4538 break; 4539 case 5: 4540 i.seg[i.mem_operands] = &gs; 4541 break; 4542 } 4543 4544 /* Skip the ':' and whitespace. */ 4545 ++op_string; 4546 if (is_space_char (*op_string)) 4547 ++op_string; 4548 4549 if (!is_digit_char (*op_string) 4550 && !is_identifier_char (*op_string) 4551 && *op_string != '(' 4552 && *op_string != ABSOLUTE_PREFIX) 4553 { 4554 as_bad (_("bad memory operand `%s'"), op_string); 4555 return 0; 4556 } 4557 /* Handle case of %es:*foo. */ 4558 if (*op_string == ABSOLUTE_PREFIX) 4559 { 4560 ++op_string; 4561 if (is_space_char (*op_string)) 4562 ++op_string; 4563 i.types[this_operand] |= JumpAbsolute; 4564 } 4565 goto do_memory_reference; 4566 } 4567 if (*op_string) 4568 { 4569 as_bad (_("junk `%s' after register"), op_string); 4570 return 0; 4571 } 4572 i.types[this_operand] |= r->reg_type & ~BaseIndex; 4573 i.op[this_operand].regs = r; 4574 i.reg_operands++; 4575 } 4576 else if (*op_string == REGISTER_PREFIX) 4577 { 4578 as_bad (_("bad register name `%s'"), op_string); 4579 return 0; 4580 } 4581 else if (*op_string == IMMEDIATE_PREFIX) 4582 { 4583 ++op_string; 4584 if (i.types[this_operand] & JumpAbsolute) 4585 { 4586 as_bad (_("immediate operand illegal with absolute jump")); 4587 return 0; 4588 } 4589 if (!i386_immediate (op_string)) 4590 return 0; 4591 } 4592 else if (is_digit_char (*op_string) 4593 || is_identifier_char (*op_string) 4594 || *op_string == '(') 4595 { 4596 /* This is a memory reference of some sort. */ 4597 char *base_string; 4598 4599 /* Start and end of displacement string expression (if found). */ 4600 char *displacement_string_start; 4601 char *displacement_string_end; 4602 4603 do_memory_reference: 4604 if ((i.mem_operands == 1 4605 && (current_templates->start->opcode_modifier & IsString) == 0) 4606 || i.mem_operands == 2) 4607 { 4608 as_bad (_("too many memory references for `%s'"), 4609 current_templates->start->name); 4610 return 0; 4611 } 4612 4613 /* Check for base index form. We detect the base index form by 4614 looking for an ')' at the end of the operand, searching 4615 for the '(' matching it, and finding a REGISTER_PREFIX or ',' 4616 after the '('. */ 4617 base_string = op_string + strlen (op_string); 4618 4619 --base_string; 4620 if (is_space_char (*base_string)) 4621 --base_string; 4622 4623 /* If we only have a displacement, set-up for it to be parsed later. */ 4624 displacement_string_start = op_string; 4625 displacement_string_end = base_string + 1; 4626 4627 if (*base_string == ')') 4628 { 4629 char *temp_string; 4630 unsigned int parens_balanced = 1; 4631 /* We've already checked that the number of left & right ()'s are 4632 equal, so this loop will not be infinite. */ 4633 do 4634 { 4635 base_string--; 4636 if (*base_string == ')') 4637 parens_balanced++; 4638 if (*base_string == '(') 4639 parens_balanced--; 4640 } 4641 while (parens_balanced); 4642 4643 temp_string = base_string; 4644 4645 /* Skip past '(' and whitespace. */ 4646 ++base_string; 4647 if (is_space_char (*base_string)) 4648 ++base_string; 4649 4650 if (*base_string == ',' 4651 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL)) 4652 { 4653 displacement_string_end = temp_string; 4654 4655 i.types[this_operand] |= BaseIndex; 4656 4657 if (i.base_reg) 4658 { 4659 base_string = end_op; 4660 if (is_space_char (*base_string)) 4661 ++base_string; 4662 } 4663 4664 /* There may be an index reg or scale factor here. */ 4665 if (*base_string == ',') 4666 { 4667 ++base_string; 4668 if (is_space_char (*base_string)) 4669 ++base_string; 4670 4671 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL) 4672 { 4673 base_string = end_op; 4674 if (is_space_char (*base_string)) 4675 ++base_string; 4676 if (*base_string == ',') 4677 { 4678 ++base_string; 4679 if (is_space_char (*base_string)) 4680 ++base_string; 4681 } 4682 else if (*base_string != ')') 4683 { 4684 as_bad (_("expecting `,' or `)' after index register in `%s'"), 4685 operand_string); 4686 return 0; 4687 } 4688 } 4689 else if (*base_string == REGISTER_PREFIX) 4690 { 4691 as_bad (_("bad register name `%s'"), base_string); 4692 return 0; 4693 } 4694 4695 /* Check for scale factor. */ 4696 if (*base_string != ')') 4697 { 4698 char *end_scale = i386_scale (base_string); 4699 4700 if (!end_scale) 4701 return 0; 4702 4703 base_string = end_scale; 4704 if (is_space_char (*base_string)) 4705 ++base_string; 4706 if (*base_string != ')') 4707 { 4708 as_bad (_("expecting `)' after scale factor in `%s'"), 4709 operand_string); 4710 return 0; 4711 } 4712 } 4713 else if (!i.index_reg) 4714 { 4715 as_bad (_("expecting index register or scale factor after `,'; got '%c'"), 4716 *base_string); 4717 return 0; 4718 } 4719 } 4720 else if (*base_string != ')') 4721 { 4722 as_bad (_("expecting `,' or `)' after base register in `%s'"), 4723 operand_string); 4724 return 0; 4725 } 4726 } 4727 else if (*base_string == REGISTER_PREFIX) 4728 { 4729 as_bad (_("bad register name `%s'"), base_string); 4730 return 0; 4731 } 4732 } 4733 4734 /* If there's an expression beginning the operand, parse it, 4735 assuming displacement_string_start and 4736 displacement_string_end are meaningful. */ 4737 if (displacement_string_start != displacement_string_end) 4738 { 4739 if (!i386_displacement (displacement_string_start, 4740 displacement_string_end)) 4741 return 0; 4742 } 4743 4744 /* Special case for (%dx) while doing input/output op. */ 4745 if (i.base_reg 4746 && i.base_reg->reg_type == (Reg16 | InOutPortReg) 4747 && i.index_reg == 0 4748 && i.log2_scale_factor == 0 4749 && i.seg[i.mem_operands] == 0 4750 && (i.types[this_operand] & Disp) == 0) 4751 { 4752 i.types[this_operand] = InOutPortReg; 4753 return 1; 4754 } 4755 4756 if (i386_index_check (operand_string) == 0) 4757 return 0; 4758 i.mem_operands++; 4759 } 4760 else 4761 { 4762 /* It's not a memory operand; argh! */ 4763 as_bad (_("invalid char %s beginning operand %d `%s'"), 4764 output_invalid (*op_string), 4765 this_operand + 1, 4766 op_string); 4767 return 0; 4768 } 4769 return 1; /* Normal return. */ 4770} 4771 4772/* md_estimate_size_before_relax() 4773 4774 Called just before relax() for rs_machine_dependent frags. The x86 4775 assembler uses these frags to handle variable size jump 4776 instructions. 4777 4778 Any symbol that is now undefined will not become defined. 4779 Return the correct fr_subtype in the frag. 4780 Return the initial "guess for variable size of frag" to caller. 4781 The guess is actually the growth beyond the fixed part. Whatever 4782 we do to grow the fixed or variable part contributes to our 4783 returned value. */ 4784 4785int 4786md_estimate_size_before_relax (fragP, segment) 4787 fragS *fragP; 4788 segT segment; 4789{ 4790 /* We've already got fragP->fr_subtype right; all we have to do is 4791 check for un-relaxable symbols. On an ELF system, we can't relax 4792 an externally visible symbol, because it may be overridden by a 4793 shared library. */ 4794 if (S_GET_SEGMENT (fragP->fr_symbol) != segment 4795#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 4796 || (IS_ELF 4797 && (S_IS_EXTERNAL (fragP->fr_symbol) 4798 || S_IS_WEAK (fragP->fr_symbol))) 4799#endif 4800 ) 4801 { 4802 /* Symbol is undefined in this segment, or we need to keep a 4803 reloc so that weak symbols can be overridden. */ 4804 int size = (fragP->fr_subtype & CODE16) ? 2 : 4; 4805 enum bfd_reloc_code_real reloc_type; 4806 unsigned char *opcode; 4807 int old_fr_fix; 4808 4809 if (fragP->fr_var != NO_RELOC) 4810 reloc_type = fragP->fr_var; 4811 else if (size == 2) 4812 reloc_type = BFD_RELOC_16_PCREL; 4813 else 4814 reloc_type = BFD_RELOC_32_PCREL; 4815 4816 old_fr_fix = fragP->fr_fix; 4817 opcode = (unsigned char *) fragP->fr_opcode; 4818 4819 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) 4820 { 4821 case UNCOND_JUMP: 4822 /* Make jmp (0xeb) a (d)word displacement jump. */ 4823 opcode[0] = 0xe9; 4824 fragP->fr_fix += size; 4825 fix_new (fragP, old_fr_fix, size, 4826 fragP->fr_symbol, 4827 fragP->fr_offset, 1, 4828 reloc_type); 4829 break; 4830 4831 case COND_JUMP86: 4832 if (size == 2 4833 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) 4834 { 4835 /* Negate the condition, and branch past an 4836 unconditional jump. */ 4837 opcode[0] ^= 1; 4838 opcode[1] = 3; 4839 /* Insert an unconditional jump. */ 4840 opcode[2] = 0xe9; 4841 /* We added two extra opcode bytes, and have a two byte 4842 offset. */ 4843 fragP->fr_fix += 2 + 2; 4844 fix_new (fragP, old_fr_fix + 2, 2, 4845 fragP->fr_symbol, 4846 fragP->fr_offset, 1, 4847 reloc_type); 4848 break; 4849 } 4850 /* Fall through. */ 4851 4852 case COND_JUMP: 4853 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) 4854 { 4855 fixS *fixP; 4856 4857 fragP->fr_fix += 1; 4858 fixP = fix_new (fragP, old_fr_fix, 1, 4859 fragP->fr_symbol, 4860 fragP->fr_offset, 1, 4861 BFD_RELOC_8_PCREL); 4862 fixP->fx_signed = 1; 4863 break; 4864 } 4865 4866 /* This changes the byte-displacement jump 0x7N 4867 to the (d)word-displacement jump 0x0f,0x8N. */ 4868 opcode[1] = opcode[0] + 0x10; 4869 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 4870 /* We've added an opcode byte. */ 4871 fragP->fr_fix += 1 + size; 4872 fix_new (fragP, old_fr_fix + 1, size, 4873 fragP->fr_symbol, 4874 fragP->fr_offset, 1, 4875 reloc_type); 4876 break; 4877 4878 default: 4879 BAD_CASE (fragP->fr_subtype); 4880 break; 4881 } 4882 frag_wane (fragP); 4883 return fragP->fr_fix - old_fr_fix; 4884 } 4885 4886 /* Guess size depending on current relax state. Initially the relax 4887 state will correspond to a short jump and we return 1, because 4888 the variable part of the frag (the branch offset) is one byte 4889 long. However, we can relax a section more than once and in that 4890 case we must either set fr_subtype back to the unrelaxed state, 4891 or return the value for the appropriate branch. */ 4892 return md_relax_table[fragP->fr_subtype].rlx_length; 4893} 4894 4895/* Called after relax() is finished. 4896 4897 In: Address of frag. 4898 fr_type == rs_machine_dependent. 4899 fr_subtype is what the address relaxed to. 4900 4901 Out: Any fixSs and constants are set up. 4902 Caller will turn frag into a ".space 0". */ 4903 4904void 4905md_convert_frag (abfd, sec, fragP) 4906 bfd *abfd ATTRIBUTE_UNUSED; 4907 segT sec ATTRIBUTE_UNUSED; 4908 fragS *fragP; 4909{ 4910 unsigned char *opcode; 4911 unsigned char *where_to_put_displacement = NULL; 4912 offsetT target_address; 4913 offsetT opcode_address; 4914 unsigned int extension = 0; 4915 offsetT displacement_from_opcode_start; 4916 4917 opcode = (unsigned char *) fragP->fr_opcode; 4918 4919 /* Address we want to reach in file space. */ 4920 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; 4921 4922 /* Address opcode resides at in file space. */ 4923 opcode_address = fragP->fr_address + fragP->fr_fix; 4924 4925 /* Displacement from opcode start to fill into instruction. */ 4926 displacement_from_opcode_start = target_address - opcode_address; 4927 4928 if ((fragP->fr_subtype & BIG) == 0) 4929 { 4930 /* Don't have to change opcode. */ 4931 extension = 1; /* 1 opcode + 1 displacement */ 4932 where_to_put_displacement = &opcode[1]; 4933 } 4934 else 4935 { 4936 if (no_cond_jump_promotion 4937 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) 4938 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required")); 4939 4940 switch (fragP->fr_subtype) 4941 { 4942 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): 4943 extension = 4; /* 1 opcode + 4 displacement */ 4944 opcode[0] = 0xe9; 4945 where_to_put_displacement = &opcode[1]; 4946 break; 4947 4948 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): 4949 extension = 2; /* 1 opcode + 2 displacement */ 4950 opcode[0] = 0xe9; 4951 where_to_put_displacement = &opcode[1]; 4952 break; 4953 4954 case ENCODE_RELAX_STATE (COND_JUMP, BIG): 4955 case ENCODE_RELAX_STATE (COND_JUMP86, BIG): 4956 extension = 5; /* 2 opcode + 4 displacement */ 4957 opcode[1] = opcode[0] + 0x10; 4958 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 4959 where_to_put_displacement = &opcode[2]; 4960 break; 4961 4962 case ENCODE_RELAX_STATE (COND_JUMP, BIG16): 4963 extension = 3; /* 2 opcode + 2 displacement */ 4964 opcode[1] = opcode[0] + 0x10; 4965 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 4966 where_to_put_displacement = &opcode[2]; 4967 break; 4968 4969 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): 4970 extension = 4; 4971 opcode[0] ^= 1; 4972 opcode[1] = 3; 4973 opcode[2] = 0xe9; 4974 where_to_put_displacement = &opcode[3]; 4975 break; 4976 4977 default: 4978 BAD_CASE (fragP->fr_subtype); 4979 break; 4980 } 4981 } 4982 4983 /* If size if less then four we are sure that the operand fits, 4984 but if it's 4, then it could be that the displacement is larger 4985 then -/+ 2GB. */ 4986 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 4987 && object_64bit 4988 && ((addressT) (displacement_from_opcode_start - extension 4989 + ((addressT) 1 << 31)) 4990 > (((addressT) 2 << 31) - 1))) 4991 { 4992 as_bad_where (fragP->fr_file, fragP->fr_line, 4993 _("jump target out of range")); 4994 /* Make us emit 0. */ 4995 displacement_from_opcode_start = extension; 4996 } 4997 /* Now put displacement after opcode. */ 4998 md_number_to_chars ((char *) where_to_put_displacement, 4999 (valueT) (displacement_from_opcode_start - extension), 5000 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); 5001 fragP->fr_fix += extension; 5002} 5003 5004/* Size of byte displacement jmp. */ 5005int md_short_jump_size = 2; 5006 5007/* Size of dword displacement jmp. */ 5008int md_long_jump_size = 5; 5009 5010void 5011md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) 5012 char *ptr; 5013 addressT from_addr, to_addr; 5014 fragS *frag ATTRIBUTE_UNUSED; 5015 symbolS *to_symbol ATTRIBUTE_UNUSED; 5016{ 5017 offsetT offset; 5018 5019 offset = to_addr - (from_addr + 2); 5020 /* Opcode for byte-disp jump. */ 5021 md_number_to_chars (ptr, (valueT) 0xeb, 1); 5022 md_number_to_chars (ptr + 1, (valueT) offset, 1); 5023} 5024 5025void 5026md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) 5027 char *ptr; 5028 addressT from_addr, to_addr; 5029 fragS *frag ATTRIBUTE_UNUSED; 5030 symbolS *to_symbol ATTRIBUTE_UNUSED; 5031{ 5032 offsetT offset; 5033 5034 offset = to_addr - (from_addr + 5); 5035 md_number_to_chars (ptr, (valueT) 0xe9, 1); 5036 md_number_to_chars (ptr + 1, (valueT) offset, 4); 5037} 5038 5039/* Apply a fixup (fixS) to segment data, once it has been determined 5040 by our caller that we have all the info we need to fix it up. 5041 5042 On the 386, immediates, displacements, and data pointers are all in 5043 the same (little-endian) format, so we don't need to care about which 5044 we are handling. */ 5045 5046void 5047md_apply_fix (fixP, valP, seg) 5048 /* The fix we're to put in. */ 5049 fixS *fixP; 5050 /* Pointer to the value of the bits. */ 5051 valueT *valP; 5052 /* Segment fix is from. */ 5053 segT seg ATTRIBUTE_UNUSED; 5054{ 5055 char *p = fixP->fx_where + fixP->fx_frag->fr_literal; 5056 valueT value = *valP; 5057 5058#if !defined (TE_Mach) 5059 if (fixP->fx_pcrel) 5060 { 5061 switch (fixP->fx_r_type) 5062 { 5063 default: 5064 break; 5065 5066 case BFD_RELOC_64: 5067 fixP->fx_r_type = BFD_RELOC_64_PCREL; 5068 break; 5069 case BFD_RELOC_32: 5070 case BFD_RELOC_X86_64_32S: 5071 fixP->fx_r_type = BFD_RELOC_32_PCREL; 5072 break; 5073 case BFD_RELOC_16: 5074 fixP->fx_r_type = BFD_RELOC_16_PCREL; 5075 break; 5076 case BFD_RELOC_8: 5077 fixP->fx_r_type = BFD_RELOC_8_PCREL; 5078 break; 5079 } 5080 } 5081 5082 if (fixP->fx_addsy != NULL 5083 && (fixP->fx_r_type == BFD_RELOC_32_PCREL 5084 || fixP->fx_r_type == BFD_RELOC_64_PCREL 5085 || fixP->fx_r_type == BFD_RELOC_16_PCREL 5086 || fixP->fx_r_type == BFD_RELOC_8_PCREL) 5087 && !use_rela_relocations) 5088 { 5089 /* This is a hack. There should be a better way to handle this. 5090 This covers for the fact that bfd_install_relocation will 5091 subtract the current location (for partial_inplace, PC relative 5092 relocations); see more below. */ 5093#ifndef OBJ_AOUT 5094 if (IS_ELF 5095#ifdef TE_PE 5096 || OUTPUT_FLAVOR == bfd_target_coff_flavour 5097#endif 5098 ) 5099 value += fixP->fx_where + fixP->fx_frag->fr_address; 5100#endif 5101#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5102 if (IS_ELF) 5103 { 5104 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); 5105 5106 if ((sym_seg == seg 5107 || (symbol_section_p (fixP->fx_addsy) 5108 && sym_seg != absolute_section)) 5109 && !generic_force_reloc (fixP)) 5110 { 5111 /* Yes, we add the values in twice. This is because 5112 bfd_install_relocation subtracts them out again. I think 5113 bfd_install_relocation is broken, but I don't dare change 5114 it. FIXME. */ 5115 value += fixP->fx_where + fixP->fx_frag->fr_address; 5116 } 5117 } 5118#endif 5119#if defined (OBJ_COFF) && defined (TE_PE) 5120 /* For some reason, the PE format does not store a 5121 section address offset for a PC relative symbol. */ 5122 if (S_GET_SEGMENT (fixP->fx_addsy) != seg 5123 || S_IS_WEAK (fixP->fx_addsy)) 5124 value += md_pcrel_from (fixP); 5125#endif 5126 } 5127 5128 /* Fix a few things - the dynamic linker expects certain values here, 5129 and we must not disappoint it. */ 5130#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5131 if (IS_ELF && fixP->fx_addsy) 5132 switch (fixP->fx_r_type) 5133 { 5134 case BFD_RELOC_386_PLT32: 5135 case BFD_RELOC_X86_64_PLT32: 5136 /* Make the jump instruction point to the address of the operand. At 5137 runtime we merely add the offset to the actual PLT entry. */ 5138 value = -4; 5139 break; 5140 5141 case BFD_RELOC_386_TLS_GD: 5142 case BFD_RELOC_386_TLS_LDM: 5143 case BFD_RELOC_386_TLS_IE_32: 5144 case BFD_RELOC_386_TLS_IE: 5145 case BFD_RELOC_386_TLS_GOTIE: 5146 case BFD_RELOC_386_TLS_GOTDESC: 5147 case BFD_RELOC_X86_64_TLSGD: 5148 case BFD_RELOC_X86_64_TLSLD: 5149 case BFD_RELOC_X86_64_GOTTPOFF: 5150 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 5151 value = 0; /* Fully resolved at runtime. No addend. */ 5152 /* Fallthrough */ 5153 case BFD_RELOC_386_TLS_LE: 5154 case BFD_RELOC_386_TLS_LDO_32: 5155 case BFD_RELOC_386_TLS_LE_32: 5156 case BFD_RELOC_X86_64_DTPOFF32: 5157 case BFD_RELOC_X86_64_DTPOFF64: 5158 case BFD_RELOC_X86_64_TPOFF32: 5159 case BFD_RELOC_X86_64_TPOFF64: 5160 S_SET_THREAD_LOCAL (fixP->fx_addsy); 5161 break; 5162 5163 case BFD_RELOC_386_TLS_DESC_CALL: 5164 case BFD_RELOC_X86_64_TLSDESC_CALL: 5165 value = 0; /* Fully resolved at runtime. No addend. */ 5166 S_SET_THREAD_LOCAL (fixP->fx_addsy); 5167 fixP->fx_done = 0; 5168 return; 5169 5170 case BFD_RELOC_386_GOT32: 5171 case BFD_RELOC_X86_64_GOT32: 5172 value = 0; /* Fully resolved at runtime. No addend. */ 5173 break; 5174 5175 case BFD_RELOC_VTABLE_INHERIT: 5176 case BFD_RELOC_VTABLE_ENTRY: 5177 fixP->fx_done = 0; 5178 return; 5179 5180 default: 5181 break; 5182 } 5183#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ 5184 *valP = value; 5185#endif /* !defined (TE_Mach) */ 5186 5187 /* Are we finished with this relocation now? */ 5188 if (fixP->fx_addsy == NULL) 5189 fixP->fx_done = 1; 5190 else if (use_rela_relocations) 5191 { 5192 fixP->fx_no_overflow = 1; 5193 /* Remember value for tc_gen_reloc. */ 5194 fixP->fx_addnumber = value; 5195 value = 0; 5196 } 5197 5198 md_number_to_chars (p, value, fixP->fx_size); 5199} 5200 5201#define MAX_LITTLENUMS 6 5202 5203/* Turn the string pointed to by litP into a floating point constant 5204 of type TYPE, and emit the appropriate bytes. The number of 5205 LITTLENUMS emitted is stored in *SIZEP. An error message is 5206 returned, or NULL on OK. */ 5207 5208char * 5209md_atof (type, litP, sizeP) 5210 int type; 5211 char *litP; 5212 int *sizeP; 5213{ 5214 int prec; 5215 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 5216 LITTLENUM_TYPE *wordP; 5217 char *t; 5218 5219 switch (type) 5220 { 5221 case 'f': 5222 case 'F': 5223 prec = 2; 5224 break; 5225 5226 case 'd': 5227 case 'D': 5228 prec = 4; 5229 break; 5230 5231 case 'x': 5232 case 'X': 5233 prec = 5; 5234 break; 5235 5236 default: 5237 *sizeP = 0; 5238 return _("Bad call to md_atof ()"); 5239 } 5240 t = atof_ieee (input_line_pointer, type, words); 5241 if (t) 5242 input_line_pointer = t; 5243 5244 *sizeP = prec * sizeof (LITTLENUM_TYPE); 5245 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with 5246 the bigendian 386. */ 5247 for (wordP = words + prec - 1; prec--;) 5248 { 5249 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); 5250 litP += sizeof (LITTLENUM_TYPE); 5251 } 5252 return 0; 5253} 5254 5255static char output_invalid_buf[8]; 5256 5257static char * 5258output_invalid (c) 5259 int c; 5260{ 5261 if (ISPRINT (c)) 5262 sprintf (output_invalid_buf, "'%c'", c); 5263 else 5264 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); 5265 return output_invalid_buf; 5266} 5267 5268/* REG_STRING starts *before* REGISTER_PREFIX. */ 5269 5270static const reg_entry * 5271parse_real_register (char *reg_string, char **end_op) 5272{ 5273 char *s = reg_string; 5274 char *p; 5275 char reg_name_given[MAX_REG_NAME_SIZE + 1]; 5276 const reg_entry *r; 5277 5278 /* Skip possible REGISTER_PREFIX and possible whitespace. */ 5279 if (*s == REGISTER_PREFIX) 5280 ++s; 5281 5282 if (is_space_char (*s)) 5283 ++s; 5284 5285 p = reg_name_given; 5286 while ((*p++ = register_chars[(unsigned char) *s]) != '\0') 5287 { 5288 if (p >= reg_name_given + MAX_REG_NAME_SIZE) 5289 return (const reg_entry *) NULL; 5290 s++; 5291 } 5292 5293 /* For naked regs, make sure that we are not dealing with an identifier. 5294 This prevents confusing an identifier like `eax_var' with register 5295 `eax'. */ 5296 if (allow_naked_reg && identifier_chars[(unsigned char) *s]) 5297 return (const reg_entry *) NULL; 5298 5299 *end_op = s; 5300 5301 r = (const reg_entry *) hash_find (reg_hash, reg_name_given); 5302 5303 /* Handle floating point regs, allowing spaces in the (i) part. */ 5304 if (r == i386_regtab /* %st is first entry of table */) 5305 { 5306 if (is_space_char (*s)) 5307 ++s; 5308 if (*s == '(') 5309 { 5310 ++s; 5311 if (is_space_char (*s)) 5312 ++s; 5313 if (*s >= '0' && *s <= '7') 5314 { 5315 r = &i386_float_regtab[*s - '0']; 5316 ++s; 5317 if (is_space_char (*s)) 5318 ++s; 5319 if (*s == ')') 5320 { 5321 *end_op = s + 1; 5322 return r; 5323 } 5324 } 5325 /* We have "%st(" then garbage. */ 5326 return (const reg_entry *) NULL; 5327 } 5328 } 5329 5330 if (r != NULL 5331 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0 5332 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer)) 5333 && flag_code != CODE_64BIT) 5334 return (const reg_entry *) NULL; 5335 5336 return r; 5337} 5338 5339/* REG_STRING starts *before* REGISTER_PREFIX. */ 5340 5341static const reg_entry * 5342parse_register (char *reg_string, char **end_op) 5343{ 5344 const reg_entry *r; 5345 5346 if (*reg_string == REGISTER_PREFIX || allow_naked_reg) 5347 r = parse_real_register (reg_string, end_op); 5348 else 5349 r = NULL; 5350 if (!r) 5351 { 5352 char *save = input_line_pointer; 5353 char c; 5354 symbolS *symbolP; 5355 5356 input_line_pointer = reg_string; 5357 c = get_symbol_end (); 5358 symbolP = symbol_find (reg_string); 5359 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) 5360 { 5361 const expressionS *e = symbol_get_value_expression (symbolP); 5362 5363 know (e->X_op == O_register); 5364 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab)); 5365 r = i386_regtab + e->X_add_number; 5366 *end_op = input_line_pointer; 5367 } 5368 *input_line_pointer = c; 5369 input_line_pointer = save; 5370 } 5371 return r; 5372} 5373 5374int 5375i386_parse_name (char *name, expressionS *e, char *nextcharP) 5376{ 5377 const reg_entry *r; 5378 char *end = input_line_pointer; 5379 5380 *end = *nextcharP; 5381 r = parse_register (name, &input_line_pointer); 5382 if (r && end <= input_line_pointer) 5383 { 5384 *nextcharP = *input_line_pointer; 5385 *input_line_pointer = 0; 5386 e->X_op = O_register; 5387 e->X_add_number = r - i386_regtab; 5388 return 1; 5389 } 5390 input_line_pointer = end; 5391 *end = 0; 5392 return 0; 5393} 5394 5395void 5396md_operand (expressionS *e) 5397{ 5398 if (*input_line_pointer == REGISTER_PREFIX) 5399 { 5400 char *end; 5401 const reg_entry *r = parse_real_register (input_line_pointer, &end); 5402 5403 if (r) 5404 { 5405 e->X_op = O_register; 5406 e->X_add_number = r - i386_regtab; 5407 input_line_pointer = end; 5408 } 5409 } 5410} 5411 5412 5413#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5414const char *md_shortopts = "kVQ:sqn"; 5415#else 5416const char *md_shortopts = "qn"; 5417#endif 5418 5419#define OPTION_32 (OPTION_MD_BASE + 0) 5420#define OPTION_64 (OPTION_MD_BASE + 1) 5421#define OPTION_DIVIDE (OPTION_MD_BASE + 2) 5422 5423struct option md_longopts[] = { 5424 {"32", no_argument, NULL, OPTION_32}, 5425#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5426 {"64", no_argument, NULL, OPTION_64}, 5427#endif 5428 {"divide", no_argument, NULL, OPTION_DIVIDE}, 5429 {NULL, no_argument, NULL, 0} 5430}; 5431size_t md_longopts_size = sizeof (md_longopts); 5432 5433int 5434md_parse_option (c, arg) 5435 int c; 5436 char *arg ATTRIBUTE_UNUSED; 5437{ 5438 switch (c) 5439 { 5440 case 'n': 5441 optimize_align_code = 0; 5442 break; 5443 5444 case 'q': 5445 quiet_warnings = 1; 5446 break; 5447 5448#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5449 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 5450 should be emitted or not. FIXME: Not implemented. */ 5451 case 'Q': 5452 break; 5453 5454 /* -V: SVR4 argument to print version ID. */ 5455 case 'V': 5456 print_version_id (); 5457 break; 5458 5459 /* -k: Ignore for FreeBSD compatibility. */ 5460 case 'k': 5461 break; 5462 5463 case 's': 5464 /* -s: On i386 Solaris, this tells the native assembler to use 5465 .stab instead of .stab.excl. We always use .stab anyhow. */ 5466 break; 5467 5468 case OPTION_64: 5469 { 5470 const char **list, **l; 5471 5472 list = bfd_target_list (); 5473 for (l = list; *l != NULL; l++) 5474 if (strcmp (*l, "elf64-x86-64") == 0) 5475 { 5476 default_arch = "x86_64"; 5477 break; 5478 } 5479 if (*l == NULL) 5480 as_fatal (_("No compiled in support for x86_64")); 5481 free (list); 5482 } 5483 break; 5484#endif 5485 5486 case OPTION_32: 5487 default_arch = "i386"; 5488 break; 5489 5490 case OPTION_DIVIDE: 5491#ifdef SVR4_COMMENT_CHARS 5492 { 5493 char *n, *t; 5494 const char *s; 5495 5496 n = (char *) xmalloc (strlen (i386_comment_chars) + 1); 5497 t = n; 5498 for (s = i386_comment_chars; *s != '\0'; s++) 5499 if (*s != '/') 5500 *t++ = *s; 5501 *t = '\0'; 5502 i386_comment_chars = n; 5503 } 5504#endif 5505 break; 5506 5507 default: 5508 return 0; 5509 } 5510 return 1; 5511} 5512 5513void 5514md_show_usage (stream) 5515 FILE *stream; 5516{ 5517#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5518 fprintf (stream, _("\ 5519 -Q ignored\n\ 5520 -V print assembler version number\n\ 5521 -k ignored\n")); 5522#endif 5523 fprintf (stream, _("\ 5524 -n Do not optimize code alignment\n\ 5525 -q quieten some warnings\n")); 5526#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5527 fprintf (stream, _("\ 5528 -s ignored\n")); 5529#endif 5530#ifdef SVR4_COMMENT_CHARS 5531 fprintf (stream, _("\ 5532 --divide do not treat `/' as a comment character\n")); 5533#else 5534 fprintf (stream, _("\ 5535 --divide ignored\n")); 5536#endif 5537} 5538 5539#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 5540 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 5541 5542/* Pick the target format to use. */ 5543 5544const char * 5545i386_target_format () 5546{ 5547 if (!strcmp (default_arch, "x86_64")) 5548 set_code_flag (CODE_64BIT); 5549 else if (!strcmp (default_arch, "i386")) 5550 set_code_flag (CODE_32BIT); 5551 else 5552 as_fatal (_("Unknown architecture")); 5553 switch (OUTPUT_FLAVOR) 5554 { 5555#ifdef OBJ_MAYBE_AOUT 5556 case bfd_target_aout_flavour: 5557 return AOUT_TARGET_FORMAT; 5558#endif 5559#ifdef OBJ_MAYBE_COFF 5560 case bfd_target_coff_flavour: 5561 return "coff-i386"; 5562#endif 5563#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) 5564 case bfd_target_elf_flavour: 5565 { 5566 if (flag_code == CODE_64BIT) 5567 { 5568 object_64bit = 1; 5569 use_rela_relocations = 1; 5570 } 5571 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT; 5572 } 5573#endif 5574 default: 5575 abort (); 5576 return NULL; 5577 } 5578} 5579 5580#endif /* OBJ_MAYBE_ more than one */ 5581 5582#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 5583void i386_elf_emit_arch_note () 5584{ 5585 if (IS_ELF && cpu_arch_name != NULL) 5586 { 5587 char *p; 5588 asection *seg = now_seg; 5589 subsegT subseg = now_subseg; 5590 Elf_Internal_Note i_note; 5591 Elf_External_Note e_note; 5592 asection *note_secp; 5593 int len; 5594 5595 /* Create the .note section. */ 5596 note_secp = subseg_new (".note", 0); 5597 bfd_set_section_flags (stdoutput, 5598 note_secp, 5599 SEC_HAS_CONTENTS | SEC_READONLY); 5600 5601 /* Process the arch string. */ 5602 len = strlen (cpu_arch_name); 5603 5604 i_note.namesz = len + 1; 5605 i_note.descsz = 0; 5606 i_note.type = NT_ARCH; 5607 p = frag_more (sizeof (e_note.namesz)); 5608 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); 5609 p = frag_more (sizeof (e_note.descsz)); 5610 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); 5611 p = frag_more (sizeof (e_note.type)); 5612 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); 5613 p = frag_more (len + 1); 5614 strcpy (p, cpu_arch_name); 5615 5616 frag_align (2, 0, 0); 5617 5618 subseg_set (seg, subseg); 5619 } 5620} 5621#endif 5622 5623symbolS * 5624md_undefined_symbol (name) 5625 char *name; 5626{ 5627 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] 5628 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] 5629 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] 5630 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) 5631 { 5632 if (!GOT_symbol) 5633 { 5634 if (symbol_find (name)) 5635 as_bad (_("GOT already in symbol table")); 5636 GOT_symbol = symbol_new (name, undefined_section, 5637 (valueT) 0, &zero_address_frag); 5638 }; 5639 return GOT_symbol; 5640 } 5641 return 0; 5642} 5643 5644/* Round up a section size to the appropriate boundary. */ 5645 5646valueT 5647md_section_align (segment, size) 5648 segT segment ATTRIBUTE_UNUSED; 5649 valueT size; 5650{ 5651#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 5652 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 5653 { 5654 /* For a.out, force the section size to be aligned. If we don't do 5655 this, BFD will align it for us, but it will not write out the 5656 final bytes of the section. This may be a bug in BFD, but it is 5657 easier to fix it here since that is how the other a.out targets 5658 work. */ 5659 int align; 5660 5661 align = bfd_get_section_alignment (stdoutput, segment); 5662 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 5663 } 5664#endif 5665 5666 return size; 5667} 5668 5669/* On the i386, PC-relative offsets are relative to the start of the 5670 next instruction. That is, the address of the offset, plus its 5671 size, since the offset is always the last part of the insn. */ 5672 5673long 5674md_pcrel_from (fixP) 5675 fixS *fixP; 5676{ 5677 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; 5678} 5679 5680#ifndef I386COFF 5681 5682static void 5683s_bss (ignore) 5684 int ignore ATTRIBUTE_UNUSED; 5685{ 5686 int temp; 5687 5688#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5689 if (IS_ELF) 5690 obj_elf_section_change_hook (); 5691#endif 5692 temp = get_absolute_expression (); 5693 subseg_set (bss_section, (subsegT) temp); 5694 demand_empty_rest_of_line (); 5695} 5696 5697#endif 5698 5699void 5700i386_validate_fix (fixp) 5701 fixS *fixp; 5702{ 5703 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) 5704 { 5705 if (fixp->fx_r_type == BFD_RELOC_32_PCREL) 5706 { 5707 if (!object_64bit) 5708 abort (); 5709 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; 5710 } 5711 else 5712 { 5713 if (!object_64bit) 5714 fixp->fx_r_type = BFD_RELOC_386_GOTOFF; 5715 else 5716 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; 5717 } 5718 fixp->fx_subsy = 0; 5719 } 5720} 5721 5722arelent * 5723tc_gen_reloc (section, fixp) 5724 asection *section ATTRIBUTE_UNUSED; 5725 fixS *fixp; 5726{ 5727 arelent *rel; 5728 bfd_reloc_code_real_type code; 5729 5730 switch (fixp->fx_r_type) 5731 { 5732 case BFD_RELOC_X86_64_PLT32: 5733 case BFD_RELOC_X86_64_GOT32: 5734 case BFD_RELOC_X86_64_GOTPCREL: 5735 case BFD_RELOC_386_PLT32: 5736 case BFD_RELOC_386_GOT32: 5737 case BFD_RELOC_386_GOTOFF: 5738 case BFD_RELOC_386_GOTPC: 5739 case BFD_RELOC_386_TLS_GD: 5740 case BFD_RELOC_386_TLS_LDM: 5741 case BFD_RELOC_386_TLS_LDO_32: 5742 case BFD_RELOC_386_TLS_IE_32: 5743 case BFD_RELOC_386_TLS_IE: 5744 case BFD_RELOC_386_TLS_GOTIE: 5745 case BFD_RELOC_386_TLS_LE_32: 5746 case BFD_RELOC_386_TLS_LE: 5747 case BFD_RELOC_386_TLS_GOTDESC: 5748 case BFD_RELOC_386_TLS_DESC_CALL: 5749 case BFD_RELOC_X86_64_TLSGD: 5750 case BFD_RELOC_X86_64_TLSLD: 5751 case BFD_RELOC_X86_64_DTPOFF32: 5752 case BFD_RELOC_X86_64_DTPOFF64: 5753 case BFD_RELOC_X86_64_GOTTPOFF: 5754 case BFD_RELOC_X86_64_TPOFF32: 5755 case BFD_RELOC_X86_64_TPOFF64: 5756 case BFD_RELOC_X86_64_GOTOFF64: 5757 case BFD_RELOC_X86_64_GOTPC32: 5758 case BFD_RELOC_X86_64_GOT64: 5759 case BFD_RELOC_X86_64_GOTPCREL64: 5760 case BFD_RELOC_X86_64_GOTPC64: 5761 case BFD_RELOC_X86_64_GOTPLT64: 5762 case BFD_RELOC_X86_64_PLTOFF64: 5763 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 5764 case BFD_RELOC_X86_64_TLSDESC_CALL: 5765 case BFD_RELOC_RVA: 5766 case BFD_RELOC_VTABLE_ENTRY: 5767 case BFD_RELOC_VTABLE_INHERIT: 5768#ifdef TE_PE 5769 case BFD_RELOC_32_SECREL: 5770#endif 5771 code = fixp->fx_r_type; 5772 break; 5773 case BFD_RELOC_X86_64_32S: 5774 if (!fixp->fx_pcrel) 5775 { 5776 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ 5777 code = fixp->fx_r_type; 5778 break; 5779 } 5780 default: 5781 if (fixp->fx_pcrel) 5782 { 5783 switch (fixp->fx_size) 5784 { 5785 default: 5786 as_bad_where (fixp->fx_file, fixp->fx_line, 5787 _("can not do %d byte pc-relative relocation"), 5788 fixp->fx_size); 5789 code = BFD_RELOC_32_PCREL; 5790 break; 5791 case 1: code = BFD_RELOC_8_PCREL; break; 5792 case 2: code = BFD_RELOC_16_PCREL; break; 5793 case 4: code = BFD_RELOC_32_PCREL; break; 5794#ifdef BFD64 5795 case 8: code = BFD_RELOC_64_PCREL; break; 5796#endif 5797 } 5798 } 5799 else 5800 { 5801 switch (fixp->fx_size) 5802 { 5803 default: 5804 as_bad_where (fixp->fx_file, fixp->fx_line, 5805 _("can not do %d byte relocation"), 5806 fixp->fx_size); 5807 code = BFD_RELOC_32; 5808 break; 5809 case 1: code = BFD_RELOC_8; break; 5810 case 2: code = BFD_RELOC_16; break; 5811 case 4: code = BFD_RELOC_32; break; 5812#ifdef BFD64 5813 case 8: code = BFD_RELOC_64; break; 5814#endif 5815 } 5816 } 5817 break; 5818 } 5819 5820 if ((code == BFD_RELOC_32 5821 || code == BFD_RELOC_32_PCREL 5822 || code == BFD_RELOC_X86_64_32S) 5823 && GOT_symbol 5824 && fixp->fx_addsy == GOT_symbol) 5825 { 5826 if (!object_64bit) 5827 code = BFD_RELOC_386_GOTPC; 5828 else 5829 code = BFD_RELOC_X86_64_GOTPC32; 5830 } 5831 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) 5832 && GOT_symbol 5833 && fixp->fx_addsy == GOT_symbol) 5834 { 5835 code = BFD_RELOC_X86_64_GOTPC64; 5836 } 5837 5838 rel = (arelent *) xmalloc (sizeof (arelent)); 5839 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 5840 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 5841 5842 rel->address = fixp->fx_frag->fr_address + fixp->fx_where; 5843 5844 if (!use_rela_relocations) 5845 { 5846 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the 5847 vtable entry to be used in the relocation's section offset. */ 5848 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 5849 rel->address = fixp->fx_offset; 5850 5851 rel->addend = 0; 5852 } 5853 /* Use the rela in 64bit mode. */ 5854 else 5855 { 5856 if (!fixp->fx_pcrel) 5857 rel->addend = fixp->fx_offset; 5858 else 5859 switch (code) 5860 { 5861 case BFD_RELOC_X86_64_PLT32: 5862 case BFD_RELOC_X86_64_GOT32: 5863 case BFD_RELOC_X86_64_GOTPCREL: 5864 case BFD_RELOC_X86_64_TLSGD: 5865 case BFD_RELOC_X86_64_TLSLD: 5866 case BFD_RELOC_X86_64_GOTTPOFF: 5867 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 5868 case BFD_RELOC_X86_64_TLSDESC_CALL: 5869 rel->addend = fixp->fx_offset - fixp->fx_size; 5870 break; 5871 default: 5872 rel->addend = (section->vma 5873 - fixp->fx_size 5874 + fixp->fx_addnumber 5875 + md_pcrel_from (fixp)); 5876 break; 5877 } 5878 } 5879 5880 rel->howto = bfd_reloc_type_lookup (stdoutput, code); 5881 if (rel->howto == NULL) 5882 { 5883 as_bad_where (fixp->fx_file, fixp->fx_line, 5884 _("cannot represent relocation type %s"), 5885 bfd_get_reloc_code_name (code)); 5886 /* Set howto to a garbage value so that we can keep going. */ 5887 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); 5888 assert (rel->howto != NULL); 5889 } 5890 5891 return rel; 5892} 5893 5894 5895/* Parse operands using Intel syntax. This implements a recursive descent 5896 parser based on the BNF grammar published in Appendix B of the MASM 6.1 5897 Programmer's Guide. 5898 5899 FIXME: We do not recognize the full operand grammar defined in the MASM 5900 documentation. In particular, all the structure/union and 5901 high-level macro operands are missing. 5902 5903 Uppercase words are terminals, lower case words are non-terminals. 5904 Objects surrounded by double brackets '[[' ']]' are optional. Vertical 5905 bars '|' denote choices. Most grammar productions are implemented in 5906 functions called 'intel_<production>'. 5907 5908 Initial production is 'expr'. 5909 5910 addOp + | - 5911 5912 alpha [a-zA-Z] 5913 5914 binOp & | AND | \| | OR | ^ | XOR 5915 5916 byteRegister AL | AH | BL | BH | CL | CH | DL | DH 5917 5918 constant digits [[ radixOverride ]] 5919 5920 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD 5921 5922 digits decdigit 5923 | digits decdigit 5924 | digits hexdigit 5925 5926 decdigit [0-9] 5927 5928 e04 e04 addOp e05 5929 | e05 5930 5931 e05 e05 binOp e06 5932 | e06 5933 5934 e06 e06 mulOp e09 5935 | e09 5936 5937 e09 OFFSET e10 5938 | SHORT e10 5939 | + e10 5940 | - e10 5941 | ~ e10 5942 | NOT e10 5943 | e09 PTR e10 5944 | e09 : e10 5945 | e10 5946 5947 e10 e10 [ expr ] 5948 | e11 5949 5950 e11 ( expr ) 5951 | [ expr ] 5952 | constant 5953 | dataType 5954 | id 5955 | $ 5956 | register 5957 5958 => expr expr cmpOp e04 5959 | e04 5960 5961 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX 5962 | BP | EBP | SP | ESP | DI | EDI | SI | ESI 5963 5964 hexdigit a | b | c | d | e | f 5965 | A | B | C | D | E | F 5966 5967 id alpha 5968 | id alpha 5969 | id decdigit 5970 5971 mulOp * | / | % | MOD | << | SHL | >> | SHR 5972 5973 quote " | ' 5974 5975 register specialRegister 5976 | gpRegister 5977 | byteRegister 5978 5979 segmentRegister CS | DS | ES | FS | GS | SS 5980 5981 specialRegister CR0 | CR2 | CR3 | CR4 5982 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 5983 | TR3 | TR4 | TR5 | TR6 | TR7 5984 5985 We simplify the grammar in obvious places (e.g., register parsing is 5986 done by calling parse_register) and eliminate immediate left recursion 5987 to implement a recursive-descent parser. 5988 5989 expr e04 expr' 5990 5991 expr' cmpOp e04 expr' 5992 | Empty 5993 5994 e04 e05 e04' 5995 5996 e04' addOp e05 e04' 5997 | Empty 5998 5999 e05 e06 e05' 6000 6001 e05' binOp e06 e05' 6002 | Empty 6003 6004 e06 e09 e06' 6005 6006 e06' mulOp e09 e06' 6007 | Empty 6008 6009 e09 OFFSET e10 e09' 6010 | SHORT e10' 6011 | + e10' 6012 | - e10' 6013 | ~ e10' 6014 | NOT e10' 6015 | e10 e09' 6016 6017 e09' PTR e10 e09' 6018 | : e10 e09' 6019 | Empty 6020 6021 e10 e11 e10' 6022 6023 e10' [ expr ] e10' 6024 | Empty 6025 6026 e11 ( expr ) 6027 | [ expr ] 6028 | BYTE 6029 | WORD 6030 | DWORD 6031 | FWORD 6032 | QWORD 6033 | TBYTE 6034 | OWORD 6035 | XMMWORD 6036 | . 6037 | $ 6038 | register 6039 | id 6040 | constant */ 6041 6042/* Parsing structure for the intel syntax parser. Used to implement the 6043 semantic actions for the operand grammar. */ 6044struct intel_parser_s 6045 { 6046 char *op_string; /* The string being parsed. */ 6047 int got_a_float; /* Whether the operand is a float. */ 6048 int op_modifier; /* Operand modifier. */ 6049 int is_mem; /* 1 if operand is memory reference. */ 6050 int in_offset; /* >=1 if parsing operand of offset. */ 6051 int in_bracket; /* >=1 if parsing operand in brackets. */ 6052 const reg_entry *reg; /* Last register reference found. */ 6053 char *disp; /* Displacement string being built. */ 6054 char *next_operand; /* Resume point when splitting operands. */ 6055 }; 6056 6057static struct intel_parser_s intel_parser; 6058 6059/* Token structure for parsing intel syntax. */ 6060struct intel_token 6061 { 6062 int code; /* Token code. */ 6063 const reg_entry *reg; /* Register entry for register tokens. */ 6064 char *str; /* String representation. */ 6065 }; 6066 6067static struct intel_token cur_token, prev_token; 6068 6069/* Token codes for the intel parser. Since T_SHORT is already used 6070 by COFF, undefine it first to prevent a warning. */ 6071#define T_NIL -1 6072#define T_CONST 1 6073#define T_REG 2 6074#define T_BYTE 3 6075#define T_WORD 4 6076#define T_DWORD 5 6077#define T_FWORD 6 6078#define T_QWORD 7 6079#define T_TBYTE 8 6080#define T_XMMWORD 9 6081#undef T_SHORT 6082#define T_SHORT 10 6083#define T_OFFSET 11 6084#define T_PTR 12 6085#define T_ID 13 6086#define T_SHL 14 6087#define T_SHR 15 6088 6089/* Prototypes for intel parser functions. */ 6090static int intel_match_token PARAMS ((int code)); 6091static void intel_get_token PARAMS ((void)); 6092static void intel_putback_token PARAMS ((void)); 6093static int intel_expr PARAMS ((void)); 6094static int intel_e04 PARAMS ((void)); 6095static int intel_e05 PARAMS ((void)); 6096static int intel_e06 PARAMS ((void)); 6097static int intel_e09 PARAMS ((void)); 6098static int intel_bracket_expr PARAMS ((void)); 6099static int intel_e10 PARAMS ((void)); 6100static int intel_e11 PARAMS ((void)); 6101 6102static int 6103i386_intel_operand (operand_string, got_a_float) 6104 char *operand_string; 6105 int got_a_float; 6106{ 6107 int ret; 6108 char *p; 6109 6110 p = intel_parser.op_string = xstrdup (operand_string); 6111 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1); 6112 6113 for (;;) 6114 { 6115 /* Initialize token holders. */ 6116 cur_token.code = prev_token.code = T_NIL; 6117 cur_token.reg = prev_token.reg = NULL; 6118 cur_token.str = prev_token.str = NULL; 6119 6120 /* Initialize parser structure. */ 6121 intel_parser.got_a_float = got_a_float; 6122 intel_parser.op_modifier = 0; 6123 intel_parser.is_mem = 0; 6124 intel_parser.in_offset = 0; 6125 intel_parser.in_bracket = 0; 6126 intel_parser.reg = NULL; 6127 intel_parser.disp[0] = '\0'; 6128 intel_parser.next_operand = NULL; 6129 6130 /* Read the first token and start the parser. */ 6131 intel_get_token (); 6132 ret = intel_expr (); 6133 6134 if (!ret) 6135 break; 6136 6137 if (cur_token.code != T_NIL) 6138 { 6139 as_bad (_("invalid operand for '%s' ('%s' unexpected)"), 6140 current_templates->start->name, cur_token.str); 6141 ret = 0; 6142 } 6143 /* If we found a memory reference, hand it over to i386_displacement 6144 to fill in the rest of the operand fields. */ 6145 else if (intel_parser.is_mem) 6146 { 6147 if ((i.mem_operands == 1 6148 && (current_templates->start->opcode_modifier & IsString) == 0) 6149 || i.mem_operands == 2) 6150 { 6151 as_bad (_("too many memory references for '%s'"), 6152 current_templates->start->name); 6153 ret = 0; 6154 } 6155 else 6156 { 6157 char *s = intel_parser.disp; 6158 i.mem_operands++; 6159 6160 if (!quiet_warnings && intel_parser.is_mem < 0) 6161 /* See the comments in intel_bracket_expr. */ 6162 as_warn (_("Treating `%s' as memory reference"), operand_string); 6163 6164 /* Add the displacement expression. */ 6165 if (*s != '\0') 6166 ret = i386_displacement (s, s + strlen (s)); 6167 if (ret) 6168 { 6169 /* Swap base and index in 16-bit memory operands like 6170 [si+bx]. Since i386_index_check is also used in AT&T 6171 mode we have to do that here. */ 6172 if (i.base_reg 6173 && i.index_reg 6174 && (i.base_reg->reg_type & Reg16) 6175 && (i.index_reg->reg_type & Reg16) 6176 && i.base_reg->reg_num >= 6 6177 && i.index_reg->reg_num < 6) 6178 { 6179 const reg_entry *base = i.index_reg; 6180 6181 i.index_reg = i.base_reg; 6182 i.base_reg = base; 6183 } 6184 ret = i386_index_check (operand_string); 6185 } 6186 } 6187 } 6188 6189 /* Constant and OFFSET expressions are handled by i386_immediate. */ 6190 else if ((intel_parser.op_modifier & (1 << T_OFFSET)) 6191 || intel_parser.reg == NULL) 6192 ret = i386_immediate (intel_parser.disp); 6193 6194 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1) 6195 ret = 0; 6196 if (!ret || !intel_parser.next_operand) 6197 break; 6198 intel_parser.op_string = intel_parser.next_operand; 6199 this_operand = i.operands++; 6200 } 6201 6202 free (p); 6203 free (intel_parser.disp); 6204 6205 return ret; 6206} 6207 6208#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg) 6209 6210/* expr e04 expr' 6211 6212 expr' cmpOp e04 expr' 6213 | Empty */ 6214static int 6215intel_expr () 6216{ 6217 /* XXX Implement the comparison operators. */ 6218 return intel_e04 (); 6219} 6220 6221/* e04 e05 e04' 6222 6223 e04' addOp e05 e04' 6224 | Empty */ 6225static int 6226intel_e04 () 6227{ 6228 int nregs = -1; 6229 6230 for (;;) 6231 { 6232 if (!intel_e05()) 6233 return 0; 6234 6235 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) 6236 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */ 6237 6238 if (cur_token.code == '+') 6239 nregs = -1; 6240 else if (cur_token.code == '-') 6241 nregs = NUM_ADDRESS_REGS; 6242 else 6243 return 1; 6244 6245 strcat (intel_parser.disp, cur_token.str); 6246 intel_match_token (cur_token.code); 6247 } 6248} 6249 6250/* e05 e06 e05' 6251 6252 e05' binOp e06 e05' 6253 | Empty */ 6254static int 6255intel_e05 () 6256{ 6257 int nregs = ~NUM_ADDRESS_REGS; 6258 6259 for (;;) 6260 { 6261 if (!intel_e06()) 6262 return 0; 6263 6264 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^') 6265 { 6266 char str[2]; 6267 6268 str[0] = cur_token.code; 6269 str[1] = 0; 6270 strcat (intel_parser.disp, str); 6271 } 6272 else 6273 break; 6274 6275 intel_match_token (cur_token.code); 6276 6277 if (nregs < 0) 6278 nregs = ~nregs; 6279 } 6280 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) 6281 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */ 6282 return 1; 6283} 6284 6285/* e06 e09 e06' 6286 6287 e06' mulOp e09 e06' 6288 | Empty */ 6289static int 6290intel_e06 () 6291{ 6292 int nregs = ~NUM_ADDRESS_REGS; 6293 6294 for (;;) 6295 { 6296 if (!intel_e09()) 6297 return 0; 6298 6299 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%') 6300 { 6301 char str[2]; 6302 6303 str[0] = cur_token.code; 6304 str[1] = 0; 6305 strcat (intel_parser.disp, str); 6306 } 6307 else if (cur_token.code == T_SHL) 6308 strcat (intel_parser.disp, "<<"); 6309 else if (cur_token.code == T_SHR) 6310 strcat (intel_parser.disp, ">>"); 6311 else 6312 break; 6313 6314 intel_match_token (cur_token.code); 6315 6316 if (nregs < 0) 6317 nregs = ~nregs; 6318 } 6319 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) 6320 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */ 6321 return 1; 6322} 6323 6324/* e09 OFFSET e09 6325 | SHORT e09 6326 | + e09 6327 | - e09 6328 | ~ e09 6329 | NOT e09 6330 | e10 e09' 6331 6332 e09' PTR e10 e09' 6333 | : e10 e09' 6334 | Empty */ 6335static int 6336intel_e09 () 6337{ 6338 int nregs = ~NUM_ADDRESS_REGS; 6339 int in_offset = 0; 6340 6341 for (;;) 6342 { 6343 /* Don't consume constants here. */ 6344 if (cur_token.code == '+' || cur_token.code == '-') 6345 { 6346 /* Need to look one token ahead - if the next token 6347 is a constant, the current token is its sign. */ 6348 int next_code; 6349 6350 intel_match_token (cur_token.code); 6351 next_code = cur_token.code; 6352 intel_putback_token (); 6353 if (next_code == T_CONST) 6354 break; 6355 } 6356 6357 /* e09 OFFSET e09 */ 6358 if (cur_token.code == T_OFFSET) 6359 { 6360 if (!in_offset++) 6361 ++intel_parser.in_offset; 6362 } 6363 6364 /* e09 SHORT e09 */ 6365 else if (cur_token.code == T_SHORT) 6366 intel_parser.op_modifier |= 1 << T_SHORT; 6367 6368 /* e09 + e09 */ 6369 else if (cur_token.code == '+') 6370 strcat (intel_parser.disp, "+"); 6371 6372 /* e09 - e09 6373 | ~ e09 6374 | NOT e09 */ 6375 else if (cur_token.code == '-' || cur_token.code == '~') 6376 { 6377 char str[2]; 6378 6379 if (nregs < 0) 6380 nregs = ~nregs; 6381 str[0] = cur_token.code; 6382 str[1] = 0; 6383 strcat (intel_parser.disp, str); 6384 } 6385 6386 /* e09 e10 e09' */ 6387 else 6388 break; 6389 6390 intel_match_token (cur_token.code); 6391 } 6392 6393 for (;;) 6394 { 6395 if (!intel_e10 ()) 6396 return 0; 6397 6398 /* e09' PTR e10 e09' */ 6399 if (cur_token.code == T_PTR) 6400 { 6401 char suffix; 6402 6403 if (prev_token.code == T_BYTE) 6404 suffix = BYTE_MNEM_SUFFIX; 6405 6406 else if (prev_token.code == T_WORD) 6407 { 6408 if (current_templates->start->name[0] == 'l' 6409 && current_templates->start->name[2] == 's' 6410 && current_templates->start->name[3] == 0) 6411 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ 6412 else if (intel_parser.got_a_float == 2) /* "fi..." */ 6413 suffix = SHORT_MNEM_SUFFIX; 6414 else 6415 suffix = WORD_MNEM_SUFFIX; 6416 } 6417 6418 else if (prev_token.code == T_DWORD) 6419 { 6420 if (current_templates->start->name[0] == 'l' 6421 && current_templates->start->name[2] == 's' 6422 && current_templates->start->name[3] == 0) 6423 suffix = WORD_MNEM_SUFFIX; 6424 else if (flag_code == CODE_16BIT 6425 && (current_templates->start->opcode_modifier 6426 & (Jump | JumpDword))) 6427 suffix = LONG_DOUBLE_MNEM_SUFFIX; 6428 else if (intel_parser.got_a_float == 1) /* "f..." */ 6429 suffix = SHORT_MNEM_SUFFIX; 6430 else 6431 suffix = LONG_MNEM_SUFFIX; 6432 } 6433 6434 else if (prev_token.code == T_FWORD) 6435 { 6436 if (current_templates->start->name[0] == 'l' 6437 && current_templates->start->name[2] == 's' 6438 && current_templates->start->name[3] == 0) 6439 suffix = LONG_MNEM_SUFFIX; 6440 else if (!intel_parser.got_a_float) 6441 { 6442 if (flag_code == CODE_16BIT) 6443 add_prefix (DATA_PREFIX_OPCODE); 6444 suffix = LONG_DOUBLE_MNEM_SUFFIX; 6445 } 6446 else 6447 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ 6448 } 6449 6450 else if (prev_token.code == T_QWORD) 6451 { 6452 if (intel_parser.got_a_float == 1) /* "f..." */ 6453 suffix = LONG_MNEM_SUFFIX; 6454 else 6455 suffix = QWORD_MNEM_SUFFIX; 6456 } 6457 6458 else if (prev_token.code == T_TBYTE) 6459 { 6460 if (intel_parser.got_a_float == 1) 6461 suffix = LONG_DOUBLE_MNEM_SUFFIX; 6462 else 6463 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ 6464 } 6465 6466 else if (prev_token.code == T_XMMWORD) 6467 { 6468 /* XXX ignored for now, but accepted since gcc uses it */ 6469 suffix = 0; 6470 } 6471 6472 else 6473 { 6474 as_bad (_("Unknown operand modifier `%s'"), prev_token.str); 6475 return 0; 6476 } 6477 6478 /* Operands for jump/call using 'ptr' notation denote absolute 6479 addresses. */ 6480 if (current_templates->start->opcode_modifier & (Jump | JumpDword)) 6481 i.types[this_operand] |= JumpAbsolute; 6482 6483 if (current_templates->start->base_opcode == 0x8d /* lea */) 6484 ; 6485 else if (!i.suffix) 6486 i.suffix = suffix; 6487 else if (i.suffix != suffix) 6488 { 6489 as_bad (_("Conflicting operand modifiers")); 6490 return 0; 6491 } 6492 6493 } 6494 6495 /* e09' : e10 e09' */ 6496 else if (cur_token.code == ':') 6497 { 6498 if (prev_token.code != T_REG) 6499 { 6500 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a 6501 segment/group identifier (which we don't have), using comma 6502 as the operand separator there is even less consistent, since 6503 there all branches only have a single operand. */ 6504 if (this_operand != 0 6505 || intel_parser.in_offset 6506 || intel_parser.in_bracket 6507 || (!(current_templates->start->opcode_modifier 6508 & (Jump|JumpDword|JumpInterSegment)) 6509 && !(current_templates->start->operand_types[0] 6510 & JumpAbsolute))) 6511 return intel_match_token (T_NIL); 6512 /* Remember the start of the 2nd operand and terminate 1st 6513 operand here. 6514 XXX This isn't right, yet (when SSSS:OOOO is right operand of 6515 another expression), but it gets at least the simplest case 6516 (a plain number or symbol on the left side) right. */ 6517 intel_parser.next_operand = intel_parser.op_string; 6518 *--intel_parser.op_string = '\0'; 6519 return intel_match_token (':'); 6520 } 6521 } 6522 6523 /* e09' Empty */ 6524 else 6525 break; 6526 6527 intel_match_token (cur_token.code); 6528 6529 } 6530 6531 if (in_offset) 6532 { 6533 --intel_parser.in_offset; 6534 if (nregs < 0) 6535 nregs = ~nregs; 6536 if (NUM_ADDRESS_REGS > nregs) 6537 { 6538 as_bad (_("Invalid operand to `OFFSET'")); 6539 return 0; 6540 } 6541 intel_parser.op_modifier |= 1 << T_OFFSET; 6542 } 6543 6544 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) 6545 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */ 6546 return 1; 6547} 6548 6549static int 6550intel_bracket_expr () 6551{ 6552 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET); 6553 const char *start = intel_parser.op_string; 6554 int len; 6555 6556 if (i.op[this_operand].regs) 6557 return intel_match_token (T_NIL); 6558 6559 intel_match_token ('['); 6560 6561 /* Mark as a memory operand only if it's not already known to be an 6562 offset expression. If it's an offset expression, we need to keep 6563 the brace in. */ 6564 if (!intel_parser.in_offset) 6565 { 6566 ++intel_parser.in_bracket; 6567 6568 /* Operands for jump/call inside brackets denote absolute addresses. */ 6569 if (current_templates->start->opcode_modifier & (Jump | JumpDword)) 6570 i.types[this_operand] |= JumpAbsolute; 6571 6572 /* Unfortunately gas always diverged from MASM in a respect that can't 6573 be easily fixed without risking to break code sequences likely to be 6574 encountered (the testsuite even check for this): MASM doesn't consider 6575 an expression inside brackets unconditionally as a memory reference. 6576 When that is e.g. a constant, an offset expression, or the sum of the 6577 two, this is still taken as a constant load. gas, however, always 6578 treated these as memory references. As a compromise, we'll try to make 6579 offset expressions inside brackets work the MASM way (since that's 6580 less likely to be found in real world code), but make constants alone 6581 continue to work the traditional gas way. In either case, issue a 6582 warning. */ 6583 intel_parser.op_modifier &= ~was_offset; 6584 } 6585 else 6586 strcat (intel_parser.disp, "["); 6587 6588 /* Add a '+' to the displacement string if necessary. */ 6589 if (*intel_parser.disp != '\0' 6590 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') 6591 strcat (intel_parser.disp, "+"); 6592 6593 if (intel_expr () 6594 && (len = intel_parser.op_string - start - 1, 6595 intel_match_token (']'))) 6596 { 6597 /* Preserve brackets when the operand is an offset expression. */ 6598 if (intel_parser.in_offset) 6599 strcat (intel_parser.disp, "]"); 6600 else 6601 { 6602 --intel_parser.in_bracket; 6603 if (i.base_reg || i.index_reg) 6604 intel_parser.is_mem = 1; 6605 if (!intel_parser.is_mem) 6606 { 6607 if (!(intel_parser.op_modifier & (1 << T_OFFSET))) 6608 /* Defer the warning until all of the operand was parsed. */ 6609 intel_parser.is_mem = -1; 6610 else if (!quiet_warnings) 6611 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start); 6612 } 6613 } 6614 intel_parser.op_modifier |= was_offset; 6615 6616 return 1; 6617 } 6618 return 0; 6619} 6620 6621/* e10 e11 e10' 6622 6623 e10' [ expr ] e10' 6624 | Empty */ 6625static int 6626intel_e10 () 6627{ 6628 if (!intel_e11 ()) 6629 return 0; 6630 6631 while (cur_token.code == '[') 6632 { 6633 if (!intel_bracket_expr ()) 6634 return 0; 6635 } 6636 6637 return 1; 6638} 6639 6640/* e11 ( expr ) 6641 | [ expr ] 6642 | BYTE 6643 | WORD 6644 | DWORD 6645 | FWORD 6646 | QWORD 6647 | TBYTE 6648 | OWORD 6649 | XMMWORD 6650 | $ 6651 | . 6652 | register 6653 | id 6654 | constant */ 6655static int 6656intel_e11 () 6657{ 6658 switch (cur_token.code) 6659 { 6660 /* e11 ( expr ) */ 6661 case '(': 6662 intel_match_token ('('); 6663 strcat (intel_parser.disp, "("); 6664 6665 if (intel_expr () && intel_match_token (')')) 6666 { 6667 strcat (intel_parser.disp, ")"); 6668 return 1; 6669 } 6670 return 0; 6671 6672 /* e11 [ expr ] */ 6673 case '[': 6674 return intel_bracket_expr (); 6675 6676 /* e11 $ 6677 | . */ 6678 case '.': 6679 strcat (intel_parser.disp, cur_token.str); 6680 intel_match_token (cur_token.code); 6681 6682 /* Mark as a memory operand only if it's not already known to be an 6683 offset expression. */ 6684 if (!intel_parser.in_offset) 6685 intel_parser.is_mem = 1; 6686 6687 return 1; 6688 6689 /* e11 register */ 6690 case T_REG: 6691 { 6692 const reg_entry *reg = intel_parser.reg = cur_token.reg; 6693 6694 intel_match_token (T_REG); 6695 6696 /* Check for segment change. */ 6697 if (cur_token.code == ':') 6698 { 6699 if (!(reg->reg_type & (SReg2 | SReg3))) 6700 { 6701 as_bad (_("`%s' is not a valid segment register"), reg->reg_name); 6702 return 0; 6703 } 6704 else if (i.seg[i.mem_operands]) 6705 as_warn (_("Extra segment override ignored")); 6706 else 6707 { 6708 if (!intel_parser.in_offset) 6709 intel_parser.is_mem = 1; 6710 switch (reg->reg_num) 6711 { 6712 case 0: 6713 i.seg[i.mem_operands] = &es; 6714 break; 6715 case 1: 6716 i.seg[i.mem_operands] = &cs; 6717 break; 6718 case 2: 6719 i.seg[i.mem_operands] = &ss; 6720 break; 6721 case 3: 6722 i.seg[i.mem_operands] = &ds; 6723 break; 6724 case 4: 6725 i.seg[i.mem_operands] = &fs; 6726 break; 6727 case 5: 6728 i.seg[i.mem_operands] = &gs; 6729 break; 6730 } 6731 } 6732 } 6733 6734 /* Not a segment register. Check for register scaling. */ 6735 else if (cur_token.code == '*') 6736 { 6737 if (!intel_parser.in_bracket) 6738 { 6739 as_bad (_("Register scaling only allowed in memory operands")); 6740 return 0; 6741 } 6742 6743 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */ 6744 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */ 6745 else if (i.index_reg) 6746 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */ 6747 6748 /* What follows must be a valid scale. */ 6749 intel_match_token ('*'); 6750 i.index_reg = reg; 6751 i.types[this_operand] |= BaseIndex; 6752 6753 /* Set the scale after setting the register (otherwise, 6754 i386_scale will complain) */ 6755 if (cur_token.code == '+' || cur_token.code == '-') 6756 { 6757 char *str, sign = cur_token.code; 6758 intel_match_token (cur_token.code); 6759 if (cur_token.code != T_CONST) 6760 { 6761 as_bad (_("Syntax error: Expecting a constant, got `%s'"), 6762 cur_token.str); 6763 return 0; 6764 } 6765 str = (char *) xmalloc (strlen (cur_token.str) + 2); 6766 strcpy (str + 1, cur_token.str); 6767 *str = sign; 6768 if (!i386_scale (str)) 6769 return 0; 6770 free (str); 6771 } 6772 else if (!i386_scale (cur_token.str)) 6773 return 0; 6774 intel_match_token (cur_token.code); 6775 } 6776 6777 /* No scaling. If this is a memory operand, the register is either a 6778 base register (first occurrence) or an index register (second 6779 occurrence). */ 6780 else if (intel_parser.in_bracket) 6781 { 6782 6783 if (!i.base_reg) 6784 i.base_reg = reg; 6785 else if (!i.index_reg) 6786 i.index_reg = reg; 6787 else 6788 { 6789 as_bad (_("Too many register references in memory operand")); 6790 return 0; 6791 } 6792 6793 i.types[this_operand] |= BaseIndex; 6794 } 6795 6796 /* It's neither base nor index. */ 6797 else if (!intel_parser.in_offset && !intel_parser.is_mem) 6798 { 6799 i.types[this_operand] |= reg->reg_type & ~BaseIndex; 6800 i.op[this_operand].regs = reg; 6801 i.reg_operands++; 6802 } 6803 else 6804 { 6805 as_bad (_("Invalid use of register")); 6806 return 0; 6807 } 6808 6809 /* Since registers are not part of the displacement string (except 6810 when we're parsing offset operands), we may need to remove any 6811 preceding '+' from the displacement string. */ 6812 if (*intel_parser.disp != '\0' 6813 && !intel_parser.in_offset) 6814 { 6815 char *s = intel_parser.disp; 6816 s += strlen (s) - 1; 6817 if (*s == '+') 6818 *s = '\0'; 6819 } 6820 6821 return 1; 6822 } 6823 6824 /* e11 BYTE 6825 | WORD 6826 | DWORD 6827 | FWORD 6828 | QWORD 6829 | TBYTE 6830 | OWORD 6831 | XMMWORD */ 6832 case T_BYTE: 6833 case T_WORD: 6834 case T_DWORD: 6835 case T_FWORD: 6836 case T_QWORD: 6837 case T_TBYTE: 6838 case T_XMMWORD: 6839 intel_match_token (cur_token.code); 6840 6841 if (cur_token.code == T_PTR) 6842 return 1; 6843 6844 /* It must have been an identifier. */ 6845 intel_putback_token (); 6846 cur_token.code = T_ID; 6847 /* FALLTHRU */ 6848 6849 /* e11 id 6850 | constant */ 6851 case T_ID: 6852 if (!intel_parser.in_offset && intel_parser.is_mem <= 0) 6853 { 6854 symbolS *symbolP; 6855 6856 /* The identifier represents a memory reference only if it's not 6857 preceded by an offset modifier and if it's not an equate. */ 6858 symbolP = symbol_find(cur_token.str); 6859 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section) 6860 intel_parser.is_mem = 1; 6861 } 6862 /* FALLTHRU */ 6863 6864 case T_CONST: 6865 case '-': 6866 case '+': 6867 { 6868 char *save_str, sign = 0; 6869 6870 /* Allow constants that start with `+' or `-'. */ 6871 if (cur_token.code == '-' || cur_token.code == '+') 6872 { 6873 sign = cur_token.code; 6874 intel_match_token (cur_token.code); 6875 if (cur_token.code != T_CONST) 6876 { 6877 as_bad (_("Syntax error: Expecting a constant, got `%s'"), 6878 cur_token.str); 6879 return 0; 6880 } 6881 } 6882 6883 save_str = (char *) xmalloc (strlen (cur_token.str) + 2); 6884 strcpy (save_str + !!sign, cur_token.str); 6885 if (sign) 6886 *save_str = sign; 6887 6888 /* Get the next token to check for register scaling. */ 6889 intel_match_token (cur_token.code); 6890 6891 /* Check if this constant is a scaling factor for an index register. */ 6892 if (cur_token.code == '*') 6893 { 6894 if (intel_match_token ('*') && cur_token.code == T_REG) 6895 { 6896 const reg_entry *reg = cur_token.reg; 6897 6898 if (!intel_parser.in_bracket) 6899 { 6900 as_bad (_("Register scaling only allowed in memory operands")); 6901 return 0; 6902 } 6903 6904 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */ 6905 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */ 6906 else if (i.index_reg) 6907 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */ 6908 6909 /* The constant is followed by `* reg', so it must be 6910 a valid scale. */ 6911 i.index_reg = reg; 6912 i.types[this_operand] |= BaseIndex; 6913 6914 /* Set the scale after setting the register (otherwise, 6915 i386_scale will complain) */ 6916 if (!i386_scale (save_str)) 6917 return 0; 6918 intel_match_token (T_REG); 6919 6920 /* Since registers are not part of the displacement 6921 string, we may need to remove any preceding '+' from 6922 the displacement string. */ 6923 if (*intel_parser.disp != '\0') 6924 { 6925 char *s = intel_parser.disp; 6926 s += strlen (s) - 1; 6927 if (*s == '+') 6928 *s = '\0'; 6929 } 6930 6931 free (save_str); 6932 6933 return 1; 6934 } 6935 6936 /* The constant was not used for register scaling. Since we have 6937 already consumed the token following `*' we now need to put it 6938 back in the stream. */ 6939 intel_putback_token (); 6940 } 6941 6942 /* Add the constant to the displacement string. */ 6943 strcat (intel_parser.disp, save_str); 6944 free (save_str); 6945 6946 return 1; 6947 } 6948 } 6949 6950 as_bad (_("Unrecognized token '%s'"), cur_token.str); 6951 return 0; 6952} 6953 6954/* Match the given token against cur_token. If they match, read the next 6955 token from the operand string. */ 6956static int 6957intel_match_token (code) 6958 int code; 6959{ 6960 if (cur_token.code == code) 6961 { 6962 intel_get_token (); 6963 return 1; 6964 } 6965 else 6966 { 6967 as_bad (_("Unexpected token `%s'"), cur_token.str); 6968 return 0; 6969 } 6970} 6971 6972/* Read a new token from intel_parser.op_string and store it in cur_token. */ 6973static void 6974intel_get_token () 6975{ 6976 char *end_op; 6977 const reg_entry *reg; 6978 struct intel_token new_token; 6979 6980 new_token.code = T_NIL; 6981 new_token.reg = NULL; 6982 new_token.str = NULL; 6983 6984 /* Free the memory allocated to the previous token and move 6985 cur_token to prev_token. */ 6986 if (prev_token.str) 6987 free (prev_token.str); 6988 6989 prev_token = cur_token; 6990 6991 /* Skip whitespace. */ 6992 while (is_space_char (*intel_parser.op_string)) 6993 intel_parser.op_string++; 6994 6995 /* Return an empty token if we find nothing else on the line. */ 6996 if (*intel_parser.op_string == '\0') 6997 { 6998 cur_token = new_token; 6999 return; 7000 } 7001 7002 /* The new token cannot be larger than the remainder of the operand 7003 string. */ 7004 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1); 7005 new_token.str[0] = '\0'; 7006 7007 if (strchr ("0123456789", *intel_parser.op_string)) 7008 { 7009 char *p = new_token.str; 7010 char *q = intel_parser.op_string; 7011 new_token.code = T_CONST; 7012 7013 /* Allow any kind of identifier char to encompass floating point and 7014 hexadecimal numbers. */ 7015 while (is_identifier_char (*q)) 7016 *p++ = *q++; 7017 *p = '\0'; 7018 7019 /* Recognize special symbol names [0-9][bf]. */ 7020 if (strlen (intel_parser.op_string) == 2 7021 && (intel_parser.op_string[1] == 'b' 7022 || intel_parser.op_string[1] == 'f')) 7023 new_token.code = T_ID; 7024 } 7025 7026 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL) 7027 { 7028 size_t len = end_op - intel_parser.op_string; 7029 7030 new_token.code = T_REG; 7031 new_token.reg = reg; 7032 7033 memcpy (new_token.str, intel_parser.op_string, len); 7034 new_token.str[len] = '\0'; 7035 } 7036 7037 else if (is_identifier_char (*intel_parser.op_string)) 7038 { 7039 char *p = new_token.str; 7040 char *q = intel_parser.op_string; 7041 7042 /* A '.' or '$' followed by an identifier char is an identifier. 7043 Otherwise, it's operator '.' followed by an expression. */ 7044 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) 7045 { 7046 new_token.code = '.'; 7047 new_token.str[0] = '.'; 7048 new_token.str[1] = '\0'; 7049 } 7050 else 7051 { 7052 while (is_identifier_char (*q) || *q == '@') 7053 *p++ = *q++; 7054 *p = '\0'; 7055 7056 if (strcasecmp (new_token.str, "NOT") == 0) 7057 new_token.code = '~'; 7058 7059 else if (strcasecmp (new_token.str, "MOD") == 0) 7060 new_token.code = '%'; 7061 7062 else if (strcasecmp (new_token.str, "AND") == 0) 7063 new_token.code = '&'; 7064 7065 else if (strcasecmp (new_token.str, "OR") == 0) 7066 new_token.code = '|'; 7067 7068 else if (strcasecmp (new_token.str, "XOR") == 0) 7069 new_token.code = '^'; 7070 7071 else if (strcasecmp (new_token.str, "SHL") == 0) 7072 new_token.code = T_SHL; 7073 7074 else if (strcasecmp (new_token.str, "SHR") == 0) 7075 new_token.code = T_SHR; 7076 7077 else if (strcasecmp (new_token.str, "BYTE") == 0) 7078 new_token.code = T_BYTE; 7079 7080 else if (strcasecmp (new_token.str, "WORD") == 0) 7081 new_token.code = T_WORD; 7082 7083 else if (strcasecmp (new_token.str, "DWORD") == 0) 7084 new_token.code = T_DWORD; 7085 7086 else if (strcasecmp (new_token.str, "FWORD") == 0) 7087 new_token.code = T_FWORD; 7088 7089 else if (strcasecmp (new_token.str, "QWORD") == 0) 7090 new_token.code = T_QWORD; 7091 7092 else if (strcasecmp (new_token.str, "TBYTE") == 0 7093 /* XXX remove (gcc still uses it) */ 7094 || strcasecmp (new_token.str, "XWORD") == 0) 7095 new_token.code = T_TBYTE; 7096 7097 else if (strcasecmp (new_token.str, "XMMWORD") == 0 7098 || strcasecmp (new_token.str, "OWORD") == 0) 7099 new_token.code = T_XMMWORD; 7100 7101 else if (strcasecmp (new_token.str, "PTR") == 0) 7102 new_token.code = T_PTR; 7103 7104 else if (strcasecmp (new_token.str, "SHORT") == 0) 7105 new_token.code = T_SHORT; 7106 7107 else if (strcasecmp (new_token.str, "OFFSET") == 0) 7108 { 7109 new_token.code = T_OFFSET; 7110 7111 /* ??? This is not mentioned in the MASM grammar but gcc 7112 makes use of it with -mintel-syntax. OFFSET may be 7113 followed by FLAT: */ 7114 if (strncasecmp (q, " FLAT:", 6) == 0) 7115 strcat (new_token.str, " FLAT:"); 7116 } 7117 7118 /* ??? This is not mentioned in the MASM grammar. */ 7119 else if (strcasecmp (new_token.str, "FLAT") == 0) 7120 { 7121 new_token.code = T_OFFSET; 7122 if (*q == ':') 7123 strcat (new_token.str, ":"); 7124 else 7125 as_bad (_("`:' expected")); 7126 } 7127 7128 else 7129 new_token.code = T_ID; 7130 } 7131 } 7132 7133 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string)) 7134 { 7135 new_token.code = *intel_parser.op_string; 7136 new_token.str[0] = *intel_parser.op_string; 7137 new_token.str[1] = '\0'; 7138 } 7139 7140 else if (strchr ("<>", *intel_parser.op_string) 7141 && *intel_parser.op_string == *(intel_parser.op_string + 1)) 7142 { 7143 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR; 7144 new_token.str[0] = *intel_parser.op_string; 7145 new_token.str[1] = *intel_parser.op_string; 7146 new_token.str[2] = '\0'; 7147 } 7148 7149 else 7150 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string); 7151 7152 intel_parser.op_string += strlen (new_token.str); 7153 cur_token = new_token; 7154} 7155 7156/* Put cur_token back into the token stream and make cur_token point to 7157 prev_token. */ 7158static void 7159intel_putback_token () 7160{ 7161 if (cur_token.code != T_NIL) 7162 { 7163 intel_parser.op_string -= strlen (cur_token.str); 7164 free (cur_token.str); 7165 } 7166 cur_token = prev_token; 7167 7168 /* Forget prev_token. */ 7169 prev_token.code = T_NIL; 7170 prev_token.reg = NULL; 7171 prev_token.str = NULL; 7172} 7173 7174int 7175tc_x86_regname_to_dw2regnum (const char *regname) 7176{ 7177 unsigned int regnum; 7178 unsigned int regnames_count; 7179 static const char *const regnames_32[] = 7180 { 7181 "eax", "ecx", "edx", "ebx", 7182 "esp", "ebp", "esi", "edi", 7183 "eip", "eflags", NULL, 7184 "st0", "st1", "st2", "st3", 7185 "st4", "st5", "st6", "st7", 7186 NULL, NULL, 7187 "xmm0", "xmm1", "xmm2", "xmm3", 7188 "xmm4", "xmm5", "xmm6", "xmm7", 7189 "mm0", "mm1", "mm2", "mm3", 7190 "mm4", "mm5", "mm6", "mm7", 7191 "fcw", "fsw", "mxcsr", 7192 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, 7193 "tr", "ldtr" 7194 }; 7195 static const char *const regnames_64[] = 7196 { 7197 "rax", "rdx", "rcx", "rbx", 7198 "rsi", "rdi", "rbp", "rsp", 7199 "r8", "r9", "r10", "r11", 7200 "r12", "r13", "r14", "r15", 7201 "rip", 7202 "xmm0", "xmm1", "xmm2", "xmm3", 7203 "xmm4", "xmm5", "xmm6", "xmm7", 7204 "xmm8", "xmm9", "xmm10", "xmm11", 7205 "xmm12", "xmm13", "xmm14", "xmm15", 7206 "st0", "st1", "st2", "st3", 7207 "st4", "st5", "st6", "st7", 7208 "mm0", "mm1", "mm2", "mm3", 7209 "mm4", "mm5", "mm6", "mm7", 7210 "rflags", 7211 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, 7212 "fs.base", "gs.base", NULL, NULL, 7213 "tr", "ldtr", 7214 "mxcsr", "fcw", "fsw" 7215 }; 7216 const char *const *regnames; 7217 7218 if (flag_code == CODE_64BIT) 7219 { 7220 regnames = regnames_64; 7221 regnames_count = ARRAY_SIZE (regnames_64); 7222 } 7223 else 7224 { 7225 regnames = regnames_32; 7226 regnames_count = ARRAY_SIZE (regnames_32); 7227 } 7228 7229 for (regnum = 0; regnum < regnames_count; regnum++) 7230 if (regnames[regnum] != NULL 7231 && strcmp (regname, regnames[regnum]) == 0) 7232 return regnum; 7233 7234 return -1; 7235} 7236 7237void 7238tc_x86_frame_initial_instructions (void) 7239{ 7240 static unsigned int sp_regno; 7241 7242 if (!sp_regno) 7243 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT 7244 ? "rsp" : "esp"); 7245 7246 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment); 7247 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); 7248} 7249 7250int 7251i386_elf_section_type (const char *str, size_t len) 7252{ 7253 if (flag_code == CODE_64BIT 7254 && len == sizeof ("unwind") - 1 7255 && strncmp (str, "unwind", 6) == 0) 7256 return SHT_X86_64_UNWIND; 7257 7258 return -1; 7259} 7260 7261#ifdef TE_PE 7262void 7263tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) 7264{ 7265 expressionS expr; 7266 7267 expr.X_op = O_secrel; 7268 expr.X_add_symbol = symbol; 7269 expr.X_add_number = 0; 7270 emit_expr (&expr, size); 7271} 7272#endif 7273 7274#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 7275/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ 7276 7277int 7278x86_64_section_letter (int letter, char **ptr_msg) 7279{ 7280 if (flag_code == CODE_64BIT) 7281 { 7282 if (letter == 'l') 7283 return SHF_X86_64_LARGE; 7284 7285 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string"); 7286 } 7287 else 7288 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string"); 7289 return -1; 7290} 7291 7292int 7293x86_64_section_word (char *str, size_t len) 7294{ 7295 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0) 7296 return SHF_X86_64_LARGE; 7297 7298 return -1; 7299} 7300 7301static void 7302handle_large_common (int small ATTRIBUTE_UNUSED) 7303{ 7304 if (flag_code != CODE_64BIT) 7305 { 7306 s_comm_internal (0, elf_common_parse); 7307 as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); 7308 } 7309 else 7310 { 7311 static segT lbss_section; 7312 asection *saved_com_section_ptr = elf_com_section_ptr; 7313 asection *saved_bss_section = bss_section; 7314 7315 if (lbss_section == NULL) 7316 { 7317 flagword applicable; 7318 segT seg = now_seg; 7319 subsegT subseg = now_subseg; 7320 7321 /* The .lbss section is for local .largecomm symbols. */ 7322 lbss_section = subseg_new (".lbss", 0); 7323 applicable = bfd_applicable_section_flags (stdoutput); 7324 bfd_set_section_flags (stdoutput, lbss_section, 7325 applicable & SEC_ALLOC); 7326 seg_info (lbss_section)->bss = 1; 7327 7328 subseg_set (seg, subseg); 7329 } 7330 7331 elf_com_section_ptr = &_bfd_elf_large_com_section; 7332 bss_section = lbss_section; 7333 7334 s_comm_internal (0, elf_common_parse); 7335 7336 elf_com_section_ptr = saved_com_section_ptr; 7337 bss_section = saved_bss_section; 7338 } 7339} 7340#endif /* OBJ_ELF || OBJ_MAYBE_ELF */ 7341