1/* tc-cris.c -- Assembler code for the CRIS CPU core. 2 Copyright 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 3 4 Contributed by Axis Communications AB, Lund, Sweden. 5 Originally written for GAS 1.38.1 by Mikael Asker. 6 Updates, BFDizing, GNUifying and ELF support by Hans-Peter Nilsson. 7 8 This file is part of GAS, the GNU Assembler. 9 10 GAS is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2, or (at your option) 13 any later version. 14 15 GAS is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GAS; see the file COPYING. If not, write to the 22 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 23 MA 02110-1301, USA. */ 24 25#include <stdio.h> 26#include "as.h" 27#include "safe-ctype.h" 28#include "subsegs.h" 29#include "opcode/cris.h" 30#include "dwarf2dbg.h" 31 32/* Conventions used here: 33 Generally speaking, pointers to binutils types such as "fragS" and 34 "expressionS" get parameter and variable names ending in "P", such as 35 "fragP", to harmonize with the rest of the binutils code. Other 36 pointers get a "p" suffix, such as "bufp". Any function or type-name 37 that could clash with a current or future binutils or GAS function get 38 a "cris_" prefix. */ 39 40#define SYNTAX_RELAX_REG_PREFIX "no_register_prefix" 41#define SYNTAX_ENFORCE_REG_PREFIX "register_prefix" 42#define SYNTAX_USER_SYM_LEADING_UNDERSCORE "leading_underscore" 43#define SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE "no_leading_underscore" 44#define REGISTER_PREFIX_CHAR '$' 45 46/* True for expressions where getting X_add_symbol and X_add_number is 47 enough to get the "base" and "offset"; no need to make_expr_symbol. 48 It's not enough to check if X_op_symbol is NULL; that misses unary 49 operations like O_uminus. */ 50#define SIMPLE_EXPR(EXP) \ 51 ((EXP)->X_op == O_constant || (EXP)->X_op == O_symbol) 52 53/* Like in ":GOT", ":GOTOFF" etc. Other ports use '@', but that's in 54 line_separator_chars for CRIS, so we avoid it. */ 55#define PIC_SUFFIX_CHAR ':' 56 57/* This might be CRIS_INSN_NONE if we're assembling a prefix-insn only. 58 Note that some prefix-insns might be assembled as CRIS_INSN_NORMAL. */ 59enum cris_insn_kind 60{ 61 CRIS_INSN_NORMAL, CRIS_INSN_NONE, CRIS_INSN_BRANCH, CRIS_INSN_MUL 62}; 63 64/* An instruction will have one of these prefixes. 65 Although the same bit-pattern, we handle BDAP with an immediate 66 expression (eventually quick or [pc+]) different from when we only have 67 register expressions. */ 68enum prefix_kind 69{ 70 PREFIX_NONE, PREFIX_BDAP_IMM, PREFIX_BDAP, PREFIX_BIAP, PREFIX_DIP, 71 PREFIX_PUSH 72}; 73 74/* The prefix for an instruction. */ 75struct cris_prefix 76{ 77 enum prefix_kind kind; 78 int base_reg_number; 79 unsigned int opcode; 80 81 /* There might be an expression to be evaluated, like I in [rN+I]. */ 82 expressionS expr; 83 84 /* If there's an expression, we might need a relocation. Here's the 85 type of what relocation to start relaxaton with. 86 The relocation is assumed to start immediately after the prefix insn, 87 so we don't provide an offset. */ 88 enum bfd_reloc_code_real reloc; 89}; 90 91/* The description of the instruction being assembled. */ 92struct cris_instruction 93{ 94 /* If CRIS_INSN_NONE, then this insn is of zero length. */ 95 enum cris_insn_kind insn_type; 96 97 /* If a special register was mentioned, this is its description, else 98 it is NULL. */ 99 const struct cris_spec_reg *spec_reg; 100 101 unsigned int opcode; 102 103 /* An insn may have at most one expression; theoretically there could be 104 another in its prefix (but I don't see how that could happen). */ 105 expressionS expr; 106 107 /* The expression might need a relocation. Here's one to start 108 relaxation with. */ 109 enum bfd_reloc_code_real reloc; 110 111 /* The size in bytes of an immediate expression, or zero if 112 nonapplicable. */ 113 int imm_oprnd_size; 114}; 115 116enum cris_archs 117{ 118 arch_cris_unknown, 119 arch_crisv0, arch_crisv3, arch_crisv8, arch_crisv10, 120 arch_cris_any_v0_v10, arch_crisv32, arch_cris_common_v10_v32 121}; 122 123static enum cris_archs cris_arch_from_string (char **); 124static int cris_insn_ver_valid_for_arch (enum cris_insn_version_usage, 125 enum cris_archs); 126 127static void cris_process_instruction (char *, struct cris_instruction *, 128 struct cris_prefix *); 129static int get_bwd_size_modifier (char **, int *); 130static int get_bw_size_modifier (char **, int *); 131static int get_gen_reg (char **, int *); 132static int get_spec_reg (char **, const struct cris_spec_reg **); 133static int get_sup_reg (char **, int *); 134static int get_autoinc_prefix_or_indir_op (char **, struct cris_prefix *, 135 int *, int *, int *, 136 expressionS *); 137static int get_3op_or_dip_prefix_op (char **, struct cris_prefix *); 138static int cris_get_expression (char **, expressionS *); 139static int get_flags (char **, int *); 140static void gen_bdap (int, expressionS *); 141static int branch_disp (int); 142static void gen_cond_branch_32 (char *, char *, fragS *, symbolS *, symbolS *, 143 long int); 144static void cris_number_to_imm (char *, long, int, fixS *, segT); 145static void cris_create_short_jump (char *, addressT, addressT, fragS *, 146 symbolS *); 147static void s_syntax (int); 148static void s_cris_file (int); 149static void s_cris_loc (int); 150static void s_cris_arch (int); 151 152/* Get ":GOT", ":GOTOFF", ":PLT" etc. suffixes. */ 153static void cris_get_pic_suffix (char **, bfd_reloc_code_real_type *, 154 expressionS *); 155static unsigned int cris_get_pic_reloc_size (bfd_reloc_code_real_type); 156 157/* All the .syntax functions. */ 158static void cris_force_reg_prefix (void); 159static void cris_relax_reg_prefix (void); 160static void cris_sym_leading_underscore (void); 161static void cris_sym_no_leading_underscore (void); 162static char *cris_insn_first_word_frag (void); 163 164/* Handle to the opcode hash table. */ 165static struct hash_control *op_hash = NULL; 166 167/* If we target cris-axis-linux-gnu (as opposed to generic cris-axis-elf), 168 we default to no underscore and required register-prefixes. The 169 difference is in the default values. */ 170#ifdef TE_LINUX 171#define DEFAULT_CRIS_AXIS_LINUX_GNU TRUE 172#else 173#define DEFAULT_CRIS_AXIS_LINUX_GNU FALSE 174#endif 175 176/* Whether we demand that registers have a `$' prefix. Default here. */ 177static bfd_boolean demand_register_prefix = DEFAULT_CRIS_AXIS_LINUX_GNU; 178 179/* Whether global user symbols have a leading underscore. Default here. */ 180static bfd_boolean symbols_have_leading_underscore 181 = !DEFAULT_CRIS_AXIS_LINUX_GNU; 182 183/* Whether or not we allow PIC, and expand to PIC-friendly constructs. */ 184static bfd_boolean pic = FALSE; 185 186/* If we're configured for "cris", default to allow all v0..v10 187 instructions and register names. */ 188#ifndef DEFAULT_CRIS_ARCH 189#define DEFAULT_CRIS_ARCH cris_any_v0_v10 190#endif 191 192/* No whitespace in the CONCAT2 parameter list. */ 193static enum cris_archs cris_arch = XCONCAT2 (arch_,DEFAULT_CRIS_ARCH); 194 195const pseudo_typeS md_pseudo_table[] = 196{ 197 {"dword", cons, 4}, 198 {"syntax", s_syntax, 0}, 199 {"file", s_cris_file, 0}, 200 {"loc", s_cris_loc, 0}, 201 {"arch", s_cris_arch, 0}, 202 {NULL, 0, 0} 203}; 204 205static int warn_for_branch_expansion = 0; 206 207/* Whether to emit error when a MULS/MULU could be located last on a 208 cache-line. */ 209static int err_for_dangerous_mul_placement 210 = (XCONCAT2 (arch_,DEFAULT_CRIS_ARCH) != arch_crisv32); 211 212const char cris_comment_chars[] = ";"; 213 214/* This array holds the chars that only start a comment at the beginning of 215 a line. If the line seems to have the form '# 123 filename' 216 .line and .file directives will appear in the pre-processed output. */ 217/* Note that input_file.c hand-checks for '#' at the beginning of the 218 first line of the input file. This is because the compiler outputs 219 #NO_APP at the beginning of its output. */ 220/* Also note that slash-star will always start a comment. */ 221const char line_comment_chars[] = "#"; 222const char line_separator_chars[] = "@"; 223 224/* Now all floating point support is shut off. See md_atof. */ 225const char EXP_CHARS[] = ""; 226const char FLT_CHARS[] = ""; 227 228/* For CRIS, we encode the relax_substateTs (in e.g. fr_substate) as: 229 2 1 0 230 ---/ /--+-----------------+-----------------+-----------------+ 231 | what state ? | how long ? | 232 ---/ /--+-----------------+-----------------+-----------------+ 233 234 The "how long" bits are 00 = byte, 01 = word, 10 = dword (long). 235 Not all lengths are legit for a given value of (what state). 236 237 Groups for CRIS address relaxing: 238 239 1. Bcc (pre-V32) 240 length: byte, word, 10-byte expansion 241 242 2. BDAP 243 length: byte, word, dword 244 245 3. MULS/MULU 246 Not really a relaxation (no infrastructure to get delay-slots 247 right), just an alignment and placement checker for the v10 248 multiply/cache-bug. 249 250 4. Bcc (V32 and later) 251 length: byte, word, 14-byte expansion 252 253 5. Bcc (V10+V32) 254 length: byte, word, error 255 256 6. BA (V32) 257 length: byte, word, dword 258 259 7. LAPC (V32) 260 length: byte, dword 261 */ 262 263#define STATE_COND_BRANCH (1) 264#define STATE_BASE_PLUS_DISP_PREFIX (2) 265#define STATE_MUL (3) 266#define STATE_COND_BRANCH_V32 (4) 267#define STATE_COND_BRANCH_COMMON (5) 268#define STATE_ABS_BRANCH_V32 (6) 269#define STATE_LAPC (7) 270#define STATE_COND_BRANCH_PIC (8) 271 272#define STATE_LENGTH_MASK (3) 273#define STATE_BYTE (0) 274#define STATE_WORD (1) 275#define STATE_DWORD (2) 276/* Symbol undefined. */ 277#define STATE_UNDF (3) 278#define STATE_MAX_LENGTH (3) 279 280/* These displacements are relative to the address following the opcode 281 word of the instruction. The first letter is Byte, Word. The 2nd 282 letter is Forward, Backward. */ 283 284#define BRANCH_BF ( 254) 285#define BRANCH_BB (-256) 286#define BRANCH_BF_V32 ( 252) 287#define BRANCH_BB_V32 (-258) 288#define BRANCH_WF (2 + 32767) 289#define BRANCH_WB (2 + -32768) 290#define BRANCH_WF_V32 (-2 + 32767) 291#define BRANCH_WB_V32 (-2 + -32768) 292 293#define BDAP_BF ( 127) 294#define BDAP_BB (-128) 295#define BDAP_WF ( 32767) 296#define BDAP_WB (-32768) 297 298#define ENCODE_RELAX(what, length) (((what) << 2) + (length)) 299 300const relax_typeS md_cris_relax_table[] = 301{ 302 /* Error sentinel (0, 0). */ 303 {1, 1, 0, 0}, 304 305 /* Unused (0, 1). */ 306 {1, 1, 0, 0}, 307 308 /* Unused (0, 2). */ 309 {1, 1, 0, 0}, 310 311 /* Unused (0, 3). */ 312 {1, 1, 0, 0}, 313 314 /* Bcc o (1, 0). */ 315 {BRANCH_BF, BRANCH_BB, 0, ENCODE_RELAX (1, 1)}, 316 317 /* Bcc [PC+] (1, 1). */ 318 {BRANCH_WF, BRANCH_WB, 2, ENCODE_RELAX (1, 2)}, 319 320 /* BEXT/BWF, BA, JUMP (external), JUMP (always), Bnot_cc, JUMP (default) 321 (1, 2). */ 322 {0, 0, 10, 0}, 323 324 /* Unused (1, 3). */ 325 {1, 1, 0, 0}, 326 327 /* BDAP o (2, 0). */ 328 {BDAP_BF, BDAP_BB, 0, ENCODE_RELAX (2, 1)}, 329 330 /* BDAP.[bw] [PC+] (2, 1). */ 331 {BDAP_WF, BDAP_WB, 2, ENCODE_RELAX (2, 2)}, 332 333 /* BDAP.d [PC+] (2, 2). */ 334 {0, 0, 4, 0}, 335 336 /* Unused (2, 3). */ 337 {1, 1, 0, 0}, 338 339 /* MULS/MULU (3, 0). Positions (3, 1..3) are unused. */ 340 {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, 341 342 /* V32: Bcc o (4, 0). */ 343 {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (4, 1)}, 344 345 /* V32: Bcc [PC+] (4, 1). */ 346 {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (4, 2)}, 347 348 /* V32: BA .+12; NOP; BA32 target; NOP; Bcc .-6 (4, 2). */ 349 {0, 0, 12, 0}, 350 351 /* Unused (4, 3). */ 352 {1, 1, 0, 0}, 353 354 /* COMMON: Bcc o (5, 0). The offsets are calculated as for v32. Code 355 should contain two nop insns (or four if offset size is large or 356 unknown) after every label. */ 357 {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (5, 1)}, 358 359 /* COMMON: Bcc [PC+] (5, 1). */ 360 {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (5, 2)}, 361 362 /* COMMON: FIXME: ???. Treat as error currently. */ 363 {0, 0, 12, 0}, 364 365 /* Unused (5, 3). */ 366 {1, 1, 0, 0}, 367 368 /* V32: BA o (6, 0). */ 369 {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (6, 1)}, 370 371 /* V32: BA.W (6, 1). */ 372 {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (6, 2)}, 373 374 /* V32: BA.D (6, 2). */ 375 {0, 0, 4, 0}, 376 377 /* Unused (6, 3). */ 378 {1, 1, 0, 0}, 379 380 /* LAPC: LAPCQ .+0..15*2,Rn (7, 0). */ 381 {14*2, -1*2, 0, ENCODE_RELAX (7, 2)}, 382 383 /* Unused (7, 1). 384 While there's a shorter sequence, e.g. LAPCQ + an ADDQ or SUBQ, 385 that would affect flags, so we can't do that as it wouldn't be a 386 proper insn expansion of LAPCQ. This row is associated with a 387 2-byte expansion, so it's unused rather than the next. */ 388 {1, 1, 0, 0}, 389 390 /* LAPC: LAPC.D (7, 2). */ 391 {0, 0, 4, 0}, 392 393 /* Unused (7, 3). */ 394 {1, 1, 0, 0}, 395 396 /* PIC for pre-v32: Bcc o (8, 0). */ 397 {BRANCH_BF, BRANCH_BB, 0, ENCODE_RELAX (STATE_COND_BRANCH_PIC, 1)}, 398 399 /* Bcc [PC+] (8, 1). */ 400 {BRANCH_WF, BRANCH_WB, 2, ENCODE_RELAX (STATE_COND_BRANCH_PIC, 2)}, 401 402 /* 32-bit expansion, PIC (8, 2). */ 403 {0, 0, 12, 0}, 404 405 /* Unused (8, 3). */ 406 {1, 1, 0, 0} 407}; 408 409#undef BDAP_BF 410#undef BDAP_BB 411#undef BDAP_WF 412#undef BDAP_WB 413 414/* Target-specific multicharacter options, not const-declared. */ 415struct option md_longopts[] = 416{ 417#define OPTION_NO_US (OPTION_MD_BASE + 0) 418 {"no-underscore", no_argument, NULL, OPTION_NO_US}, 419#define OPTION_US (OPTION_MD_BASE + 1) 420 {"underscore", no_argument, NULL, OPTION_US}, 421#define OPTION_PIC (OPTION_US + 1) 422 {"pic", no_argument, NULL, OPTION_PIC}, 423#define OPTION_MULBUG_ABORT_ON (OPTION_PIC + 1) 424 {"mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_ON}, 425#define OPTION_MULBUG_ABORT_OFF (OPTION_MULBUG_ABORT_ON + 1) 426 {"no-mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_OFF}, 427#define OPTION_ARCH (OPTION_MULBUG_ABORT_OFF + 1) 428 {"march", required_argument, NULL, OPTION_ARCH}, 429 {NULL, no_argument, NULL, 0} 430}; 431 432/* Not const-declared. */ 433size_t md_longopts_size = sizeof (md_longopts); 434const char *md_shortopts = "hHN"; 435 436/* At first glance, this may seems wrong and should be 4 (ba + nop); but 437 since a short_jump must skip a *number* of long jumps, it must also be 438 a long jump. Here, we hope to make it a "ba [16bit_offs]" and a "nop" 439 for the delay slot and hope that the jump table at most needs 440 32767/4=8191 long-jumps. A branch is better than a jump, since it is 441 relative; we will not have a reloc to fix up somewhere. 442 443 Note that we can't add relocs, because relaxation uses these fixed 444 numbers, and md_create_short_jump is called after relaxation. */ 445 446int md_short_jump_size = 6; 447 448/* The v32 version has a delay-slot, hence two bytes longer. 449 The pre-v32 PIC version uses a prefixed insn. */ 450#define cris_any_v0_v10_long_jump_size 6 451#define cris_any_v0_v10_long_jump_size_pic 8 452#define crisv32_long_jump_size 8 453 454int md_long_jump_size = XCONCAT2 (DEFAULT_CRIS_ARCH,_long_jump_size); 455 456/* Report output format. Small changes in output format (like elf 457 variants below) can happen until all options are parsed, but after 458 that, the output format must remain fixed. */ 459 460const char * 461cris_target_format (void) 462{ 463 switch (OUTPUT_FLAVOR) 464 { 465 case bfd_target_aout_flavour: 466 return "a.out-cris"; 467 468 case bfd_target_elf_flavour: 469 if (symbols_have_leading_underscore) 470 return "elf32-us-cris"; 471 return "elf32-cris"; 472 473 default: 474 abort (); 475 return NULL; 476 } 477} 478 479/* Return a bfd_mach_cris... value corresponding to the value of 480 cris_arch. */ 481 482unsigned int 483cris_mach (void) 484{ 485 unsigned int retval = 0; 486 487 switch (cris_arch) 488 { 489 case arch_cris_common_v10_v32: 490 retval = bfd_mach_cris_v10_v32; 491 break; 492 493 case arch_crisv32: 494 retval = bfd_mach_cris_v32; 495 break; 496 497 case arch_crisv10: 498 case arch_cris_any_v0_v10: 499 retval = bfd_mach_cris_v0_v10; 500 break; 501 502 default: 503 BAD_CASE (cris_arch); 504 } 505 506 return retval; 507} 508 509/* We need a port-specific relaxation function to cope with sym2 - sym1 510 relative expressions with both symbols in the same segment (but not 511 necessarily in the same frag as this insn), for example: 512 move.d [pc+sym2-(sym1-2)],r10 513 sym1: 514 The offset can be 8, 16 or 32 bits long. */ 515 516long 517cris_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS *fragP, 518 long stretch ATTRIBUTE_UNUSED) 519{ 520 long growth; 521 offsetT aim = 0; 522 symbolS *symbolP; 523 const relax_typeS *this_type; 524 const relax_typeS *start_type; 525 relax_substateT next_state; 526 relax_substateT this_state; 527 const relax_typeS *table = TC_GENERIC_RELAX_TABLE; 528 529 /* We only have to cope with frags as prepared by 530 md_estimate_size_before_relax. The dword cases may get here 531 because of the different reasons that they aren't relaxable. */ 532 switch (fragP->fr_subtype) 533 { 534 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): 535 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): 536 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): 537 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): 538 case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): 539 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): 540 /* When we get to these states, the frag won't grow any more. */ 541 return 0; 542 543 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): 544 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): 545 if (fragP->fr_symbol == NULL 546 || S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) 547 as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"), 548 __FUNCTION__, (long) fragP->fr_symbol); 549 symbolP = fragP->fr_symbol; 550 if (symbol_resolved_p (symbolP)) 551 as_fatal (_("internal inconsistency problem in %s: resolved symbol"), 552 __FUNCTION__); 553 aim = S_GET_VALUE (symbolP); 554 break; 555 556 case ENCODE_RELAX (STATE_MUL, STATE_BYTE): 557 /* Nothing to do here. */ 558 return 0; 559 560 default: 561 as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"), 562 __FUNCTION__, fragP->fr_subtype); 563 } 564 565 /* The rest is stolen from relax_frag. There's no obvious way to 566 share the code, but fortunately no requirement to keep in sync as 567 long as fragP->fr_symbol does not have its segment changed. */ 568 569 this_state = fragP->fr_subtype; 570 start_type = this_type = table + this_state; 571 572 if (aim < 0) 573 { 574 /* Look backwards. */ 575 for (next_state = this_type->rlx_more; next_state;) 576 if (aim >= this_type->rlx_backward) 577 next_state = 0; 578 else 579 { 580 /* Grow to next state. */ 581 this_state = next_state; 582 this_type = table + this_state; 583 next_state = this_type->rlx_more; 584 } 585 } 586 else 587 { 588 /* Look forwards. */ 589 for (next_state = this_type->rlx_more; next_state;) 590 if (aim <= this_type->rlx_forward) 591 next_state = 0; 592 else 593 { 594 /* Grow to next state. */ 595 this_state = next_state; 596 this_type = table + this_state; 597 next_state = this_type->rlx_more; 598 } 599 } 600 601 growth = this_type->rlx_length - start_type->rlx_length; 602 if (growth != 0) 603 fragP->fr_subtype = this_state; 604 return growth; 605} 606 607/* Prepare machine-dependent frags for relaxation. 608 609 Called just before relaxation starts. Any symbol that is now undefined 610 will not become defined. 611 612 Return the correct fr_subtype in the frag. 613 614 Return the initial "guess for fr_var" to caller. The guess for fr_var 615 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix 616 or fr_var contributes to our returned value. 617 618 Although it may not be explicit in the frag, pretend 619 fr_var starts with a value. */ 620 621int 622md_estimate_size_before_relax (fragS *fragP, segT segment_type) 623{ 624 int old_fr_fix; 625 symbolS *symbolP = fragP->fr_symbol; 626 627#define HANDLE_RELAXABLE(state) \ 628 case ENCODE_RELAX (state, STATE_UNDF): \ 629 if (symbolP != NULL \ 630 && S_GET_SEGMENT (symbolP) == segment_type \ 631 && !S_IS_WEAK (symbolP)) \ 632 /* The symbol lies in the same segment - a relaxable \ 633 case. */ \ 634 fragP->fr_subtype \ 635 = ENCODE_RELAX (state, STATE_BYTE); \ 636 else \ 637 /* Unknown or not the same segment, so not relaxable. */ \ 638 fragP->fr_subtype \ 639 = ENCODE_RELAX (state, STATE_DWORD); \ 640 fragP->fr_var \ 641 = md_cris_relax_table[fragP->fr_subtype].rlx_length; \ 642 break 643 644 old_fr_fix = fragP->fr_fix; 645 646 switch (fragP->fr_subtype) 647 { 648 HANDLE_RELAXABLE (STATE_COND_BRANCH); 649 HANDLE_RELAXABLE (STATE_COND_BRANCH_V32); 650 HANDLE_RELAXABLE (STATE_COND_BRANCH_COMMON); 651 HANDLE_RELAXABLE (STATE_COND_BRANCH_PIC); 652 HANDLE_RELAXABLE (STATE_ABS_BRANCH_V32); 653 654 case ENCODE_RELAX (STATE_LAPC, STATE_UNDF): 655 if (symbolP != NULL 656 && S_GET_SEGMENT (symbolP) == segment_type 657 && !S_IS_WEAK (symbolP)) 658 { 659 /* The symbol lies in the same segment - a relaxable case. 660 Check if we currently have an odd offset; we can't code 661 that into the instruction. Relaxing presumably only cause 662 multiple-of-two changes, so we should only need to adjust 663 for that here. */ 664 bfd_vma target_address 665 = (symbolP 666 ? S_GET_VALUE (symbolP) 667 : 0) + fragP->fr_offset; 668 bfd_vma var_part_offset = fragP->fr_fix; 669 bfd_vma address_of_var_part = fragP->fr_address + var_part_offset; 670 long offset = target_address - (address_of_var_part - 2); 671 672 fragP->fr_subtype 673 = (offset & 1) 674 ? ENCODE_RELAX (STATE_LAPC, STATE_DWORD) 675 : ENCODE_RELAX (STATE_LAPC, STATE_BYTE); 676 } 677 else 678 /* Unknown or not the same segment, so not relaxable. */ 679 fragP->fr_subtype 680 = ENCODE_RELAX (STATE_LAPC, STATE_DWORD); 681 fragP->fr_var 682 = md_cris_relax_table[fragP->fr_subtype].rlx_length; 683 break; 684 685 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF): 686 /* Note that we can not do anything sane with relaxing 687 [rX + a_known_symbol_in_text], it will have to be a 32-bit 688 value. 689 690 We could play tricks with managing a constant pool and make 691 a_known_symbol_in_text a "bdap [pc + offset]" pointing there 692 (like the GOT for ELF shared libraries), but that's no use, it 693 would in general be no shorter or faster code, only more 694 complicated. */ 695 696 if (S_GET_SEGMENT (symbolP) != absolute_section) 697 { 698 /* Go for dword if not absolute or same segment. */ 699 fragP->fr_subtype 700 = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD); 701 fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; 702 } 703 else if (!symbol_resolved_p (fragP->fr_symbol)) 704 { 705 /* The symbol will eventually be completely resolved as an 706 absolute expression, but right now it depends on the result 707 of relaxation and we don't know anything else about the 708 value. We start relaxation with the assumption that it'll 709 fit in a byte. */ 710 fragP->fr_subtype 711 = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE); 712 fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; 713 } 714 else 715 { 716 /* Absolute expression. */ 717 long int value; 718 value = (symbolP != NULL 719 ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset; 720 721 if (value >= -128 && value <= 127) 722 { 723 /* Byte displacement. */ 724 (fragP->fr_opcode)[0] = value; 725 } 726 else 727 { 728 /* Word or dword displacement. */ 729 int pow2_of_size = 1; 730 char *writep; 731 732 if (value < -32768 || value > 32767) 733 { 734 /* Outside word range, make it a dword. */ 735 pow2_of_size = 2; 736 } 737 738 /* Modify the byte-offset BDAP into a word or dword offset 739 BDAP. Or really, a BDAP rX,8bit into a 740 BDAP.[wd] rX,[PC+] followed by a word or dword. */ 741 (fragP->fr_opcode)[0] = BDAP_PC_LOW + pow2_of_size * 16; 742 743 /* Keep the register number in the highest four bits. */ 744 (fragP->fr_opcode)[1] &= 0xF0; 745 (fragP->fr_opcode)[1] |= BDAP_INCR_HIGH; 746 747 /* It grew by two or four bytes. */ 748 fragP->fr_fix += 1 << pow2_of_size; 749 writep = fragP->fr_literal + old_fr_fix; 750 md_number_to_chars (writep, value, 1 << pow2_of_size); 751 } 752 frag_wane (fragP); 753 } 754 break; 755 756 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE): 757 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD): 758 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): 759 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_BYTE): 760 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_WORD): 761 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD): 762 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE): 763 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD): 764 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): 765 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE): 766 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD): 767 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): 768 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE): 769 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD): 770 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): 771 case ENCODE_RELAX (STATE_LAPC, STATE_BYTE): 772 case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): 773 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): 774 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): 775 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): 776 /* When relaxing a section for the second time, we don't need to 777 do anything except making sure that fr_var is set right. */ 778 fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; 779 break; 780 781 case ENCODE_RELAX (STATE_MUL, STATE_BYTE): 782 /* Nothing to do here. */ 783 break; 784 785 default: 786 BAD_CASE (fragP->fr_subtype); 787 } 788 789 return fragP->fr_var + (fragP->fr_fix - old_fr_fix); 790} 791 792/* Perform post-processing of machine-dependent frags after relaxation. 793 Called after relaxation is finished. 794 In: Address of frag. 795 fr_type == rs_machine_dependent. 796 fr_subtype is what the address relaxed to. 797 798 Out: Any fixS:s and constants are set up. 799 800 The caller will turn the frag into a ".space 0". */ 801 802void 803md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, 804 fragS *fragP) 805{ 806 /* Pointer to first byte in variable-sized part of the frag. */ 807 char *var_partp; 808 809 /* Pointer to first opcode byte in frag. */ 810 char *opcodep; 811 812 /* Used to check integrity of the relaxation. 813 One of 2 = long, 1 = word, or 0 = byte. */ 814 int length_code; 815 816 /* Size in bytes of variable-sized part of frag. */ 817 int var_part_size = 0; 818 819 /* This is part of *fragP. It contains all information about addresses 820 and offsets to varying parts. */ 821 symbolS *symbolP; 822 unsigned long var_part_offset; 823 824 /* Where, in file space, is _var of *fragP? */ 825 unsigned long address_of_var_part = 0; 826 827 /* Where, in file space, does addr point? */ 828 unsigned long target_address; 829 830 know (fragP->fr_type == rs_machine_dependent); 831 832 length_code = fragP->fr_subtype & STATE_LENGTH_MASK; 833 know (length_code >= 0 && length_code < STATE_MAX_LENGTH); 834 835 var_part_offset = fragP->fr_fix; 836 var_partp = fragP->fr_literal + var_part_offset; 837 opcodep = fragP->fr_opcode; 838 839 symbolP = fragP->fr_symbol; 840 target_address = (symbolP ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset; 841 address_of_var_part = fragP->fr_address + var_part_offset; 842 843 switch (fragP->fr_subtype) 844 { 845 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE): 846 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_BYTE): 847 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE): 848 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE): 849 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE): 850 opcodep[0] = branch_disp ((target_address - address_of_var_part)); 851 var_part_size = 0; 852 break; 853 854 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD): 855 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_WORD): 856 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD): 857 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD): 858 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD): 859 /* We had a quick immediate branch, now turn it into a word one i.e. a 860 PC autoincrement. */ 861 opcodep[0] = BRANCH_PC_LOW; 862 opcodep[1] &= 0xF0; 863 opcodep[1] |= BRANCH_INCR_HIGH; 864 md_number_to_chars (var_partp, 865 (long) 866 (target_address 867 - (address_of_var_part 868 + (cris_arch == arch_crisv32 869 || cris_arch == arch_cris_common_v10_v32 870 ? -2 : 2))), 871 2); 872 var_part_size = 2; 873 break; 874 875 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): 876 gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, 877 fragP->fr_symbol, (symbolS *) NULL, 878 fragP->fr_offset); 879 /* Ten bytes added: a branch, nop and a jump. */ 880 var_part_size = 2 + 2 + 4 + 2; 881 break; 882 883 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD): 884 gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, 885 fragP->fr_symbol, (symbolS *) NULL, 886 fragP->fr_offset); 887 /* Twelve bytes added: a branch, nop and a pic-branch-32. */ 888 var_part_size = 2 + 2 + 4 + 2 + 2; 889 break; 890 891 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): 892 gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, 893 fragP->fr_symbol, (symbolS *) NULL, 894 fragP->fr_offset); 895 /* Twelve bytes added: a branch, nop and another branch and nop. */ 896 var_part_size = 2 + 2 + 2 + 4 + 2; 897 break; 898 899 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): 900 as_bad_where (fragP->fr_file, fragP->fr_line, 901 _("Relaxation to long branches for .arch common_v10_v32\ 902 not implemented")); 903 /* Pretend we have twelve bytes for sake of quelling further 904 errors. */ 905 var_part_size = 2 + 2 + 2 + 4 + 2; 906 break; 907 908 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): 909 /* We had a quick immediate branch or a word immediate ba. Now 910 turn it into a dword one. */ 911 opcodep[0] = BA_DWORD_OPCODE & 255; 912 opcodep[1] = (BA_DWORD_OPCODE >> 8) & 255; 913 fix_new (fragP, var_partp - fragP->fr_literal, 4, symbolP, 914 fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL); 915 var_part_size = 4; 916 break; 917 918 case ENCODE_RELAX (STATE_LAPC, STATE_BYTE): 919 { 920 long offset = target_address - (address_of_var_part - 2); 921 922 /* This is mostly a sanity check; useful occurrences (if there 923 really are any) should have been caught in 924 md_estimate_size_before_relax. We can (at least 925 theoretically) stumble over invalid code with odd sizes and 926 .p2aligns within the code, so emit an error if that happens. 927 (The generic relaxation machinery is not fit to check this.) */ 928 929 if (offset & 1) 930 as_bad_where (fragP->fr_file, fragP->fr_line, 931 _("Complicated LAPC target operand is not\ 932 a multiple of two. Use LAPC.D")); 933 934 /* FIXME: This *is* a sanity check. Remove when done with. */ 935 if (offset > 15*2 || offset < 0) 936 as_fatal (_("Internal error found in md_convert_frag: offset %ld.\ 937 Please report this."), 938 offset); 939 940 opcodep[0] |= (offset / 2) & 0xf; 941 var_part_size = 0; 942 } 943 break; 944 945 case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): 946 { 947 md_number_to_chars (opcodep, 948 LAPC_DWORD_OPCODE + (opcodep[1] & 0xf0) * 256, 949 2); 950 /* Remember that the reloc is against the position *after* the 951 relocated contents, so we need to adjust to the start of 952 the insn. */ 953 fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol, 954 fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL); 955 var_part_size = 4; 956 } 957 break; 958 959 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): 960 if (symbolP == NULL) 961 as_fatal (_("internal inconsistency in %s: bdapq no symbol"), 962 __FUNCTION__); 963 opcodep[0] = S_GET_VALUE (symbolP); 964 var_part_size = 0; 965 break; 966 967 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): 968 /* We had a BDAP 8-bit "quick immediate", now turn it into a 16-bit 969 one that uses PC autoincrement. */ 970 opcodep[0] = BDAP_PC_LOW + (1 << 4); 971 opcodep[1] &= 0xF0; 972 opcodep[1] |= BDAP_INCR_HIGH; 973 if (symbolP == NULL) 974 as_fatal (_("internal inconsistency in %s: bdap.w with no symbol"), 975 __FUNCTION__); 976 md_number_to_chars (var_partp, S_GET_VALUE (symbolP), 2); 977 var_part_size = 2; 978 break; 979 980 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): 981 /* We had a BDAP 16-bit "word", change the offset to a dword. */ 982 opcodep[0] = BDAP_PC_LOW + (2 << 4); 983 opcodep[1] &= 0xF0; 984 opcodep[1] |= BDAP_INCR_HIGH; 985 if (fragP->fr_symbol == NULL) 986 md_number_to_chars (var_partp, fragP->fr_offset, 4); 987 else 988 fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol, 989 fragP->fr_offset, 0, BFD_RELOC_32); 990 var_part_size = 4; 991 break; 992 993 case ENCODE_RELAX (STATE_MUL, STATE_BYTE): 994 /* This is the only time we check position and aligmnent of the 995 placement-tracking frag. */ 996 if (sec->alignment_power < 2) 997 as_bad_where (fragP->fr_file, fragP->fr_line, 998 _("section alignment must be >= 4 bytes to check MULS/MULU safeness")); 999 else 1000 { 1001 /* If the address after the MULS/MULU has alignment which is 1002 that of the section and may be that of a cache-size of the 1003 buggy versions, then the MULS/MULU can be placed badly. */ 1004 if ((address_of_var_part 1005 & ((1 << sec->alignment_power) - 1) & 31) == 0) 1006 as_bad_where (fragP->fr_file, fragP->fr_line, 1007 _("dangerous MULS/MULU location; give it higher alignment")); 1008 } 1009 break; 1010 1011 default: 1012 BAD_CASE (fragP->fr_subtype); 1013 break; 1014 } 1015 1016 fragP->fr_fix += var_part_size; 1017} 1018 1019/* Generate a short jump around a secondary jump table. 1020 Used by md_create_long_jump. 1021 1022 This used to be md_create_short_jump, but is now called from 1023 md_create_long_jump instead, when sufficient, since the sizes of the 1024 jumps are the same for pre-v32. */ 1025 1026static void 1027cris_create_short_jump (char *storep, addressT from_addr, addressT to_addr, 1028 fragS *fragP ATTRIBUTE_UNUSED, 1029 symbolS *to_symbol ATTRIBUTE_UNUSED) 1030{ 1031 long int distance; 1032 1033 /* See md_create_long_jump about the comment on the "+ 2". */ 1034 long int max_minimal_minus_distance; 1035 long int max_minimal_plus_distance; 1036 int nop_opcode; 1037 1038 if (cris_arch == arch_crisv32) 1039 { 1040 max_minimal_minus_distance = BRANCH_BB_V32 + 2; 1041 max_minimal_plus_distance = BRANCH_BF_V32 + 2; 1042 nop_opcode = NOP_OPCODE_V32; 1043 } 1044 else 1045 { 1046 max_minimal_minus_distance = BRANCH_BB + 2; 1047 max_minimal_plus_distance = BRANCH_BF + 2; 1048 nop_opcode = NOP_OPCODE; 1049 } 1050 1051 distance = to_addr - from_addr; 1052 1053 if (max_minimal_minus_distance <= distance 1054 && distance <= max_minimal_plus_distance) 1055 { 1056 /* Create a "short" short jump: "BA distance - 2". */ 1057 storep[0] = branch_disp (distance - 2); 1058 storep[1] = BA_QUICK_HIGH; 1059 1060 /* A nop for the delay slot. */ 1061 md_number_to_chars (storep + 2, nop_opcode, 2); 1062 1063 /* The extra word should be filled with something sane too. Make it 1064 a nop to keep disassembly sane. */ 1065 md_number_to_chars (storep + 4, nop_opcode, 2); 1066 } 1067 else 1068 { 1069 /* Make it a "long" short jump: "BA (PC+)". */ 1070 md_number_to_chars (storep, BA_PC_INCR_OPCODE, 2); 1071 1072 /* ".WORD distance - 4". */ 1073 md_number_to_chars (storep + 2, 1074 (long) (distance - 4 1075 - (cris_arch == arch_crisv32 1076 ? -4 : 0)), 1077 2); 1078 1079 /* A nop for the delay slot. */ 1080 md_number_to_chars (storep + 4, nop_opcode, 2); 1081 } 1082} 1083 1084/* Generate a long jump in a secondary jump table. 1085 1086 storep Where to store the jump instruction. 1087 from_addr Address of the jump instruction. 1088 to_addr Destination address of the jump. 1089 fragP Which frag the destination address operand 1090 lies in. 1091 to_symbol Destination symbol. */ 1092 1093void 1094md_create_long_jump (char *storep, addressT from_addr, addressT to_addr, 1095 fragS *fragP, symbolS *to_symbol) 1096{ 1097 long int distance; 1098 1099 /* FIXME: What's that "+ 3"? It comes from the magic numbers that 1100 used to be here, it's just translated to the limit macros used in 1101 the relax table. But why + 3? */ 1102 long int max_short_minus_distance 1103 = cris_arch != arch_crisv32 ? BRANCH_WB + 3 : BRANCH_WB_V32 + 3; 1104 1105 long int max_short_plus_distance 1106 = cris_arch != arch_crisv32 ? BRANCH_WF + 3 : BRANCH_WF_V32 + 3; 1107 1108 /* Bail out for compatibility mode. (It seems it can be implemented, 1109 perhaps with a 10-byte sequence: "move.d NNNN,$pc/$acr", "jump 1110 $acr", "nop"; but doesn't seem worth it at the moment.) */ 1111 if (cris_arch == arch_cris_common_v10_v32) 1112 as_fatal (_("Out-of-range .word offset handling\ 1113 is not implemented for .arch common_v10_v32")); 1114 1115 distance = to_addr - from_addr; 1116 1117 if (max_short_minus_distance <= distance 1118 && distance <= max_short_plus_distance) 1119 /* Then make it a "short" long jump. */ 1120 cris_create_short_jump (storep, from_addr, to_addr, fragP, 1121 to_symbol); 1122 else 1123 { 1124 /* We have a "long" long jump: "JUMP [PC+]". If CRISv32, always 1125 make it a BA. Else make it an "MOVE [PC=PC+N],P0" if we're supposed 1126 to emit PIC code. */ 1127 md_number_to_chars (storep, 1128 cris_arch == arch_crisv32 1129 ? BA_DWORD_OPCODE 1130 : (pic ? MOVE_PC_INCR_OPCODE_PREFIX 1131 : JUMP_PC_INCR_OPCODE), 1132 2); 1133 1134 /* Follow with a ".DWORD to_addr", PC-relative for PIC. */ 1135 fix_new (fragP, storep + 2 - fragP->fr_literal, 4, to_symbol, 1136 cris_arch == arch_crisv32 ? 6 : 0, 1137 cris_arch == arch_crisv32 || pic ? 1 : 0, 1138 cris_arch == arch_crisv32 || pic 1139 ? BFD_RELOC_32_PCREL : BFD_RELOC_32); 1140 1141 /* Follow it with a "NOP" for CRISv32. */ 1142 if (cris_arch == arch_crisv32) 1143 md_number_to_chars (storep + 6, NOP_OPCODE_V32, 2); 1144 else if (pic) 1145 /* ...and the rest of the move-opcode for pre-v32 PIC. */ 1146 md_number_to_chars (storep + 6, MOVE_PC_INCR_OPCODE_SUFFIX, 2); 1147 } 1148} 1149 1150/* Allocate space for the first piece of an insn, and mark it as the 1151 start of the insn for debug-format use. */ 1152 1153static char * 1154cris_insn_first_word_frag (void) 1155{ 1156 char *insnp = frag_more (2); 1157 1158 /* We need to mark the start of the insn by passing dwarf2_emit_insn 1159 the offset from the current fragment position. This must be done 1160 after the first fragment is created but before any other fragments 1161 (fixed or varying) are created. Note that the offset only 1162 corresponds to the "size" of the insn for a fixed-size, 1163 non-expanded insn. */ 1164 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 1165 dwarf2_emit_insn (2); 1166 1167 return insnp; 1168} 1169 1170/* Port-specific assembler initialization. */ 1171 1172void 1173md_begin (void) 1174{ 1175 const char *hashret = NULL; 1176 int i = 0; 1177 1178 /* Set up a hash table for the instructions. */ 1179 op_hash = hash_new (); 1180 if (op_hash == NULL) 1181 as_fatal (_("Virtual memory exhausted")); 1182 1183 /* Enable use of ".if ..asm.arch.cris.v32" 1184 and ".if ..asm.arch.cris.common_v10_v32" and a few others. */ 1185 symbol_table_insert (symbol_new ("..asm.arch.cris.v32", absolute_section, 1186 (cris_arch == arch_crisv32), 1187 &zero_address_frag)); 1188 symbol_table_insert (symbol_new ("..asm.arch.cris.v10", absolute_section, 1189 (cris_arch == arch_crisv10), 1190 &zero_address_frag)); 1191 symbol_table_insert (symbol_new ("..asm.arch.cris.common_v10_v32", 1192 absolute_section, 1193 (cris_arch == arch_cris_common_v10_v32), 1194 &zero_address_frag)); 1195 symbol_table_insert (symbol_new ("..asm.arch.cris.any_v0_v10", 1196 absolute_section, 1197 (cris_arch == arch_cris_any_v0_v10), 1198 &zero_address_frag)); 1199 1200 while (cris_opcodes[i].name != NULL) 1201 { 1202 const char *name = cris_opcodes[i].name; 1203 1204 if (! cris_insn_ver_valid_for_arch (cris_opcodes[i].applicable_version, 1205 cris_arch)) 1206 { 1207 i++; 1208 continue; 1209 } 1210 1211 /* Need to cast to get rid of "const". FIXME: Fix hash_insert instead. */ 1212 hashret = hash_insert (op_hash, name, (void *) &cris_opcodes[i]); 1213 1214 if (hashret != NULL && *hashret != '\0') 1215 as_fatal (_("Can't hash `%s': %s\n"), cris_opcodes[i].name, 1216 *hashret == 0 ? _("(unknown reason)") : hashret); 1217 do 1218 { 1219 if (cris_opcodes[i].match & cris_opcodes[i].lose) 1220 as_fatal (_("Buggy opcode: `%s' \"%s\"\n"), cris_opcodes[i].name, 1221 cris_opcodes[i].args); 1222 1223 ++i; 1224 } 1225 while (cris_opcodes[i].name != NULL 1226 && strcmp (cris_opcodes[i].name, name) == 0); 1227 } 1228} 1229 1230/* Assemble a source line. */ 1231 1232void 1233md_assemble (char *str) 1234{ 1235 struct cris_instruction output_instruction; 1236 struct cris_prefix prefix; 1237 char *opcodep; 1238 char *p; 1239 1240 know (str); 1241 1242 /* Do the low-level grunt - assemble to bits and split up into a prefix 1243 and ordinary insn. */ 1244 cris_process_instruction (str, &output_instruction, &prefix); 1245 1246 /* Handle any prefixes to the instruction. */ 1247 switch (prefix.kind) 1248 { 1249 case PREFIX_NONE: 1250 break; 1251 1252 /* When the expression is unknown for a BDAP, it can need 0, 2 or 4 1253 extra bytes, so we handle it separately. */ 1254 case PREFIX_BDAP_IMM: 1255 /* We only do it if the relocation is unspecified, i.e. not a PIC 1256 relocation. */ 1257 if (prefix.reloc == BFD_RELOC_NONE) 1258 { 1259 gen_bdap (prefix.base_reg_number, &prefix.expr); 1260 break; 1261 } 1262 /* Fall through. */ 1263 case PREFIX_BDAP: 1264 case PREFIX_BIAP: 1265 case PREFIX_DIP: 1266 opcodep = cris_insn_first_word_frag (); 1267 1268 /* Output the prefix opcode. */ 1269 md_number_to_chars (opcodep, (long) prefix.opcode, 2); 1270 1271 /* Having a specified reloc only happens for DIP and for BDAP with 1272 PIC operands, but it is ok to drop through here for the other 1273 prefixes as they can have no relocs specified. */ 1274 if (prefix.reloc != BFD_RELOC_NONE) 1275 { 1276 unsigned int relocsize 1277 = (prefix.kind == PREFIX_DIP 1278 ? 4 : cris_get_pic_reloc_size (prefix.reloc)); 1279 1280 p = frag_more (relocsize); 1281 fix_new_exp (frag_now, (p - frag_now->fr_literal), relocsize, 1282 &prefix.expr, 0, prefix.reloc); 1283 } 1284 break; 1285 1286 case PREFIX_PUSH: 1287 opcodep = cris_insn_first_word_frag (); 1288 1289 /* Output the prefix opcode. Being a "push", we add the negative 1290 size of the register to "sp". */ 1291 if (output_instruction.spec_reg != NULL) 1292 { 1293 /* Special register. */ 1294 opcodep[0] = -output_instruction.spec_reg->reg_size; 1295 } 1296 else 1297 { 1298 /* General register. */ 1299 opcodep[0] = -4; 1300 } 1301 opcodep[1] = (REG_SP << 4) + (BDAP_QUICK_OPCODE >> 8); 1302 break; 1303 1304 default: 1305 BAD_CASE (prefix.kind); 1306 } 1307 1308 /* If we only had a prefix insn, we're done. */ 1309 if (output_instruction.insn_type == CRIS_INSN_NONE) 1310 return; 1311 1312 /* Done with the prefix. Continue with the main instruction. */ 1313 if (prefix.kind == PREFIX_NONE) 1314 opcodep = cris_insn_first_word_frag (); 1315 else 1316 opcodep = frag_more (2); 1317 1318 /* Output the instruction opcode. */ 1319 md_number_to_chars (opcodep, (long) (output_instruction.opcode), 2); 1320 1321 /* Output the symbol-dependent instruction stuff. */ 1322 if (output_instruction.insn_type == CRIS_INSN_BRANCH) 1323 { 1324 segT to_seg = absolute_section; 1325 int is_undefined = 0; 1326 int length_code; 1327 1328 if (output_instruction.expr.X_op != O_constant) 1329 { 1330 to_seg = S_GET_SEGMENT (output_instruction.expr.X_add_symbol); 1331 1332 if (to_seg == undefined_section) 1333 is_undefined = 1; 1334 } 1335 1336 if (to_seg == now_seg || is_undefined 1337 /* In CRISv32, there *is* a 32-bit absolute branch, so don't 1338 emit the 12-byte sequence for known symbols in other 1339 segments. */ 1340 || (cris_arch == arch_crisv32 1341 && output_instruction.opcode == BA_QUICK_OPCODE)) 1342 { 1343 /* Handle complex expressions. */ 1344 valueT addvalue 1345 = (SIMPLE_EXPR (&output_instruction.expr) 1346 ? output_instruction.expr.X_add_number 1347 : 0); 1348 symbolS *sym 1349 = (SIMPLE_EXPR (&output_instruction.expr) 1350 ? output_instruction.expr.X_add_symbol 1351 : make_expr_symbol (&output_instruction.expr)); 1352 1353 /* If is_undefined, the expression may still become now_seg. 1354 That case is handled by md_estimate_size_before_relax. */ 1355 length_code = to_seg == now_seg ? STATE_BYTE : STATE_UNDF; 1356 1357 /* Make room for max twelve bytes of variable length for v32 mode 1358 or PIC, ten for v10 and older. */ 1359 frag_var (rs_machine_dependent, 1360 (cris_arch == arch_crisv32 1361 || cris_arch == arch_cris_common_v10_v32 1362 || pic) ? 12 : 10, 0, 1363 ENCODE_RELAX (cris_arch == arch_crisv32 1364 ? (output_instruction.opcode 1365 == BA_QUICK_OPCODE 1366 ? STATE_ABS_BRANCH_V32 1367 : STATE_COND_BRANCH_V32) 1368 : (cris_arch == arch_cris_common_v10_v32 1369 ? STATE_COND_BRANCH_COMMON 1370 : (pic ? STATE_COND_BRANCH_PIC 1371 : STATE_COND_BRANCH)), 1372 length_code), 1373 sym, addvalue, opcodep); 1374 } 1375 else 1376 { 1377 /* We have: to_seg != now_seg && to_seg != undefined_section. 1378 This means it is a branch to a known symbol in another 1379 section, perhaps an absolute address. Emit a 32-bit branch. */ 1380 char *cond_jump 1381 = frag_more ((cris_arch == arch_crisv32 1382 || cris_arch == arch_cris_common_v10_v32 1383 || pic) 1384 ? 12 : 10); 1385 1386 gen_cond_branch_32 (opcodep, cond_jump, frag_now, 1387 output_instruction.expr.X_add_symbol, 1388 (symbolS *) NULL, 1389 output_instruction.expr.X_add_number); 1390 } 1391 } 1392 else if (output_instruction.insn_type == CRIS_INSN_MUL 1393 && err_for_dangerous_mul_placement) 1394 /* Create a frag which which we track the location of the mul insn 1395 (in the last two bytes before the mul-frag). */ 1396 frag_variant (rs_machine_dependent, 0, 0, 1397 ENCODE_RELAX (STATE_MUL, STATE_BYTE), 1398 NULL, 0, opcodep); 1399 else 1400 { 1401 if (output_instruction.imm_oprnd_size > 0) 1402 { 1403 /* The instruction has an immediate operand. */ 1404 enum bfd_reloc_code_real reloc = BFD_RELOC_NONE; 1405 1406 switch (output_instruction.imm_oprnd_size) 1407 { 1408 /* Any byte-size immediate constants are treated as 1409 word-size. FIXME: Thus overflow check does not work 1410 correctly. */ 1411 1412 case 2: 1413 /* Note that size-check for the explicit reloc has already 1414 been done when we get here. */ 1415 if (output_instruction.reloc != BFD_RELOC_NONE) 1416 reloc = output_instruction.reloc; 1417 else 1418 reloc = BFD_RELOC_16; 1419 break; 1420 1421 case 4: 1422 /* Allow a relocation specified in the operand. */ 1423 if (output_instruction.reloc != BFD_RELOC_NONE) 1424 reloc = output_instruction.reloc; 1425 else 1426 reloc = BFD_RELOC_32; 1427 break; 1428 1429 default: 1430 BAD_CASE (output_instruction.imm_oprnd_size); 1431 } 1432 1433 p = frag_more (output_instruction.imm_oprnd_size); 1434 fix_new_exp (frag_now, (p - frag_now->fr_literal), 1435 output_instruction.imm_oprnd_size, 1436 &output_instruction.expr, 1437 reloc == BFD_RELOC_32_PCREL 1438 || reloc == BFD_RELOC_16_PCREL 1439 || reloc == BFD_RELOC_8_PCREL, reloc); 1440 } 1441 else if (output_instruction.reloc == BFD_RELOC_CRIS_LAPCQ_OFFSET 1442 && output_instruction.expr.X_md != 0) 1443 { 1444 /* Handle complex expressions. */ 1445 valueT addvalue 1446 = (output_instruction.expr.X_op_symbol != NULL 1447 ? 0 : output_instruction.expr.X_add_number); 1448 symbolS *sym 1449 = (output_instruction.expr.X_op_symbol != NULL 1450 ? make_expr_symbol (&output_instruction.expr) 1451 : output_instruction.expr.X_add_symbol); 1452 1453 /* This is a relaxing construct, so we need a frag_var rather 1454 than the fix_new_exp call below. */ 1455 frag_var (rs_machine_dependent, 1456 4, 0, 1457 ENCODE_RELAX (STATE_LAPC, STATE_UNDF), 1458 sym, addvalue, opcodep); 1459 } 1460 else if (output_instruction.reloc != BFD_RELOC_NONE) 1461 { 1462 /* An immediate operand that has a relocation and needs to be 1463 processed further. */ 1464 1465 /* It is important to use fix_new_exp here and everywhere else 1466 (and not fix_new), as fix_new_exp can handle "difference 1467 expressions" - where the expression contains a difference of 1468 two symbols in the same segment. */ 1469 fix_new_exp (frag_now, (opcodep - frag_now->fr_literal), 2, 1470 &output_instruction.expr, 1471 output_instruction.reloc == BFD_RELOC_32_PCREL 1472 || output_instruction.reloc == BFD_RELOC_16_PCREL 1473 || output_instruction.reloc == BFD_RELOC_8_PCREL 1474 || (output_instruction.reloc 1475 == BFD_RELOC_CRIS_LAPCQ_OFFSET), 1476 output_instruction.reloc); 1477 } 1478 } 1479} 1480 1481/* Low level text-to-bits assembly. */ 1482 1483static void 1484cris_process_instruction (char *insn_text, struct cris_instruction *out_insnp, 1485 struct cris_prefix *prefixp) 1486{ 1487 char *s; 1488 char modified_char = 0; 1489 const char *args; 1490 struct cris_opcode *instruction; 1491 char *operands; 1492 int match = 0; 1493 int mode; 1494 int regno; 1495 int size_bits; 1496 1497 /* Reset these fields to a harmless state in case we need to return in 1498 error. */ 1499 prefixp->kind = PREFIX_NONE; 1500 prefixp->reloc = BFD_RELOC_NONE; 1501 out_insnp->insn_type = CRIS_INSN_NONE; 1502 out_insnp->imm_oprnd_size = 0; 1503 1504 /* Find the end of the opcode mnemonic. We assume (true in 2.9.1) 1505 that the caller has translated the opcode to lower-case, up to the 1506 first non-letter. */ 1507 for (operands = insn_text; ISLOWER (*operands); ++operands) 1508 ; 1509 1510 /* Terminate the opcode after letters, but save the character there if 1511 it was of significance. */ 1512 switch (*operands) 1513 { 1514 case '\0': 1515 break; 1516 1517 case '.': 1518 /* Put back the modified character later. */ 1519 modified_char = *operands; 1520 /* Fall through. */ 1521 1522 case ' ': 1523 /* Consume the character after the mnemonic 1524 and replace it with '\0'. */ 1525 *operands++ = '\0'; 1526 break; 1527 1528 default: 1529 as_bad (_("Unknown opcode: `%s'"), insn_text); 1530 return; 1531 } 1532 1533 /* Find the instruction. */ 1534 instruction = (struct cris_opcode *) hash_find (op_hash, insn_text); 1535 if (instruction == NULL) 1536 { 1537 as_bad (_("Unknown opcode: `%s'"), insn_text); 1538 return; 1539 } 1540 1541 /* Put back the modified character. */ 1542 switch (modified_char) 1543 { 1544 case 0: 1545 break; 1546 1547 default: 1548 *--operands = modified_char; 1549 } 1550 1551 /* Try to match an opcode table slot. */ 1552 for (s = operands;;) 1553 { 1554 int imm_expr_found; 1555 1556 /* Initialize *prefixp, perhaps after being modified for a 1557 "near match". */ 1558 prefixp->kind = PREFIX_NONE; 1559 prefixp->reloc = BFD_RELOC_NONE; 1560 1561 /* Initialize *out_insnp. */ 1562 memset (out_insnp, 0, sizeof (*out_insnp)); 1563 out_insnp->opcode = instruction->match; 1564 out_insnp->reloc = BFD_RELOC_NONE; 1565 out_insnp->insn_type = CRIS_INSN_NORMAL; 1566 out_insnp->imm_oprnd_size = 0; 1567 1568 imm_expr_found = 0; 1569 1570 /* Build the opcode, checking as we go to make sure that the 1571 operands match. */ 1572 for (args = instruction->args;; ++args) 1573 { 1574 switch (*args) 1575 { 1576 case '\0': 1577 /* If we've come to the end of arguments, we're done. */ 1578 if (*s == '\0') 1579 match = 1; 1580 break; 1581 1582 case '!': 1583 /* Non-matcher character for disassembly. 1584 Ignore it here. */ 1585 continue; 1586 1587 case '[': 1588 case ']': 1589 case ',': 1590 case ' ': 1591 /* These must match exactly. */ 1592 if (*s++ == *args) 1593 continue; 1594 break; 1595 1596 case 'A': 1597 /* "ACR", case-insensitive. 1598 Handle a sometimes-mandatory dollar sign as register 1599 prefix. */ 1600 if (*s == REGISTER_PREFIX_CHAR) 1601 s++; 1602 else if (demand_register_prefix) 1603 break; 1604 1605 if ((*s++ != 'a' && s[-1] != 'A') 1606 || (*s++ != 'c' && s[-1] != 'C') 1607 || (*s++ != 'r' && s[-1] != 'R')) 1608 break; 1609 continue; 1610 1611 case 'B': 1612 /* This is not really an operand, but causes a "BDAP 1613 -size,SP" prefix to be output, for PUSH instructions. */ 1614 prefixp->kind = PREFIX_PUSH; 1615 continue; 1616 1617 case 'b': 1618 /* This letter marks an operand that should not be matched 1619 in the assembler. It is a branch with 16-bit 1620 displacement. The assembler will create them from the 1621 8-bit flavor when necessary. The assembler does not 1622 support the [rN+] operand, as the [r15+] that is 1623 generated for 16-bit displacements. */ 1624 break; 1625 1626 case 'c': 1627 /* A 5-bit unsigned immediate in bits <4:0>. */ 1628 if (! cris_get_expression (&s, &out_insnp->expr)) 1629 break; 1630 else 1631 { 1632 if (out_insnp->expr.X_op == O_constant 1633 && (out_insnp->expr.X_add_number < 0 1634 || out_insnp->expr.X_add_number > 31)) 1635 as_bad (_("Immediate value not in 5 bit unsigned range: %ld"), 1636 out_insnp->expr.X_add_number); 1637 1638 out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_5; 1639 continue; 1640 } 1641 1642 case 'C': 1643 /* A 4-bit unsigned immediate in bits <3:0>. */ 1644 if (! cris_get_expression (&s, &out_insnp->expr)) 1645 break; 1646 else 1647 { 1648 if (out_insnp->expr.X_op == O_constant 1649 && (out_insnp->expr.X_add_number < 0 1650 || out_insnp->expr.X_add_number > 15)) 1651 as_bad (_("Immediate value not in 4 bit unsigned range: %ld"), 1652 out_insnp->expr.X_add_number); 1653 1654 out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_4; 1655 continue; 1656 } 1657 1658 /* For 'd', check for an optional ".d" or ".D" at the 1659 start of the operands, followed by a space character. */ 1660 case 'd': 1661 if (modified_char == '.' && *s == '.') 1662 { 1663 if ((s[1] != 'd' && s[1] == 'D') 1664 || ! ISSPACE (s[2])) 1665 break; 1666 s += 2; 1667 continue; 1668 } 1669 continue; 1670 1671 case 'D': 1672 /* General register in bits <15:12> and <3:0>. */ 1673 if (! get_gen_reg (&s, ®no)) 1674 break; 1675 else 1676 { 1677 out_insnp->opcode |= regno /* << 0 */; 1678 out_insnp->opcode |= regno << 12; 1679 continue; 1680 } 1681 1682 case 'f': 1683 /* Flags from the condition code register. */ 1684 { 1685 int flags = 0; 1686 1687 if (! get_flags (&s, &flags)) 1688 break; 1689 1690 out_insnp->opcode |= ((flags & 0xf0) << 8) | (flags & 0xf); 1691 continue; 1692 } 1693 1694 case 'i': 1695 /* A 6-bit signed immediate in bits <5:0>. */ 1696 if (! cris_get_expression (&s, &out_insnp->expr)) 1697 break; 1698 else 1699 { 1700 if (out_insnp->expr.X_op == O_constant 1701 && (out_insnp->expr.X_add_number < -32 1702 || out_insnp->expr.X_add_number > 31)) 1703 as_bad (_("Immediate value not in 6 bit range: %ld"), 1704 out_insnp->expr.X_add_number); 1705 out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_6; 1706 continue; 1707 } 1708 1709 case 'I': 1710 /* A 6-bit unsigned immediate in bits <5:0>. */ 1711 if (! cris_get_expression (&s, &out_insnp->expr)) 1712 break; 1713 else 1714 { 1715 if (out_insnp->expr.X_op == O_constant 1716 && (out_insnp->expr.X_add_number < 0 1717 || out_insnp->expr.X_add_number > 63)) 1718 as_bad (_("Immediate value not in 6 bit unsigned range: %ld"), 1719 out_insnp->expr.X_add_number); 1720 out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_6; 1721 continue; 1722 } 1723 1724 case 'M': 1725 /* A size modifier, B, W or D, to be put in a bit position 1726 suitable for CLEAR instructions (i.e. reflecting a zero 1727 register). */ 1728 if (! get_bwd_size_modifier (&s, &size_bits)) 1729 break; 1730 else 1731 { 1732 switch (size_bits) 1733 { 1734 case 0: 1735 out_insnp->opcode |= 0 << 12; 1736 break; 1737 1738 case 1: 1739 out_insnp->opcode |= 4 << 12; 1740 break; 1741 1742 case 2: 1743 out_insnp->opcode |= 8 << 12; 1744 break; 1745 } 1746 continue; 1747 } 1748 1749 case 'm': 1750 /* A size modifier, B, W or D, to be put in bits <5:4>. */ 1751 if (modified_char != '.' 1752 || ! get_bwd_size_modifier (&s, &size_bits)) 1753 break; 1754 else 1755 { 1756 out_insnp->opcode |= size_bits << 4; 1757 continue; 1758 } 1759 1760 case 'o': 1761 /* A branch expression. */ 1762 if (! cris_get_expression (&s, &out_insnp->expr)) 1763 break; 1764 else 1765 { 1766 out_insnp->insn_type = CRIS_INSN_BRANCH; 1767 continue; 1768 } 1769 1770 case 'Q': 1771 /* A 8-bit quick BDAP expression, "expr,R". */ 1772 if (! cris_get_expression (&s, &out_insnp->expr)) 1773 break; 1774 1775 if (*s != ',') 1776 break; 1777 1778 s++; 1779 1780 if (!get_gen_reg (&s, ®no)) 1781 break; 1782 1783 out_insnp->opcode |= regno << 12; 1784 out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_8; 1785 continue; 1786 1787 case 'O': 1788 /* A BDAP expression for any size, "expr,R". */ 1789 if (! cris_get_expression (&s, &prefixp->expr)) 1790 break; 1791 else 1792 { 1793 if (*s != ',') 1794 break; 1795 1796 s++; 1797 1798 if (!get_gen_reg (&s, &prefixp->base_reg_number)) 1799 break; 1800 1801 /* Since 'O' is used with an explicit bdap, we have no 1802 "real" instruction. */ 1803 prefixp->kind = PREFIX_BDAP_IMM; 1804 prefixp->opcode 1805 = BDAP_QUICK_OPCODE | (prefixp->base_reg_number << 12); 1806 1807 out_insnp->insn_type = CRIS_INSN_NONE; 1808 continue; 1809 } 1810 1811 case 'P': 1812 /* Special register in bits <15:12>. */ 1813 if (! get_spec_reg (&s, &out_insnp->spec_reg)) 1814 break; 1815 else 1816 { 1817 /* Use of some special register names come with a 1818 specific warning. Note that we have no ".cpu type" 1819 pseudo yet, so some of this is just unused 1820 framework. */ 1821 if (out_insnp->spec_reg->warning) 1822 as_warn (out_insnp->spec_reg->warning); 1823 else if (out_insnp->spec_reg->applicable_version 1824 == cris_ver_warning) 1825 /* Others have a generic warning. */ 1826 as_warn (_("Unimplemented register `%s' specified"), 1827 out_insnp->spec_reg->name); 1828 1829 out_insnp->opcode 1830 |= out_insnp->spec_reg->number << 12; 1831 continue; 1832 } 1833 1834 case 'p': 1835 /* This character is used in the disassembler to 1836 recognize a prefix instruction to fold into the 1837 addressing mode for the next instruction. It is 1838 ignored here. */ 1839 continue; 1840 1841 case 'R': 1842 /* General register in bits <15:12>. */ 1843 if (! get_gen_reg (&s, ®no)) 1844 break; 1845 else 1846 { 1847 out_insnp->opcode |= regno << 12; 1848 continue; 1849 } 1850 1851 case 'r': 1852 /* General register in bits <3:0>. */ 1853 if (! get_gen_reg (&s, ®no)) 1854 break; 1855 else 1856 { 1857 out_insnp->opcode |= regno /* << 0 */; 1858 continue; 1859 } 1860 1861 case 'S': 1862 /* Source operand in bit <10> and a prefix; a 3-operand 1863 prefix. */ 1864 if (! get_3op_or_dip_prefix_op (&s, prefixp)) 1865 break; 1866 else 1867 continue; 1868 1869 case 's': 1870 /* Source operand in bits <10>, <3:0> and optionally a 1871 prefix; i.e. an indirect operand or an side-effect 1872 prefix (where valid). */ 1873 if (! get_autoinc_prefix_or_indir_op (&s, prefixp, &mode, 1874 ®no, 1875 &imm_expr_found, 1876 &out_insnp->expr)) 1877 break; 1878 else 1879 { 1880 if (prefixp->kind != PREFIX_NONE) 1881 { 1882 /* A prefix, so it has the autoincrement bit 1883 set. */ 1884 out_insnp->opcode |= (AUTOINCR_BIT << 8); 1885 } 1886 else 1887 { 1888 /* No prefix. The "mode" variable contains bits like 1889 whether or not this is autoincrement mode. */ 1890 out_insnp->opcode |= (mode << 10); 1891 1892 /* If there was a PIC reloc specifier, then it was 1893 attached to the prefix. Note that we can't check 1894 that the reloc size matches, since we don't have 1895 all the operands yet in all cases. */ 1896 if (prefixp->reloc != BFD_RELOC_NONE) 1897 out_insnp->reloc = prefixp->reloc; 1898 } 1899 1900 out_insnp->opcode |= regno /* << 0 */ ; 1901 continue; 1902 } 1903 1904 case 'N': 1905 case 'Y': 1906 /* Like 's', but immediate operand only. Also does not 1907 modify insn. There are no insns where a PIC reloc 1908 specifier makes sense. */ 1909 if (cris_get_expression (&s, &out_insnp->expr)) 1910 { 1911 imm_expr_found = 1; 1912 continue; 1913 } 1914 break; 1915 1916 case 'n': 1917 /* Like 'N', but PC-relative to the start of the insn. 1918 There might be a :PLT to request a PLT entry. */ 1919 if (cris_get_expression (&s, &out_insnp->expr)) 1920 { 1921 imm_expr_found = 1; 1922 out_insnp->reloc = BFD_RELOC_32_PCREL; 1923 1924 /* We have to adjust the expression, because that 1925 relocation is to the location *after* the 1926 relocation. So add 2 for the insn and 4 for the 1927 relocation. */ 1928 out_insnp->expr.X_add_number += 6; 1929 1930 if (pic && *s == PIC_SUFFIX_CHAR) 1931 cris_get_pic_suffix (&s, &out_insnp->reloc, 1932 &out_insnp->expr); 1933 1934 continue; 1935 } 1936 break; 1937 1938 case 'U': 1939 /* Maybe 'u', maybe 'n'. Only for LAPC/LAPCQ. */ 1940 if (cris_get_expression (&s, &out_insnp->expr)) 1941 { 1942 out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET; 1943 1944 /* Define 1 as relaxing. */ 1945 out_insnp->expr.X_md = 1; 1946 continue; 1947 } 1948 break; 1949 1950 case 'u': 1951 /* Four PC-relative bits in <3:0> representing <4:1>:0 of 1952 an offset relative to the beginning of the current 1953 insn. */ 1954 if (cris_get_expression (&s, &out_insnp->expr)) 1955 { 1956 out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET; 1957 1958 /* Define 0 as non-relaxing. */ 1959 out_insnp->expr.X_md = 0; 1960 1961 /* We have to adjust the expression, because that 1962 relocation is to the location *after* the 1963 insn. So add 2 for the insn. */ 1964 out_insnp->expr.X_add_number += 2; 1965 continue; 1966 } 1967 break; 1968 1969 case 'x': 1970 /* Rs.m in bits <15:12> and <5:4>. */ 1971 if (! get_gen_reg (&s, ®no) 1972 || ! get_bwd_size_modifier (&s, &size_bits)) 1973 break; 1974 else 1975 { 1976 out_insnp->opcode |= (regno << 12) | (size_bits << 4); 1977 continue; 1978 } 1979 1980 case 'y': 1981 /* Source operand in bits <10>, <3:0> and optionally a 1982 prefix; i.e. an indirect operand or an side-effect 1983 prefix. 1984 1985 The difference to 's' is that this does not allow an 1986 "immediate" expression. */ 1987 if (! get_autoinc_prefix_or_indir_op (&s, prefixp, 1988 &mode, ®no, 1989 &imm_expr_found, 1990 &out_insnp->expr) 1991 || imm_expr_found) 1992 break; 1993 else 1994 { 1995 if (prefixp->kind != PREFIX_NONE) 1996 { 1997 /* A prefix, and those matched here always have 1998 side-effects (see 's' case). */ 1999 out_insnp->opcode |= (AUTOINCR_BIT << 8); 2000 } 2001 else 2002 { 2003 /* No prefix. The "mode" variable contains bits 2004 like whether or not this is autoincrement 2005 mode. */ 2006 out_insnp->opcode |= (mode << 10); 2007 } 2008 2009 out_insnp->opcode |= regno /* << 0 */; 2010 continue; 2011 } 2012 2013 case 'z': 2014 /* Size modifier (B or W) in bit <4>. */ 2015 if (! get_bw_size_modifier (&s, &size_bits)) 2016 break; 2017 else 2018 { 2019 out_insnp->opcode |= size_bits << 4; 2020 continue; 2021 } 2022 2023 case 'T': 2024 if (cris_arch == arch_crisv32 2025 && get_sup_reg (&s, ®no)) 2026 { 2027 out_insnp->opcode |= regno << 12; 2028 continue; 2029 } 2030 break; 2031 2032 default: 2033 BAD_CASE (*args); 2034 } 2035 2036 /* We get here when we fail a match above or we found a 2037 complete match. Break out of this loop. */ 2038 break; 2039 } 2040 2041 /* Was it a match or a miss? */ 2042 if (match == 0) 2043 { 2044 /* If it's just that the args don't match, maybe the next 2045 item in the table is the same opcode but with 2046 matching operands. First skip any invalid ones. */ 2047 while (instruction[1].name != NULL 2048 && strcmp (instruction->name, instruction[1].name) == 0 2049 && ! cris_insn_ver_valid_for_arch (instruction[1] 2050 .applicable_version, 2051 cris_arch)) 2052 ++instruction; 2053 2054 if (instruction[1].name != NULL 2055 && strcmp (instruction->name, instruction[1].name) == 0 2056 && cris_insn_ver_valid_for_arch (instruction[1] 2057 .applicable_version, 2058 cris_arch)) 2059 { 2060 /* Yep. Restart and try that one instead. */ 2061 ++instruction; 2062 s = operands; 2063 continue; 2064 } 2065 else 2066 { 2067 /* We've come to the end of instructions with this 2068 opcode, so it must be an error. */ 2069 as_bad (_("Illegal operands")); 2070 2071 /* As discard_rest_of_line, but without continuing to the 2072 next line. */ 2073 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 2074 input_line_pointer++; 2075 return; 2076 } 2077 } 2078 else 2079 { 2080 /* We have a match. Check if there's anything more to do. */ 2081 if (imm_expr_found) 2082 { 2083 /* There was an immediate mode operand, so we must check 2084 that it has an appropriate size. */ 2085 switch (instruction->imm_oprnd_size) 2086 { 2087 default: 2088 case SIZE_NONE: 2089 /* Shouldn't happen; this one does not have immediate 2090 operands with different sizes. */ 2091 BAD_CASE (instruction->imm_oprnd_size); 2092 break; 2093 2094 case SIZE_FIX_32: 2095 out_insnp->imm_oprnd_size = 4; 2096 break; 2097 2098 case SIZE_SPEC_REG: 2099 if (cris_arch == arch_crisv32) 2100 /* All immediate loads of special registers are 2101 32-bit on CRISv32. */ 2102 out_insnp->imm_oprnd_size = 4; 2103 else 2104 switch (out_insnp->spec_reg->reg_size) 2105 { 2106 case 1: 2107 if (out_insnp->expr.X_op == O_constant 2108 && (out_insnp->expr.X_add_number < -128 2109 || out_insnp->expr.X_add_number > 255)) 2110 as_bad (_("Immediate value not in 8 bit range: %ld"), 2111 out_insnp->expr.X_add_number); 2112 /* Fall through. */ 2113 case 2: 2114 /* FIXME: We need an indicator in the instruction 2115 table to pass on, to indicate if we need to check 2116 overflow for a signed or unsigned number. */ 2117 if (out_insnp->expr.X_op == O_constant 2118 && (out_insnp->expr.X_add_number < -32768 2119 || out_insnp->expr.X_add_number > 65535)) 2120 as_bad (_("Immediate value not in 16 bit range: %ld"), 2121 out_insnp->expr.X_add_number); 2122 out_insnp->imm_oprnd_size = 2; 2123 break; 2124 2125 case 4: 2126 out_insnp->imm_oprnd_size = 4; 2127 break; 2128 2129 default: 2130 BAD_CASE (out_insnp->spec_reg->reg_size); 2131 } 2132 break; 2133 2134 case SIZE_FIELD: 2135 case SIZE_FIELD_SIGNED: 2136 case SIZE_FIELD_UNSIGNED: 2137 switch (size_bits) 2138 { 2139 /* FIXME: Find way to pass un/signedness to 2140 caller, and set reloc type instead, postponing 2141 this check until cris_number_to_imm. That 2142 necessarily corrects the reloc type for the 2143 byte case, maybe requiring further changes. */ 2144 case 0: 2145 if (out_insnp->expr.X_op == O_constant) 2146 { 2147 if (instruction->imm_oprnd_size == SIZE_FIELD 2148 && (out_insnp->expr.X_add_number < -128 2149 || out_insnp->expr.X_add_number > 255)) 2150 as_bad (_("Immediate value not in 8 bit range: %ld"), 2151 out_insnp->expr.X_add_number); 2152 else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED 2153 && (out_insnp->expr.X_add_number < -128 2154 || out_insnp->expr.X_add_number > 127)) 2155 as_bad (_("Immediate value not in 8 bit signed range: %ld"), 2156 out_insnp->expr.X_add_number); 2157 else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED 2158 && (out_insnp->expr.X_add_number < 0 2159 || out_insnp->expr.X_add_number > 255)) 2160 as_bad (_("Immediate value not in 8 bit unsigned range: %ld"), 2161 out_insnp->expr.X_add_number); 2162 } 2163 2164 /* Fall through. */ 2165 case 1: 2166 if (out_insnp->expr.X_op == O_constant) 2167 { 2168 if (instruction->imm_oprnd_size == SIZE_FIELD 2169 && (out_insnp->expr.X_add_number < -32768 2170 || out_insnp->expr.X_add_number > 65535)) 2171 as_bad (_("Immediate value not in 16 bit range: %ld"), 2172 out_insnp->expr.X_add_number); 2173 else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED 2174 && (out_insnp->expr.X_add_number < -32768 2175 || out_insnp->expr.X_add_number > 32767)) 2176 as_bad (_("Immediate value not in 16 bit signed range: %ld"), 2177 out_insnp->expr.X_add_number); 2178 else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED 2179 && (out_insnp->expr.X_add_number < 0 2180 || out_insnp->expr.X_add_number > 65535)) 2181 as_bad (_("Immediate value not in 16 bit unsigned range: %ld"), 2182 out_insnp->expr.X_add_number); 2183 } 2184 out_insnp->imm_oprnd_size = 2; 2185 break; 2186 2187 case 2: 2188 out_insnp->imm_oprnd_size = 4; 2189 break; 2190 2191 default: 2192 BAD_CASE (out_insnp->spec_reg->reg_size); 2193 } 2194 } 2195 2196 /* If there was a relocation specified for the immediate 2197 expression (i.e. it had a PIC modifier) check that the 2198 size of the PIC relocation matches the size specified by 2199 the opcode. */ 2200 if (out_insnp->reloc != BFD_RELOC_NONE 2201 && (cris_get_pic_reloc_size (out_insnp->reloc) 2202 != (unsigned int) out_insnp->imm_oprnd_size)) 2203 as_bad (_("PIC relocation size does not match operand size")); 2204 } 2205 else if (instruction->op == cris_muls_op 2206 || instruction->op == cris_mulu_op) 2207 out_insnp->insn_type = CRIS_INSN_MUL; 2208 } 2209 break; 2210 } 2211} 2212 2213/* Get a B, W, or D size modifier from the string pointed out by *cPP, 2214 which must point to a '.' in front of the modifier. On successful 2215 return, *cPP is advanced to the character following the size 2216 modifier, and is undefined otherwise. 2217 2218 cPP Pointer to pointer to string starting 2219 with the size modifier. 2220 2221 size_bitsp Pointer to variable to contain the size bits on 2222 successful return. 2223 2224 Return 1 iff a correct size modifier is found, else 0. */ 2225 2226static int 2227get_bwd_size_modifier (char **cPP, int *size_bitsp) 2228{ 2229 if (**cPP != '.') 2230 return 0; 2231 else 2232 { 2233 /* Consume the '.'. */ 2234 (*cPP)++; 2235 2236 switch (**cPP) 2237 { 2238 case 'B': 2239 case 'b': 2240 *size_bitsp = 0; 2241 break; 2242 2243 case 'W': 2244 case 'w': 2245 *size_bitsp = 1; 2246 break; 2247 2248 case 'D': 2249 case 'd': 2250 *size_bitsp = 2; 2251 break; 2252 2253 default: 2254 return 0; 2255 } 2256 2257 /* Consume the size letter. */ 2258 (*cPP)++; 2259 return 1; 2260 } 2261} 2262 2263/* Get a B or W size modifier from the string pointed out by *cPP, 2264 which must point to a '.' in front of the modifier. On successful 2265 return, *cPP is advanced to the character following the size 2266 modifier, and is undefined otherwise. 2267 2268 cPP Pointer to pointer to string starting 2269 with the size modifier. 2270 2271 size_bitsp Pointer to variable to contain the size bits on 2272 successful return. 2273 2274 Return 1 iff a correct size modifier is found, else 0. */ 2275 2276static int 2277get_bw_size_modifier (char **cPP, int *size_bitsp) 2278{ 2279 if (**cPP != '.') 2280 return 0; 2281 else 2282 { 2283 /* Consume the '.'. */ 2284 (*cPP)++; 2285 2286 switch (**cPP) 2287 { 2288 case 'B': 2289 case 'b': 2290 *size_bitsp = 0; 2291 break; 2292 2293 case 'W': 2294 case 'w': 2295 *size_bitsp = 1; 2296 break; 2297 2298 default: 2299 return 0; 2300 } 2301 2302 /* Consume the size letter. */ 2303 (*cPP)++; 2304 return 1; 2305 } 2306} 2307 2308/* Get a general register from the string pointed out by *cPP. The 2309 variable *cPP is advanced to the character following the general 2310 register name on a successful return, and has its initial position 2311 otherwise. 2312 2313 cPP Pointer to pointer to string, beginning with a general 2314 register name. 2315 2316 regnop Pointer to int containing the register number. 2317 2318 Return 1 iff a correct general register designator is found, 2319 else 0. */ 2320 2321static int 2322get_gen_reg (char **cPP, int *regnop) 2323{ 2324 char *oldp; 2325 oldp = *cPP; 2326 2327 /* Handle a sometimes-mandatory dollar sign as register prefix. */ 2328 if (**cPP == REGISTER_PREFIX_CHAR) 2329 (*cPP)++; 2330 else if (demand_register_prefix) 2331 return 0; 2332 2333 switch (**cPP) 2334 { 2335 case 'P': 2336 case 'p': 2337 /* "P" as in "PC"? Consume the "P". */ 2338 (*cPP)++; 2339 2340 if ((**cPP == 'C' || **cPP == 'c') 2341 && ! ISALNUM ((*cPP)[1]) 2342 /* Here's a little twist: For v32 and the compatibility mode, 2343 we only recognize PC as a register number if there's '+]' 2344 after. We don't consume that, but the presence can only be 2345 valid after a register in a post-increment context, which 2346 is also the only valid context for PC as a register for 2347 v32. Not that it's used very often, but saying "MOVE.D 2348 [PC+],R5" should remain valid. It's not supported for 2349 jump-type insns or other insns with no [Rn+] mode, though. */ 2350 && ((cris_arch != arch_crisv32 2351 && cris_arch != arch_cris_common_v10_v32) 2352 || ((*cPP)[1] == '+' && (*cPP)[2] == ']'))) 2353 { 2354 /* It's "PC": consume the "c" and we're done. */ 2355 (*cPP)++; 2356 *regnop = REG_PC; 2357 return 1; 2358 } 2359 break; 2360 2361 /* Like with PC, we recognize ACR, but only if it's *not* followed 2362 by '+', and only for v32. */ 2363 case 'A': 2364 case 'a': 2365 if (cris_arch != arch_crisv32 2366 || ((*cPP)[1] != 'c' && (*cPP)[1] != 'C') 2367 || ((*cPP)[2] != 'r' && (*cPP)[2] != 'R') 2368 || ISALNUM ((*cPP)[3]) 2369 || (*cPP)[3] == '+') 2370 break; 2371 (*cPP) += 3; 2372 *regnop = 15; 2373 return 1; 2374 2375 case 'R': 2376 case 'r': 2377 /* Hopefully r[0-9] or r1[0-5]. Consume 'R' or 'r'. */ 2378 (*cPP)++; 2379 2380 if (ISDIGIT (**cPP)) 2381 { 2382 /* It's r[0-9]. Consume and check the next digit. */ 2383 *regnop = **cPP - '0'; 2384 (*cPP)++; 2385 2386 if (! ISALNUM (**cPP)) 2387 { 2388 /* No more digits, we're done. */ 2389 return 1; 2390 } 2391 else 2392 { 2393 /* One more digit. Consume and add. */ 2394 *regnop = *regnop * 10 + (**cPP - '0'); 2395 2396 /* We need to check for a valid register number; Rn, 2397 0 <= n <= MAX_REG. */ 2398 if (*regnop <= MAX_REG) 2399 { 2400 /* Consume second digit. */ 2401 (*cPP)++; 2402 return 1; 2403 } 2404 } 2405 } 2406 break; 2407 2408 case 'S': 2409 case 's': 2410 /* "S" as in "SP"? Consume the "S". */ 2411 (*cPP)++; 2412 if (**cPP == 'P' || **cPP == 'p') 2413 { 2414 /* It's "SP": consume the "p" and we're done. */ 2415 (*cPP)++; 2416 *regnop = REG_SP; 2417 return 1; 2418 } 2419 break; 2420 2421 default: 2422 /* Just here to silence compilation warnings. */ 2423 ; 2424 } 2425 2426 /* We get here if we fail. Restore the pointer. */ 2427 *cPP = oldp; 2428 return 0; 2429} 2430 2431/* Get a special register from the string pointed out by *cPP. The 2432 variable *cPP is advanced to the character following the special 2433 register name if one is found, and retains its original position 2434 otherwise. 2435 2436 cPP Pointer to pointer to string starting with a special register 2437 name. 2438 2439 sregpp Pointer to Pointer to struct spec_reg, where a pointer to the 2440 register description will be stored. 2441 2442 Return 1 iff a correct special register name is found. */ 2443 2444static int 2445get_spec_reg (char **cPP, const struct cris_spec_reg **sregpp) 2446{ 2447 char *s1; 2448 const char *s2; 2449 char *name_begin = *cPP; 2450 2451 const struct cris_spec_reg *sregp; 2452 2453 /* Handle a sometimes-mandatory dollar sign as register prefix. */ 2454 if (*name_begin == REGISTER_PREFIX_CHAR) 2455 name_begin++; 2456 else if (demand_register_prefix) 2457 return 0; 2458 2459 /* Loop over all special registers. */ 2460 for (sregp = cris_spec_regs; sregp->name != NULL; sregp++) 2461 { 2462 /* Start over from beginning of the supposed name. */ 2463 s1 = name_begin; 2464 s2 = sregp->name; 2465 2466 while (*s2 != '\0' && TOLOWER (*s1) == *s2) 2467 { 2468 s1++; 2469 s2++; 2470 } 2471 2472 /* For a match, we must have consumed the name in the table, and we 2473 must be outside what could be part of a name. Assume here that a 2474 test for alphanumerics is sufficient for a name test. */ 2475 if (*s2 == 0 && ! ISALNUM (*s1) 2476 && cris_insn_ver_valid_for_arch (sregp->applicable_version, 2477 cris_arch)) 2478 { 2479 /* We have a match. Update the pointer and be done. */ 2480 *cPP = s1; 2481 *sregpp = sregp; 2482 return 1; 2483 } 2484 } 2485 2486 /* If we got here, we did not find any name. */ 2487 return 0; 2488} 2489 2490/* Get a support register from the string pointed out by *cPP. The 2491 variable *cPP is advanced to the character following the support- 2492 register name if one is found, and retains its original position 2493 otherwise. 2494 2495 cPP Pointer to pointer to string starting with a support-register 2496 name. 2497 2498 sregpp Pointer to int containing the register number. 2499 2500 Return 1 iff a correct support-register name is found. */ 2501 2502static int 2503get_sup_reg (char **cPP, int *regnop) 2504{ 2505 char *s1; 2506 const char *s2; 2507 char *name_begin = *cPP; 2508 2509 const struct cris_support_reg *sregp; 2510 2511 /* Handle a sometimes-mandatory dollar sign as register prefix. */ 2512 if (*name_begin == REGISTER_PREFIX_CHAR) 2513 name_begin++; 2514 else if (demand_register_prefix) 2515 return 0; 2516 2517 /* Loop over all support-registers. */ 2518 for (sregp = cris_support_regs; sregp->name != NULL; sregp++) 2519 { 2520 /* Start over from beginning of the supposed name. */ 2521 s1 = name_begin; 2522 s2 = sregp->name; 2523 2524 while (*s2 != '\0' && TOLOWER (*s1) == *s2) 2525 { 2526 s1++; 2527 s2++; 2528 } 2529 2530 /* For a match, we must have consumed the name in the table, and we 2531 must be outside what could be part of a name. Assume here that a 2532 test for alphanumerics is sufficient for a name test. */ 2533 if (*s2 == 0 && ! ISALNUM (*s1)) 2534 { 2535 /* We have a match. Update the pointer and be done. */ 2536 *cPP = s1; 2537 *regnop = sregp->number; 2538 return 1; 2539 } 2540 } 2541 2542 /* If we got here, we did not find any name. */ 2543 return 0; 2544} 2545 2546/* Get an unprefixed or side-effect-prefix operand from the string pointed 2547 out by *cPP. The pointer *cPP is advanced to the character following 2548 the indirect operand if we have success, else it contains an undefined 2549 value. 2550 2551 cPP Pointer to pointer to string beginning with the first 2552 character of the supposed operand. 2553 2554 prefixp Pointer to structure containing an optional instruction 2555 prefix. 2556 2557 is_autoincp Pointer to int indicating the indirect or autoincrement 2558 bits. 2559 2560 src_regnop Pointer to int containing the source register number in 2561 the instruction. 2562 2563 imm_foundp Pointer to an int indicating if an immediate expression 2564 is found. 2565 2566 imm_exprP Pointer to a structure containing an immediate 2567 expression, if success and if *imm_foundp is nonzero. 2568 2569 Return 1 iff a correct indirect operand is found. */ 2570 2571static int 2572get_autoinc_prefix_or_indir_op (char **cPP, struct cris_prefix *prefixp, 2573 int *is_autoincp, int *src_regnop, 2574 int *imm_foundp, expressionS *imm_exprP) 2575{ 2576 /* Assume there was no immediate mode expression. */ 2577 *imm_foundp = 0; 2578 2579 if (**cPP == '[') 2580 { 2581 /* So this operand is one of: 2582 Indirect: [rN] 2583 Autoincrement: [rN+] 2584 Indexed with assign: [rN=rM+rO.S] 2585 Offset with assign: [rN=rM+I], [rN=rM+[rO].s], [rN=rM+[rO+].s] 2586 2587 Either way, consume the '['. */ 2588 (*cPP)++; 2589 2590 /* Get the rN register. */ 2591 if (! get_gen_reg (cPP, src_regnop)) 2592 /* If there was no register, then this cannot match. */ 2593 return 0; 2594 else 2595 { 2596 /* We got the register, now check the next character. */ 2597 switch (**cPP) 2598 { 2599 case ']': 2600 /* Indirect mode. We're done here. */ 2601 prefixp->kind = PREFIX_NONE; 2602 *is_autoincp = 0; 2603 break; 2604 2605 case '+': 2606 /* This must be an auto-increment mode, if there's a 2607 match. */ 2608 prefixp->kind = PREFIX_NONE; 2609 *is_autoincp = 1; 2610 2611 /* We consume this character and break out to check the 2612 closing ']'. */ 2613 (*cPP)++; 2614 break; 2615 2616 case '=': 2617 /* This must be indexed with assign, or offset with assign 2618 to match. Not supported for crisv32 or in 2619 compatibility mode. */ 2620 if (cris_arch == arch_crisv32 2621 || cris_arch == arch_cris_common_v10_v32) 2622 return 0; 2623 2624 (*cPP)++; 2625 2626 /* Either way, the next thing must be a register. */ 2627 if (! get_gen_reg (cPP, &prefixp->base_reg_number)) 2628 /* No register, no match. */ 2629 return 0; 2630 else 2631 { 2632 /* We've consumed "[rN=rM", so we must be looking at 2633 "+rO.s]" or "+I]", or "-I]", or "+[rO].s]" or 2634 "+[rO+].s]". */ 2635 if (**cPP == '+') 2636 { 2637 int index_reg_number; 2638 (*cPP)++; 2639 2640 if (**cPP == '[') 2641 { 2642 int size_bits; 2643 /* This must be [rx=ry+[rz].s] or 2644 [rx=ry+[rz+].s] or no match. We must be 2645 looking at rz after consuming the '['. */ 2646 (*cPP)++; 2647 2648 if (!get_gen_reg (cPP, &index_reg_number)) 2649 return 0; 2650 2651 prefixp->kind = PREFIX_BDAP; 2652 prefixp->opcode 2653 = (BDAP_INDIR_OPCODE 2654 + (prefixp->base_reg_number << 12) 2655 + index_reg_number); 2656 2657 if (**cPP == '+') 2658 { 2659 /* We've seen "[rx=ry+[rz+" here, so now we 2660 know that there must be "].s]" left to 2661 check. */ 2662 (*cPP)++; 2663 prefixp->opcode |= AUTOINCR_BIT << 8; 2664 } 2665 2666 /* If it wasn't autoincrement, we don't need to 2667 add anything. */ 2668 2669 /* Check the next-to-last ']'. */ 2670 if (**cPP != ']') 2671 return 0; 2672 2673 (*cPP)++; 2674 2675 /* Check the ".s" modifier. */ 2676 if (! get_bwd_size_modifier (cPP, &size_bits)) 2677 return 0; 2678 2679 prefixp->opcode |= size_bits << 4; 2680 2681 /* Now we got [rx=ry+[rz+].s or [rx=ry+[rz].s. 2682 We break out to check the final ']'. */ 2683 break; 2684 } 2685 /* It wasn't an indirection. Check if it's a 2686 register. */ 2687 else if (get_gen_reg (cPP, &index_reg_number)) 2688 { 2689 int size_bits; 2690 2691 /* Indexed with assign mode: "[rN+rM.S]". */ 2692 prefixp->kind = PREFIX_BIAP; 2693 prefixp->opcode 2694 = (BIAP_OPCODE + (index_reg_number << 12) 2695 + prefixp->base_reg_number /* << 0 */); 2696 2697 if (! get_bwd_size_modifier (cPP, &size_bits)) 2698 /* Size missing, this isn't a match. */ 2699 return 0; 2700 else 2701 { 2702 /* Size found, break out to check the 2703 final ']'. */ 2704 prefixp->opcode |= size_bits << 4; 2705 break; 2706 } 2707 } 2708 /* Not a register. Then this must be "[rN+I]". */ 2709 else if (cris_get_expression (cPP, &prefixp->expr)) 2710 { 2711 /* We've got offset with assign mode. Fill 2712 in the blanks and break out to match the 2713 final ']'. */ 2714 prefixp->kind = PREFIX_BDAP_IMM; 2715 2716 /* We tentatively put an opcode corresponding to 2717 a 32-bit operand here, although it may be 2718 relaxed when there's no PIC specifier for the 2719 operand. */ 2720 prefixp->opcode 2721 = (BDAP_INDIR_OPCODE 2722 | (prefixp->base_reg_number << 12) 2723 | (AUTOINCR_BIT << 8) 2724 | (2 << 4) 2725 | REG_PC /* << 0 */); 2726 2727 /* This can have a PIC suffix, specifying reloc 2728 type to use. */ 2729 if (pic && **cPP == PIC_SUFFIX_CHAR) 2730 { 2731 unsigned int relocsize; 2732 2733 cris_get_pic_suffix (cPP, &prefixp->reloc, 2734 &prefixp->expr); 2735 2736 /* Tweak the size of the immediate operand 2737 in the prefix opcode if it isn't what we 2738 set. */ 2739 relocsize 2740 = cris_get_pic_reloc_size (prefixp->reloc); 2741 if (relocsize != 4) 2742 prefixp->opcode 2743 = ((prefixp->opcode & ~(3 << 4)) 2744 | ((relocsize >> 1) << 4)); 2745 } 2746 break; 2747 } 2748 else 2749 /* Neither register nor expression found, so 2750 this can't be a match. */ 2751 return 0; 2752 } 2753 /* Not "[rN+" but perhaps "[rN-"? */ 2754 else if (**cPP == '-') 2755 { 2756 /* We must have an offset with assign mode. */ 2757 if (! cris_get_expression (cPP, &prefixp->expr)) 2758 /* No expression, no match. */ 2759 return 0; 2760 else 2761 { 2762 /* We've got offset with assign mode. Fill 2763 in the blanks and break out to match the 2764 final ']'. 2765 2766 Note that we don't allow a PIC suffix for an 2767 operand with a minus sign. */ 2768 prefixp->kind = PREFIX_BDAP_IMM; 2769 break; 2770 } 2771 } 2772 else 2773 /* Neither '+' nor '-' after "[rN=rM". Lose. */ 2774 return 0; 2775 } 2776 default: 2777 /* Neither ']' nor '+' nor '=' after "[rN". Lose. */ 2778 return 0; 2779 } 2780 } 2781 2782 /* When we get here, we have a match and will just check the closing 2783 ']'. We can still fail though. */ 2784 if (**cPP != ']') 2785 return 0; 2786 else 2787 { 2788 /* Don't forget to consume the final ']'. 2789 Then return in glory. */ 2790 (*cPP)++; 2791 return 1; 2792 } 2793 } 2794 /* No indirection. Perhaps a constant? */ 2795 else if (cris_get_expression (cPP, imm_exprP)) 2796 { 2797 /* Expression found, this is immediate mode. */ 2798 prefixp->kind = PREFIX_NONE; 2799 *is_autoincp = 1; 2800 *src_regnop = REG_PC; 2801 *imm_foundp = 1; 2802 2803 /* This can have a PIC suffix, specifying reloc type to use. The 2804 caller must check that the reloc size matches the operand size. */ 2805 if (pic && **cPP == PIC_SUFFIX_CHAR) 2806 cris_get_pic_suffix (cPP, &prefixp->reloc, imm_exprP); 2807 2808 return 1; 2809 } 2810 2811 /* No luck today. */ 2812 return 0; 2813} 2814 2815/* This function gets an indirect operand in a three-address operand 2816 combination from the string pointed out by *cPP. The pointer *cPP is 2817 advanced to the character following the indirect operand on success, or 2818 has an unspecified value on failure. 2819 2820 cPP Pointer to pointer to string beginning 2821 with the operand 2822 2823 prefixp Pointer to structure containing an 2824 instruction prefix 2825 2826 Returns 1 iff a correct indirect operand is found. */ 2827 2828static int 2829get_3op_or_dip_prefix_op (char **cPP, struct cris_prefix *prefixp) 2830{ 2831 int reg_number; 2832 2833 if (**cPP != '[') 2834 /* We must have a '[' or it's a clean failure. */ 2835 return 0; 2836 2837 /* Eat the first '['. */ 2838 (*cPP)++; 2839 2840 if (**cPP == '[') 2841 { 2842 /* A second '[', so this must be double-indirect mode. */ 2843 (*cPP)++; 2844 prefixp->kind = PREFIX_DIP; 2845 prefixp->opcode = DIP_OPCODE; 2846 2847 /* Get the register or fail entirely. */ 2848 if (! get_gen_reg (cPP, ®_number)) 2849 return 0; 2850 else 2851 { 2852 prefixp->opcode |= reg_number /* << 0 */ ; 2853 if (**cPP == '+') 2854 { 2855 /* Since we found a '+', this must be double-indirect 2856 autoincrement mode. */ 2857 (*cPP)++; 2858 prefixp->opcode |= AUTOINCR_BIT << 8; 2859 } 2860 2861 /* There's nothing particular to do, if this was a 2862 double-indirect *without* autoincrement. */ 2863 } 2864 2865 /* Check the first ']'. The second one is checked at the end. */ 2866 if (**cPP != ']') 2867 return 0; 2868 2869 /* Eat the first ']', so we'll be looking at a second ']'. */ 2870 (*cPP)++; 2871 } 2872 /* No second '['. Then we should have a register here, making 2873 it "[rN". */ 2874 else if (get_gen_reg (cPP, &prefixp->base_reg_number)) 2875 { 2876 /* This must be indexed or offset mode: "[rN+I]" or 2877 "[rN+rM.S]" or "[rN+[rM].S]" or "[rN+[rM+].S]". */ 2878 if (**cPP == '+') 2879 { 2880 int index_reg_number; 2881 2882 (*cPP)++; 2883 2884 if (**cPP == '[') 2885 { 2886 /* This is "[rx+["... Expect a register next. */ 2887 int size_bits; 2888 (*cPP)++; 2889 2890 if (!get_gen_reg (cPP, &index_reg_number)) 2891 return 0; 2892 2893 prefixp->kind = PREFIX_BDAP; 2894 prefixp->opcode 2895 = (BDAP_INDIR_OPCODE 2896 + (prefixp->base_reg_number << 12) 2897 + index_reg_number); 2898 2899 /* We've seen "[rx+[ry", so check if this is 2900 autoincrement. */ 2901 if (**cPP == '+') 2902 { 2903 /* Yep, now at "[rx+[ry+". */ 2904 (*cPP)++; 2905 prefixp->opcode |= AUTOINCR_BIT << 8; 2906 } 2907 /* If it wasn't autoincrement, we don't need to 2908 add anything. */ 2909 2910 /* Check a first closing ']': "[rx+[ry]" or 2911 "[rx+[ry+]". */ 2912 if (**cPP != ']') 2913 return 0; 2914 (*cPP)++; 2915 2916 /* Now expect a size modifier ".S". */ 2917 if (! get_bwd_size_modifier (cPP, &size_bits)) 2918 return 0; 2919 2920 prefixp->opcode |= size_bits << 4; 2921 2922 /* Ok, all interesting stuff has been seen: 2923 "[rx+[ry+].S" or "[rx+[ry].S". We only need to 2924 expect a final ']', which we'll do in a common 2925 closing session. */ 2926 } 2927 /* Seen "[rN+", but not a '[', so check if we have a 2928 register. */ 2929 else if (get_gen_reg (cPP, &index_reg_number)) 2930 { 2931 /* This is indexed mode: "[rN+rM.S]" or 2932 "[rN+rM.S+]". */ 2933 int size_bits; 2934 prefixp->kind = PREFIX_BIAP; 2935 prefixp->opcode 2936 = (BIAP_OPCODE 2937 | prefixp->base_reg_number /* << 0 */ 2938 | (index_reg_number << 12)); 2939 2940 /* Consume the ".S". */ 2941 if (! get_bwd_size_modifier (cPP, &size_bits)) 2942 /* Missing size, so fail. */ 2943 return 0; 2944 else 2945 /* Size found. Add that piece and drop down to 2946 the common checking of the closing ']'. */ 2947 prefixp->opcode |= size_bits << 4; 2948 } 2949 /* Seen "[rN+", but not a '[' or a register, so then 2950 it must be a constant "I". 2951 2952 As a quality of implementation improvement, we check for a 2953 closing ']', like in an erroneous "[rN+]". If we don't, 2954 the expression parser will emit a confusing "bad 2955 expression" when it sees the ']', probably because it 2956 doesn't like seeing no expression. */ 2957 else if (**cPP != ']' && cris_get_expression (cPP, &prefixp->expr)) 2958 { 2959 /* Expression found, so fill in the bits of offset 2960 mode and drop down to check the closing ']'. */ 2961 prefixp->kind = PREFIX_BDAP_IMM; 2962 2963 /* We tentatively put an opcode corresponding to a 32-bit 2964 operand here, although it may be relaxed when there's no 2965 PIC specifier for the operand. */ 2966 prefixp->opcode 2967 = (BDAP_INDIR_OPCODE 2968 | (prefixp->base_reg_number << 12) 2969 | (AUTOINCR_BIT << 8) 2970 | (2 << 4) 2971 | REG_PC /* << 0 */); 2972 2973 /* This can have a PIC suffix, specifying reloc type to use. */ 2974 if (pic && **cPP == PIC_SUFFIX_CHAR) 2975 { 2976 unsigned int relocsize; 2977 2978 cris_get_pic_suffix (cPP, &prefixp->reloc, &prefixp->expr); 2979 2980 /* Tweak the size of the immediate operand in the prefix 2981 opcode if it isn't what we set. */ 2982 relocsize = cris_get_pic_reloc_size (prefixp->reloc); 2983 if (relocsize != 4) 2984 prefixp->opcode 2985 = ((prefixp->opcode & ~(3 << 4)) 2986 | ((relocsize >> 1) << 4)); 2987 } 2988 } 2989 else 2990 /* Nothing valid here: lose. */ 2991 return 0; 2992 } 2993 /* Seen "[rN" but no '+', so check if it's a '-'. */ 2994 else if (**cPP == '-') 2995 { 2996 /* Yep, we must have offset mode. */ 2997 if (! cris_get_expression (cPP, &prefixp->expr)) 2998 /* No expression, so we lose. */ 2999 return 0; 3000 else 3001 { 3002 /* Expression found to make this offset mode, so 3003 fill those bits and drop down to check the 3004 closing ']'. 3005 3006 Note that we don't allow a PIC suffix for 3007 an operand with a minus sign like this. */ 3008 prefixp->kind = PREFIX_BDAP_IMM; 3009 } 3010 } 3011 else 3012 { 3013 /* We've seen "[rN", but not '+' or '-'; rather a ']'. 3014 Hmm. Normally this is a simple indirect mode that we 3015 shouldn't match, but if we expect ']', then we have a 3016 zero offset, so it can be a three-address-operand, 3017 like "[rN],rO,rP", thus offset mode. 3018 3019 Don't eat the ']', that will be done in the closing 3020 ceremony. */ 3021 prefixp->expr.X_op = O_constant; 3022 prefixp->expr.X_add_number = 0; 3023 prefixp->expr.X_add_symbol = NULL; 3024 prefixp->expr.X_op_symbol = NULL; 3025 prefixp->kind = PREFIX_BDAP_IMM; 3026 } 3027 } 3028 /* A '[', but no second '[', and no register. Check if we 3029 have an expression, making this "[I]" for a double-indirect 3030 prefix. */ 3031 else if (cris_get_expression (cPP, &prefixp->expr)) 3032 { 3033 /* Expression found, the so called absolute mode for a 3034 double-indirect prefix on PC. */ 3035 prefixp->kind = PREFIX_DIP; 3036 prefixp->opcode = DIP_OPCODE | (AUTOINCR_BIT << 8) | REG_PC; 3037 prefixp->reloc = BFD_RELOC_32; 3038 } 3039 else 3040 /* Neither '[' nor register nor expression. We lose. */ 3041 return 0; 3042 3043 /* We get here as a closing ceremony to a successful match. We just 3044 need to check the closing ']'. */ 3045 if (**cPP != ']') 3046 /* Oops. Close but no air-polluter. */ 3047 return 0; 3048 3049 /* Don't forget to consume that ']', before returning in glory. */ 3050 (*cPP)++; 3051 return 1; 3052} 3053 3054/* Get an expression from the string pointed out by *cPP. 3055 The pointer *cPP is advanced to the character following the expression 3056 on a success, or retains its original value otherwise. 3057 3058 cPP Pointer to pointer to string beginning with the expression. 3059 3060 exprP Pointer to structure containing the expression. 3061 3062 Return 1 iff a correct expression is found. */ 3063 3064static int 3065cris_get_expression (char **cPP, expressionS *exprP) 3066{ 3067 char *saved_input_line_pointer; 3068 segT exp; 3069 3070 /* The "expression" function expects to find an expression at the 3071 global variable input_line_pointer, so we have to save it to give 3072 the impression that we don't fiddle with global variables. */ 3073 saved_input_line_pointer = input_line_pointer; 3074 input_line_pointer = *cPP; 3075 3076 /* Avoid a common error, confusing addressing modes. Beware that the 3077 call to expression below does not signal that error; it treats [] 3078 as parentheses, unless #define NEED_INDEX_OPERATOR in which case it 3079 gives them other confusing semantics rather than plain outlawing 3080 them, which is what we want. */ 3081 if (*input_line_pointer == '[') 3082 { 3083 input_line_pointer = saved_input_line_pointer; 3084 return 0; 3085 } 3086 3087 exp = expression (exprP); 3088 if (exprP->X_op == O_illegal || exprP->X_op == O_absent) 3089 { 3090 input_line_pointer = saved_input_line_pointer; 3091 return 0; 3092 } 3093 3094 /* Everything seems to be fine, just restore the global 3095 input_line_pointer and say we're successful. */ 3096 *cPP = input_line_pointer; 3097 input_line_pointer = saved_input_line_pointer; 3098 return 1; 3099} 3100 3101/* Get a sequence of flag characters from *spp. The pointer *cPP is 3102 advanced to the character following the expression. The flag 3103 characters are consecutive, no commas or spaces. 3104 3105 cPP Pointer to pointer to string beginning with the expression. 3106 3107 flagp Pointer to int to return the flags expression. 3108 3109 Return 1 iff a correct flags expression is found. */ 3110 3111static int 3112get_flags (char **cPP, int *flagsp) 3113{ 3114 for (;;) 3115 { 3116 switch (**cPP) 3117 { 3118 case 'd': 3119 case 'D': 3120 if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3, 3121 cris_arch)) 3122 return 0; 3123 *flagsp |= 0x80; 3124 break; 3125 3126 case 'm': 3127 case 'M': 3128 if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10, 3129 cris_arch)) 3130 return 0; 3131 *flagsp |= 0x80; 3132 break; 3133 3134 case 'e': 3135 case 'E': 3136 if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3, 3137 cris_arch)) 3138 return 0; 3139 *flagsp |= 0x40; 3140 break; 3141 3142 case 'b': 3143 case 'B': 3144 if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10, 3145 cris_arch)) 3146 return 0; 3147 *flagsp |= 0x40; 3148 break; 3149 3150 case 'p': 3151 case 'P': 3152 if (! cris_insn_ver_valid_for_arch (cris_ver_v32p, 3153 cris_arch)) 3154 return 0; 3155 *flagsp |= 0x80; 3156 break; 3157 3158 case 'u': 3159 case 'U': 3160 if (! cris_insn_ver_valid_for_arch (cris_ver_v32p, 3161 cris_arch)) 3162 return 0; 3163 *flagsp |= 0x40; 3164 break; 3165 3166 case 'i': 3167 case 'I': 3168 *flagsp |= 0x20; 3169 break; 3170 3171 case 'x': 3172 case 'X': 3173 *flagsp |= 0x10; 3174 break; 3175 3176 case 'n': 3177 case 'N': 3178 *flagsp |= 0x8; 3179 break; 3180 3181 case 'z': 3182 case 'Z': 3183 *flagsp |= 0x4; 3184 break; 3185 3186 case 'v': 3187 case 'V': 3188 *flagsp |= 0x2; 3189 break; 3190 3191 case 'c': 3192 case 'C': 3193 *flagsp |= 1; 3194 break; 3195 3196 default: 3197 /* We consider this successful if we stop at a comma or 3198 whitespace. Anything else, and we consider it a failure. */ 3199 if (**cPP != ',' 3200 && **cPP != 0 3201 && ! ISSPACE (**cPP)) 3202 return 0; 3203 else 3204 return 1; 3205 } 3206 3207 /* Don't forget to consume each flag character. */ 3208 (*cPP)++; 3209 } 3210} 3211 3212/* Generate code and fixes for a BDAP prefix. 3213 For v32, this handles ADDOQ because thankfully the opcodes are the 3214 same. 3215 3216 base_regno Int containing the base register number. 3217 3218 exprP Pointer to structure containing the offset expression. */ 3219 3220static void 3221gen_bdap (int base_regno, expressionS *exprP) 3222{ 3223 unsigned int opcode; 3224 char *opcodep; 3225 3226 /* Put out the prefix opcode; assume quick immediate mode at first. */ 3227 opcode = BDAP_QUICK_OPCODE | (base_regno << 12); 3228 opcodep = cris_insn_first_word_frag (); 3229 md_number_to_chars (opcodep, opcode, 2); 3230 3231 if (exprP->X_op == O_constant) 3232 { 3233 /* We have an absolute expression that we know the size of right 3234 now. */ 3235 long int value; 3236 int size; 3237 3238 value = exprP->X_add_number; 3239 if (value < -32768 || value > 32767) 3240 /* Outside range for a "word", make it a dword. */ 3241 size = 2; 3242 else 3243 /* Assume "word" size. */ 3244 size = 1; 3245 3246 /* If this is a signed-byte value, we can fit it into the prefix 3247 insn itself. */ 3248 if (value >= -128 && value <= 127) 3249 opcodep[0] = value; 3250 else 3251 { 3252 /* This is a word or dword displacement, which will be put in a 3253 word or dword after the prefix. */ 3254 char *p; 3255 3256 opcodep[0] = BDAP_PC_LOW + (size << 4); 3257 opcodep[1] &= 0xF0; 3258 opcodep[1] |= BDAP_INCR_HIGH; 3259 p = frag_more (1 << size); 3260 md_number_to_chars (p, value, 1 << size); 3261 } 3262 } 3263 else 3264 { 3265 /* Handle complex expressions. */ 3266 valueT addvalue 3267 = SIMPLE_EXPR (exprP) ? exprP->X_add_number : 0; 3268 symbolS *sym 3269 = (SIMPLE_EXPR (exprP) 3270 ? exprP->X_add_symbol : make_expr_symbol (exprP)); 3271 3272 /* The expression is not defined yet but may become absolute. We 3273 make it a relocation to be relaxed. */ 3274 frag_var (rs_machine_dependent, 4, 0, 3275 ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF), 3276 sym, addvalue, opcodep); 3277 } 3278} 3279 3280/* Encode a branch displacement in the range -256..254 into the form used 3281 by CRIS conditional branch instructions. 3282 3283 offset The displacement value in bytes. */ 3284 3285static int 3286branch_disp (int offset) 3287{ 3288 int disp; 3289 3290 /* Adjust all short branch offsets here. */ 3291 if (cris_arch == arch_crisv32 || cris_arch == arch_cris_common_v10_v32) 3292 offset += 2; 3293 3294 disp = offset & 0xFE; 3295 3296 if (offset < 0) 3297 disp |= 1; 3298 3299 return disp; 3300} 3301 3302/* Generate code and fixes for a 32-bit conditional branch instruction 3303 created by "extending" an existing 8-bit branch instruction. 3304 3305 opcodep Pointer to the word containing the original 8-bit branch 3306 instruction. 3307 3308 writep Pointer to "extension area" following the first instruction 3309 word. 3310 3311 fragP Pointer to the frag containing the instruction. 3312 3313 add_symP, Parts of the destination address expression. 3314 sub_symP, 3315 add_num. */ 3316 3317static void 3318gen_cond_branch_32 (char *opcodep, char *writep, fragS *fragP, 3319 symbolS *add_symP, symbolS *sub_symP, long int add_num) 3320{ 3321 int nop_opcode; 3322 int opc_offset; 3323 int branch_offset; 3324 3325 if (cris_arch == arch_crisv32) 3326 { 3327 nop_opcode = NOP_OPCODE_V32; 3328 opc_offset = 10; 3329 branch_offset = -2 - 8; 3330 } 3331 else if (pic) 3332 { 3333 nop_opcode = NOP_OPCODE; 3334 opc_offset = 10; 3335 branch_offset = -2 - 8; 3336 } 3337 else 3338 { 3339 nop_opcode = NOP_OPCODE; 3340 opc_offset = 8; 3341 branch_offset = -2 - 6; 3342 } 3343 3344 /* We should never get here for compatibility mode. */ 3345 if (cris_arch == arch_cris_common_v10_v32) 3346 as_fatal (_("Calling gen_cond_branch_32 for .arch common_v10_v32\n")); 3347 3348 if (warn_for_branch_expansion) 3349 as_warn_where (fragP->fr_file, fragP->fr_line, 3350 _("32-bit conditional branch generated")); 3351 3352 /* Here, writep points to what will be opcodep + 2. First, we change 3353 the actual branch in opcodep[0] and opcodep[1], so that in the 3354 final insn, it will look like: 3355 opcodep+10: Bcc .-6 3356 3357 This means we don't have to worry about changing the opcode or 3358 messing with the delay-slot instruction. So, we move it to last in 3359 the "extended" branch, and just change the displacement. Admittedly, 3360 it's not the optimal extended construct, but we should get this 3361 rarely enough that it shouldn't matter. */ 3362 3363 writep[opc_offset] = branch_disp (branch_offset); 3364 writep[opc_offset + 1] = opcodep[1]; 3365 3366 /* Then, we change the branch to an unconditional branch over the 3367 extended part, to the new location of the Bcc: 3368 opcodep: BA .+10 3369 opcodep+2: NOP 3370 3371 Note that these two writes are to currently different locations, 3372 merged later. */ 3373 3374 md_number_to_chars (opcodep, BA_QUICK_OPCODE 3375 + (cris_arch == arch_crisv32 ? 12 : (pic ? 10 : 8)), 3376 2); 3377 md_number_to_chars (writep, nop_opcode, 2); 3378 3379 /* Then the extended thing, the 32-bit jump insn. 3380 opcodep+4: JUMP [PC+] 3381 or, in the PIC case, 3382 opcodep+4: MOVE [PC=PC+N],P0. */ 3383 3384 md_number_to_chars (writep + 2, 3385 cris_arch == arch_crisv32 3386 ? BA_DWORD_OPCODE 3387 : (pic ? MOVE_PC_INCR_OPCODE_PREFIX 3388 : JUMP_PC_INCR_OPCODE), 2); 3389 3390 /* We have to fill in the actual value too. 3391 opcodep+6: .DWORD 3392 This is most probably an expression, but we can cope with an absolute 3393 value too. FIXME: Testcase needed with and without pic. */ 3394 3395 if (add_symP == NULL && sub_symP == NULL) 3396 { 3397 /* An absolute address. */ 3398 if (pic || cris_arch == arch_crisv32) 3399 fix_new (fragP, writep + 4 - fragP->fr_literal, 4, 3400 section_symbol (absolute_section), 3401 add_num 3402 + (cris_arch == arch_crisv32 ? 6 : 0), 3403 1, BFD_RELOC_32_PCREL); 3404 else 3405 md_number_to_chars (writep + 4, add_num, 4); 3406 } 3407 else 3408 { 3409 if (sub_symP != NULL) 3410 as_bad_where (fragP->fr_file, fragP->fr_line, 3411 _("Complex expression not supported")); 3412 3413 /* Not absolute, we have to make it a frag for later evaluation. */ 3414 fix_new (fragP, writep + 4 - fragP->fr_literal, 4, add_symP, 3415 add_num + (cris_arch == arch_crisv32 ? 6 : 0), 3416 pic || cris_arch == arch_crisv32 ? 1 : 0, 3417 pic || cris_arch == arch_crisv32 3418 ? BFD_RELOC_32_PCREL : BFD_RELOC_32); 3419 } 3420 3421 if (cris_arch == arch_crisv32) 3422 /* Follow it with a "NOP" for CRISv32. */ 3423 md_number_to_chars (writep + 8, NOP_OPCODE_V32, 2); 3424 else if (pic) 3425 /* ...and the rest of the move-opcode for pre-v32 PIC. */ 3426 md_number_to_chars (writep + 8, MOVE_PC_INCR_OPCODE_SUFFIX, 2); 3427} 3428 3429/* Get the size of an immediate-reloc in bytes. Only valid for PIC 3430 relocs. */ 3431 3432static unsigned int 3433cris_get_pic_reloc_size (bfd_reloc_code_real_type reloc) 3434{ 3435 return reloc == BFD_RELOC_CRIS_16_GOTPLT || reloc == BFD_RELOC_CRIS_16_GOT 3436 ? 2 : 4; 3437} 3438 3439/* Store a reloc type at *RELOCP corresponding to the PIC suffix at *CPP. 3440 Adjust *EXPRP with any addend found after the PIC suffix. */ 3441 3442static void 3443cris_get_pic_suffix (char **cPP, bfd_reloc_code_real_type *relocp, 3444 expressionS *exprP) 3445{ 3446 char *s = *cPP; 3447 unsigned int i; 3448 expressionS const_expr; 3449 3450 const struct pic_suffixes_struct 3451 { 3452 const char *const suffix; 3453 unsigned int len; 3454 bfd_reloc_code_real_type reloc; 3455 } pic_suffixes[] = 3456 { 3457#undef PICMAP 3458#define PICMAP(s, r) {s, sizeof (s) - 1, r} 3459 /* Keep this in order with longest unambiguous prefix first. */ 3460 PICMAP ("GOTPLT16", BFD_RELOC_CRIS_16_GOTPLT), 3461 PICMAP ("GOTPLT", BFD_RELOC_CRIS_32_GOTPLT), 3462 PICMAP ("PLTG", BFD_RELOC_CRIS_32_PLT_GOTREL), 3463 PICMAP ("PLT", BFD_RELOC_CRIS_32_PLT_PCREL), 3464 PICMAP ("GOTOFF", BFD_RELOC_CRIS_32_GOTREL), 3465 PICMAP ("GOT16", BFD_RELOC_CRIS_16_GOT), 3466 PICMAP ("GOT", BFD_RELOC_CRIS_32_GOT) 3467 }; 3468 3469 /* We've already seen the ':', so consume it. */ 3470 s++; 3471 3472 for (i = 0; i < sizeof (pic_suffixes)/sizeof (pic_suffixes[0]); i++) 3473 { 3474 if (strncmp (s, pic_suffixes[i].suffix, pic_suffixes[i].len) == 0 3475 && ! is_part_of_name (s[pic_suffixes[i].len])) 3476 { 3477 /* We have a match. Consume the suffix and set the relocation 3478 type. */ 3479 s += pic_suffixes[i].len; 3480 3481 /* There can be a constant term appended. If so, we will add it 3482 to *EXPRP. */ 3483 if (*s == '+' || *s == '-') 3484 { 3485 if (! cris_get_expression (&s, &const_expr)) 3486 /* There was some kind of syntax error. Bail out. */ 3487 break; 3488 3489 /* Allow complex expressions as the constant part. It still 3490 has to be an assembly-time constant or there will be an 3491 error emitting the reloc. This makes the PIC qualifiers 3492 idempotent; foo:GOTOFF+32 == foo+32:GOTOFF. The former we 3493 recognize here; the latter is parsed in the incoming 3494 expression. */ 3495 exprP->X_add_symbol = make_expr_symbol (exprP); 3496 exprP->X_op = O_add; 3497 exprP->X_add_number = 0; 3498 exprP->X_op_symbol = make_expr_symbol (&const_expr); 3499 } 3500 3501 *relocp = pic_suffixes[i].reloc; 3502 *cPP = s; 3503 return; 3504 } 3505 } 3506 3507 /* No match. Don't consume anything; fall back and there will be a 3508 syntax error. */ 3509} 3510 3511/* This *could* have been: 3512 3513 Turn a string in input_line_pointer into a floating point constant 3514 of type TYPE, and store the appropriate bytes in *LITP. The number 3515 of LITTLENUMS emitted is stored in *SIZEP. 3516 3517 type A character from FLTCHARS that describes what kind of 3518 floating-point number is wanted. 3519 3520 litp A pointer to an array that the result should be stored in. 3521 3522 sizep A pointer to an integer where the size of the result is stored. 3523 3524 But we don't support floating point constants in assembly code *at all*, 3525 since it's suboptimal and just opens up bug opportunities. GCC emits 3526 the bit patterns as hex. All we could do here is to emit what GCC 3527 would have done in the first place. *Nobody* writes floating-point 3528 code as assembly code, but if they do, they should be able enough to 3529 find out the correct bit patterns and use them. */ 3530 3531char * 3532md_atof (int type ATTRIBUTE_UNUSED, char *litp ATTRIBUTE_UNUSED, 3533 int *sizep ATTRIBUTE_UNUSED) 3534{ 3535 /* FIXME: Is this function mentioned in the internals.texi manual? If 3536 not, add it. */ 3537 return _("Bad call to md_atof () - floating point formats are not supported"); 3538} 3539 3540/* Turn a number as a fixS * into a series of bytes that represents the 3541 number on the target machine. The purpose of this procedure is the 3542 same as that of md_number_to_chars but this procedure is supposed to 3543 handle general bit field fixes and machine-dependent fixups. 3544 3545 bufp Pointer to an array where the result should be stored. 3546 3547 val The value to store. 3548 3549 n The number of bytes in "val" that should be stored. 3550 3551 fixP The fix to be applied to the bit field starting at bufp. 3552 3553 seg The segment containing this number. */ 3554 3555static void 3556cris_number_to_imm (char *bufp, long val, int n, fixS *fixP, segT seg) 3557{ 3558 segT sym_seg; 3559 3560 know (n <= 4); 3561 know (fixP); 3562 3563 /* We put the relative "vma" for the other segment for inter-segment 3564 relocations in the object data to stay binary "compatible" (with an 3565 uninteresting old version) for the relocation. 3566 Maybe delete some day. */ 3567 if (fixP->fx_addsy 3568 && (sym_seg = S_GET_SEGMENT (fixP->fx_addsy)) != seg) 3569 val += sym_seg->vma; 3570 3571 if (fixP->fx_addsy != NULL || fixP->fx_pcrel) 3572 switch (fixP->fx_r_type) 3573 { 3574 /* These must be fully resolved when getting here. */ 3575 case BFD_RELOC_16_PCREL: 3576 case BFD_RELOC_8_PCREL: 3577 as_bad_where (fixP->fx_file, fixP->fx_line, 3578 _("PC-relative relocation must be trivially resolved")); 3579 default: 3580 ; 3581 } 3582 3583 /* Only do this for old-arch binaries. */ 3584 if (cris_arch != arch_cris_any_v0_v10 3585 && (fixP->fx_addsy != NULL || fixP->fx_pcrel)) 3586 return; 3587 3588 switch (fixP->fx_r_type) 3589 { 3590 /* Ditto here, we put the addend into the object code as 3591 well as the reloc addend. Keep it that way for now, to simplify 3592 regression tests on the object file contents. FIXME: Seems 3593 uninteresting now that we have a test suite. */ 3594 3595 case BFD_RELOC_CRIS_16_GOT: 3596 case BFD_RELOC_CRIS_32_GOT: 3597 case BFD_RELOC_CRIS_32_GOTREL: 3598 case BFD_RELOC_CRIS_16_GOTPLT: 3599 case BFD_RELOC_CRIS_32_GOTPLT: 3600 case BFD_RELOC_CRIS_32_PLT_GOTREL: 3601 case BFD_RELOC_CRIS_32_PLT_PCREL: 3602 /* We don't want to put in any kind of non-zero bits in the data 3603 being relocated for these. */ 3604 break; 3605 3606 case BFD_RELOC_32_PCREL: 3607 /* If this one isn't fully resolved, we don't want to put anything 3608 in the object. */ 3609 if (fixP->fx_addsy != NULL || fixP->fx_pcrel) 3610 break; 3611 3612 /* Fall through. */ 3613 case BFD_RELOC_32: 3614 /* No use having warnings here, since most hosts have a 32-bit type 3615 for "long" (which will probably change soon, now that I wrote 3616 this). */ 3617 bufp[3] = (val >> 24) & 0xFF; 3618 bufp[2] = (val >> 16) & 0xFF; 3619 bufp[1] = (val >> 8) & 0xFF; 3620 bufp[0] = val & 0xFF; 3621 break; 3622 3623 /* FIXME: The 16 and 8-bit cases should have a way to check 3624 whether a signed or unsigned (or any signedness) number is 3625 accepted. */ 3626 3627 case BFD_RELOC_16: 3628 case BFD_RELOC_16_PCREL: 3629 if (val > 0xffff || val < -32768) 3630 as_bad_where (fixP->fx_file, fixP->fx_line, 3631 _("Value not in 16 bit range: %ld"), val); 3632 if (! fixP->fx_addsy) 3633 { 3634 bufp[1] = (val >> 8) & 0xFF; 3635 bufp[0] = val & 0xFF; 3636 } 3637 break; 3638 3639 case BFD_RELOC_CRIS_SIGNED_16: 3640 if (val > 32767 || val < -32768) 3641 as_bad_where (fixP->fx_file, fixP->fx_line, 3642 _("Value not in 16 bit signed range: %ld"), val); 3643 if (! fixP->fx_addsy) 3644 { 3645 bufp[1] = (val >> 8) & 0xFF; 3646 bufp[0] = val & 0xFF; 3647 } 3648 break; 3649 3650 case BFD_RELOC_8: 3651 case BFD_RELOC_8_PCREL: 3652 if (val > 255 || val < -128) 3653 as_bad_where (fixP->fx_file, fixP->fx_line, _("Value not in 8 bit range: %ld"), val); 3654 if (! fixP->fx_addsy) 3655 bufp[0] = val & 0xFF; 3656 break; 3657 3658 case BFD_RELOC_CRIS_SIGNED_8: 3659 if (val > 127 || val < -128) 3660 as_bad_where (fixP->fx_file, fixP->fx_line, 3661 _("Value not in 8 bit signed range: %ld"), val); 3662 if (! fixP->fx_addsy) 3663 bufp[0] = val & 0xFF; 3664 break; 3665 3666 case BFD_RELOC_CRIS_LAPCQ_OFFSET: 3667 /* FIXME: Test-cases for out-of-range values. Probably also need 3668 to use as_bad_where. */ 3669 case BFD_RELOC_CRIS_UNSIGNED_4: 3670 if (val > 15 || val < 0) 3671 as_bad_where (fixP->fx_file, fixP->fx_line, 3672 _("Value not in 4 bit unsigned range: %ld"), val); 3673 if (! fixP->fx_addsy) 3674 bufp[0] |= val & 0x0F; 3675 break; 3676 3677 case BFD_RELOC_CRIS_UNSIGNED_5: 3678 if (val > 31 || val < 0) 3679 as_bad_where (fixP->fx_file, fixP->fx_line, 3680 _("Value not in 5 bit unsigned range: %ld"), val); 3681 if (! fixP->fx_addsy) 3682 bufp[0] |= val & 0x1F; 3683 break; 3684 3685 case BFD_RELOC_CRIS_SIGNED_6: 3686 if (val > 31 || val < -32) 3687 as_bad_where (fixP->fx_file, fixP->fx_line, 3688 _("Value not in 6 bit range: %ld"), val); 3689 if (! fixP->fx_addsy) 3690 bufp[0] |= val & 0x3F; 3691 break; 3692 3693 case BFD_RELOC_CRIS_UNSIGNED_6: 3694 if (val > 63 || val < 0) 3695 as_bad_where (fixP->fx_file, fixP->fx_line, 3696 _("Value not in 6 bit unsigned range: %ld"), val); 3697 if (! fixP->fx_addsy) 3698 bufp[0] |= val & 0x3F; 3699 break; 3700 3701 case BFD_RELOC_CRIS_BDISP8: 3702 if (! fixP->fx_addsy) 3703 bufp[0] = branch_disp (val); 3704 break; 3705 3706 case BFD_RELOC_NONE: 3707 /* May actually happen automatically. For example at broken 3708 words, if the word turns out not to be broken. 3709 FIXME: When? Which testcase? */ 3710 if (! fixP->fx_addsy) 3711 md_number_to_chars (bufp, val, n); 3712 break; 3713 3714 case BFD_RELOC_VTABLE_INHERIT: 3715 /* This borrowed from tc-ppc.c on a whim. */ 3716 if (fixP->fx_addsy 3717 && !S_IS_DEFINED (fixP->fx_addsy) 3718 && !S_IS_WEAK (fixP->fx_addsy)) 3719 S_SET_WEAK (fixP->fx_addsy); 3720 /* Fall through. */ 3721 3722 case BFD_RELOC_VTABLE_ENTRY: 3723 fixP->fx_done = 0; 3724 break; 3725 3726 default: 3727 BAD_CASE (fixP->fx_r_type); 3728 } 3729} 3730 3731/* Processes machine-dependent command line options. Called once for 3732 each option on the command line that the machine-independent part of 3733 GAS does not understand. */ 3734 3735int 3736md_parse_option (int arg, char *argp ATTRIBUTE_UNUSED) 3737{ 3738 switch (arg) 3739 { 3740 case 'H': 3741 case 'h': 3742 printf (_("Please use --help to see usage and options for this assembler.\n")); 3743 md_show_usage (stdout); 3744 exit (EXIT_SUCCESS); 3745 3746 case 'N': 3747 warn_for_branch_expansion = 1; 3748 break; 3749 3750 case OPTION_NO_US: 3751 demand_register_prefix = TRUE; 3752 3753 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 3754 as_bad (_("--no-underscore is invalid with a.out format")); 3755 else 3756 symbols_have_leading_underscore = FALSE; 3757 break; 3758 3759 case OPTION_US: 3760 demand_register_prefix = FALSE; 3761 symbols_have_leading_underscore = TRUE; 3762 break; 3763 3764 case OPTION_PIC: 3765 pic = TRUE; 3766 if (cris_arch != arch_crisv32) 3767 md_long_jump_size = cris_any_v0_v10_long_jump_size_pic; 3768 else 3769 md_long_jump_size = crisv32_long_jump_size; 3770 break; 3771 3772 case OPTION_ARCH: 3773 { 3774 char *str = argp; 3775 enum cris_archs argarch = cris_arch_from_string (&str); 3776 3777 if (argarch == arch_cris_unknown) 3778 as_bad (_("invalid <arch> in --march=<arch>: %s"), argp); 3779 else 3780 cris_arch = argarch; 3781 3782 if (argarch == arch_crisv32) 3783 { 3784 err_for_dangerous_mul_placement = 0; 3785 md_long_jump_size = crisv32_long_jump_size; 3786 } 3787 else 3788 { 3789 if (pic) 3790 md_long_jump_size = cris_any_v0_v10_long_jump_size_pic; 3791 else 3792 md_long_jump_size = cris_any_v0_v10_long_jump_size; 3793 } 3794 } 3795 break; 3796 3797 case OPTION_MULBUG_ABORT_OFF: 3798 err_for_dangerous_mul_placement = 0; 3799 break; 3800 3801 case OPTION_MULBUG_ABORT_ON: 3802 err_for_dangerous_mul_placement = 1; 3803 break; 3804 3805 default: 3806 return 0; 3807 } 3808 3809 return 1; 3810} 3811 3812/* Round up a section size to the appropriate boundary. */ 3813valueT 3814md_section_align (segT segment, valueT size) 3815{ 3816 /* Round all sects to multiple of 4, except the bss section, which 3817 we'll round to word-size. 3818 3819 FIXME: Check if this really matters. All sections should be 3820 rounded up, and all sections should (optionally) be assumed to be 3821 dword-aligned, it's just that there is actual usage of linking to a 3822 multiple of two. */ 3823 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 3824 { 3825 if (segment == bss_section) 3826 return (size + 1) & ~1; 3827 return (size + 3) & ~3; 3828 } 3829 else 3830 { 3831 /* FIXME: Is this wanted? It matches the testsuite, but that's not 3832 really a valid reason. */ 3833 if (segment == text_section) 3834 return (size + 3) & ~3; 3835 } 3836 3837 return size; 3838} 3839 3840/* Generate a machine-dependent relocation. */ 3841arelent * 3842tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP) 3843{ 3844 arelent *relP; 3845 bfd_reloc_code_real_type code; 3846 3847 switch (fixP->fx_r_type) 3848 { 3849 case BFD_RELOC_CRIS_SIGNED_8: 3850 code = BFD_RELOC_8; 3851 break; 3852 3853 case BFD_RELOC_CRIS_SIGNED_16: 3854 code = BFD_RELOC_16; 3855 break; 3856 3857 case BFD_RELOC_CRIS_16_GOT: 3858 case BFD_RELOC_CRIS_32_GOT: 3859 case BFD_RELOC_CRIS_16_GOTPLT: 3860 case BFD_RELOC_CRIS_32_GOTPLT: 3861 case BFD_RELOC_CRIS_32_GOTREL: 3862 case BFD_RELOC_CRIS_32_PLT_GOTREL: 3863 case BFD_RELOC_CRIS_32_PLT_PCREL: 3864 case BFD_RELOC_32: 3865 case BFD_RELOC_32_PCREL: 3866 case BFD_RELOC_16: 3867 case BFD_RELOC_8: 3868 case BFD_RELOC_VTABLE_INHERIT: 3869 case BFD_RELOC_VTABLE_ENTRY: 3870 case BFD_RELOC_CRIS_UNSIGNED_8: 3871 case BFD_RELOC_CRIS_UNSIGNED_16: 3872 case BFD_RELOC_CRIS_LAPCQ_OFFSET: 3873 code = fixP->fx_r_type; 3874 break; 3875 default: 3876 as_bad_where (fixP->fx_file, fixP->fx_line, 3877 _("Semantics error. This type of operand can not be relocated, it must be an assembly-time constant")); 3878 return 0; 3879 } 3880 3881 relP = (arelent *) xmalloc (sizeof (arelent)); 3882 assert (relP != 0); 3883 relP->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3884 *relP->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); 3885 relP->address = fixP->fx_frag->fr_address + fixP->fx_where; 3886 3887 relP->addend = fixP->fx_offset; 3888 3889 /* This is the standard place for KLUDGEs to work around bugs in 3890 bfd_install_relocation (first such note in the documentation 3891 appears with binutils-2.8). 3892 3893 That function bfd_install_relocation does the wrong thing with 3894 putting stuff into the addend of a reloc (it should stay out) for a 3895 weak symbol. The really bad thing is that it adds the 3896 "segment-relative offset" of the symbol into the reloc. In this 3897 case, the reloc should instead be relative to the symbol with no 3898 other offset than the assembly code shows; and since the symbol is 3899 weak, any local definition should be ignored until link time (or 3900 thereafter). 3901 To wit: weaksym+42 should be weaksym+42 in the reloc, 3902 not weaksym+(offset_from_segment_of_local_weaksym_definition) 3903 3904 To "work around" this, we subtract the segment-relative offset of 3905 "known" weak symbols. This evens out the extra offset. 3906 3907 That happens for a.out but not for ELF, since for ELF, 3908 bfd_install_relocation uses the "special function" field of the 3909 howto, and does not execute the code that needs to be undone. */ 3910 3911 if (OUTPUT_FLAVOR == bfd_target_aout_flavour 3912 && fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy) 3913 && ! bfd_is_und_section (S_GET_SEGMENT (fixP->fx_addsy))) 3914 { 3915 relP->addend -= S_GET_VALUE (fixP->fx_addsy); 3916 } 3917 3918 relP->howto = bfd_reloc_type_lookup (stdoutput, code); 3919 if (! relP->howto) 3920 { 3921 const char *name; 3922 3923 name = S_GET_NAME (fixP->fx_addsy); 3924 if (name == NULL) 3925 name = _("<unknown>"); 3926 as_fatal (_("Cannot generate relocation type for symbol %s, code %s"), 3927 name, bfd_get_reloc_code_name (code)); 3928 } 3929 3930 return relP; 3931} 3932 3933/* Machine-dependent usage-output. */ 3934 3935void 3936md_show_usage (FILE *stream) 3937{ 3938 /* The messages are formatted to line up with the generic options. */ 3939 fprintf (stream, _("CRIS-specific options:\n")); 3940 fprintf (stream, "%s", 3941 _(" -h, -H Don't execute, print this help text. Deprecated.\n")); 3942 fprintf (stream, "%s", 3943 _(" -N Warn when branches are expanded to jumps.\n")); 3944 fprintf (stream, "%s", 3945 _(" --underscore User symbols are normally prepended with underscore.\n")); 3946 fprintf (stream, "%s", 3947 _(" Registers will not need any prefix.\n")); 3948 fprintf (stream, "%s", 3949 _(" --no-underscore User symbols do not have any prefix.\n")); 3950 fprintf (stream, "%s", 3951 _(" Registers will require a `$'-prefix.\n")); 3952 fprintf (stream, "%s", 3953 _(" --pic Enable generation of position-independent code.\n")); 3954 fprintf (stream, "%s", 3955 _(" --march=<arch> Generate code for <arch>. Valid choices for <arch>\n\ 3956 are v0_v10, v10, v32 and common_v10_v32.\n")); 3957} 3958 3959/* Apply a fixS (fixup of an instruction or data that we didn't have 3960 enough info to complete immediately) to the data in a frag. */ 3961 3962void 3963md_apply_fix (fixS *fixP, valueT *valP, segT seg) 3964{ 3965 /* This assignment truncates upper bits if valueT is 64 bits (as with 3966 --enable-64-bit-bfd), which is fine here, though we cast to avoid 3967 any compiler warnings. */ 3968 long val = (long) *valP; 3969 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 3970 3971 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 3972 fixP->fx_done = 1; 3973 3974 if (fixP->fx_bit_fixP || fixP->fx_im_disp != 0) 3975 { 3976 as_bad_where (fixP->fx_file, fixP->fx_line, _("Invalid relocation")); 3977 fixP->fx_done = 1; 3978 } 3979 else 3980 { 3981 /* We can't actually support subtracting a symbol. */ 3982 if (fixP->fx_subsy != (symbolS *) NULL) 3983 as_bad_where (fixP->fx_file, fixP->fx_line, 3984 _("expression too complex")); 3985 3986 /* This operand-type is scaled. */ 3987 if (fixP->fx_r_type == BFD_RELOC_CRIS_LAPCQ_OFFSET) 3988 val /= 2; 3989 cris_number_to_imm (buf, val, fixP->fx_size, fixP, seg); 3990 } 3991} 3992 3993/* All relocations are relative to the location just after the fixup; 3994 the address of the fixup plus its size. */ 3995 3996long 3997md_pcrel_from (fixS *fixP) 3998{ 3999 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; 4000 4001 /* FIXME: We get here only at the end of assembly, when X in ".-X" is 4002 still unknown. Since we don't have pc-relative relocations in a.out, 4003 this is invalid. What to do if anything for a.out, is to add 4004 pc-relative relocations everywhere including the elinux program 4005 loader. For ELF, allow straight-forward PC-relative relocations, 4006 which are always relative to the location after the relocation. */ 4007 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 4008 || (fixP->fx_r_type != BFD_RELOC_8_PCREL 4009 && fixP->fx_r_type != BFD_RELOC_16_PCREL 4010 && fixP->fx_r_type != BFD_RELOC_32_PCREL 4011 && fixP->fx_r_type != BFD_RELOC_CRIS_LAPCQ_OFFSET)) 4012 as_bad_where (fixP->fx_file, fixP->fx_line, 4013 _("Invalid pc-relative relocation")); 4014 return fixP->fx_size + addr; 4015} 4016 4017/* We have no need to give defaults for symbol-values. */ 4018symbolS * 4019md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 4020{ 4021 return 0; 4022} 4023 4024/* If this function returns non-zero, it prevents the relocation 4025 against symbol(s) in the FIXP from being replaced with relocations 4026 against section symbols, and guarantees that a relocation will be 4027 emitted even when the value can be resolved locally. */ 4028int 4029md_cris_force_relocation (struct fix *fixp) 4030{ 4031 switch (fixp->fx_r_type) 4032 { 4033 case BFD_RELOC_CRIS_16_GOT: 4034 case BFD_RELOC_CRIS_32_GOT: 4035 case BFD_RELOC_CRIS_16_GOTPLT: 4036 case BFD_RELOC_CRIS_32_GOTPLT: 4037 case BFD_RELOC_CRIS_32_GOTREL: 4038 case BFD_RELOC_CRIS_32_PLT_GOTREL: 4039 case BFD_RELOC_CRIS_32_PLT_PCREL: 4040 return 1; 4041 default: 4042 ; 4043 } 4044 4045 return generic_force_reloc (fixp); 4046} 4047 4048/* Check and emit error if broken-word handling has failed to fix up a 4049 case-table. This is called from write.c, after doing everything it 4050 knows about how to handle broken words. */ 4051 4052void 4053tc_cris_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP) 4054{ 4055 if (new_offset > 32767 || new_offset < -32768) 4056 /* We really want a genuine error, not a warning, so make it one. */ 4057 as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line, 4058 _("Adjusted signed .word (%ld) overflows: `switch'-statement too large."), 4059 (long) new_offset); 4060} 4061 4062/* Make a leading REGISTER_PREFIX_CHAR mandatory for all registers. */ 4063 4064static void 4065cris_force_reg_prefix (void) 4066{ 4067 demand_register_prefix = TRUE; 4068} 4069 4070/* Do not demand a leading REGISTER_PREFIX_CHAR for all registers. */ 4071 4072static void 4073cris_relax_reg_prefix (void) 4074{ 4075 demand_register_prefix = FALSE; 4076} 4077 4078/* Adjust for having a leading '_' on all user symbols. */ 4079 4080static void 4081cris_sym_leading_underscore (void) 4082{ 4083 /* We can't really do anything more than assert that what the program 4084 thinks symbol starts with agrees with the command-line options, since 4085 the bfd is already created. */ 4086 4087 if (!symbols_have_leading_underscore) 4088 as_bad (_(".syntax %s requires command-line option `--underscore'"), 4089 SYNTAX_USER_SYM_LEADING_UNDERSCORE); 4090} 4091 4092/* Adjust for not having any particular prefix on user symbols. */ 4093 4094static void cris_sym_no_leading_underscore (void) 4095{ 4096 if (symbols_have_leading_underscore) 4097 as_bad (_(".syntax %s requires command-line option `--no-underscore'"), 4098 SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE); 4099} 4100 4101/* Handle the .syntax pseudo, which takes an argument that decides what 4102 syntax the assembly code has. */ 4103 4104static void 4105s_syntax (int ignore ATTRIBUTE_UNUSED) 4106{ 4107 static const struct syntaxes 4108 { 4109 const char *const operand; 4110 void (*fn) (void); 4111 } syntax_table[] = 4112 {{SYNTAX_ENFORCE_REG_PREFIX, cris_force_reg_prefix}, 4113 {SYNTAX_RELAX_REG_PREFIX, cris_relax_reg_prefix}, 4114 {SYNTAX_USER_SYM_LEADING_UNDERSCORE, cris_sym_leading_underscore}, 4115 {SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE, cris_sym_no_leading_underscore}}; 4116 4117 const struct syntaxes *sp; 4118 4119 for (sp = syntax_table; 4120 sp < syntax_table + sizeof (syntax_table) / sizeof (syntax_table[0]); 4121 sp++) 4122 { 4123 if (strncmp (input_line_pointer, sp->operand, 4124 strlen (sp->operand)) == 0) 4125 { 4126 (sp->fn) (); 4127 4128 input_line_pointer += strlen (sp->operand); 4129 demand_empty_rest_of_line (); 4130 return; 4131 } 4132 } 4133 4134 as_bad (_("Unknown .syntax operand")); 4135} 4136 4137/* Wrapper for dwarf2_directive_file to emit error if this is seen when 4138 not emitting ELF. */ 4139 4140static void 4141s_cris_file (int dummy) 4142{ 4143 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 4144 as_bad (_("Pseudodirective .file is only valid when generating ELF")); 4145 else 4146 dwarf2_directive_file (dummy); 4147} 4148 4149/* Wrapper for dwarf2_directive_loc to emit error if this is seen when not 4150 emitting ELF. */ 4151 4152static void 4153s_cris_loc (int dummy) 4154{ 4155 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 4156 as_bad (_("Pseudodirective .loc is only valid when generating ELF")); 4157 else 4158 dwarf2_directive_loc (dummy); 4159} 4160 4161/* Translate a <arch> string (as common to --march=<arch> and .arch <arch>) 4162 into an enum. If the string *STR is recognized, *STR is updated to point 4163 to the end of the string. If the string is not recognized, 4164 arch_cris_unknown is returned. */ 4165 4166static enum cris_archs 4167cris_arch_from_string (char **str) 4168{ 4169 static const struct cris_arch_struct 4170 { 4171 const char *const name; 4172 enum cris_archs arch; 4173 } arch_table[] = 4174 /* Keep in order longest-first for choices where one is a prefix 4175 of another. */ 4176 {{"v0_v10", arch_cris_any_v0_v10}, 4177 {"v10", arch_crisv10}, 4178 {"v32", arch_crisv32}, 4179 {"common_v10_v32", arch_cris_common_v10_v32}}; 4180 4181 const struct cris_arch_struct *ap; 4182 4183 for (ap = arch_table; 4184 ap < arch_table + sizeof (arch_table) / sizeof (arch_table[0]); 4185 ap++) 4186 { 4187 int len = strlen (ap->name); 4188 4189 if (strncmp (*str, ap->name, len) == 0 4190 && (str[0][len] == 0 || ISSPACE (str[0][len]))) 4191 { 4192 *str += strlen (ap->name); 4193 return ap->arch; 4194 } 4195 } 4196 4197 return arch_cris_unknown; 4198} 4199 4200/* Return nonzero if architecture version ARCH matches version range in 4201 IVER. */ 4202 4203static int 4204cris_insn_ver_valid_for_arch (enum cris_insn_version_usage iver, 4205 enum cris_archs arch) 4206{ 4207 switch (arch) 4208 { 4209 case arch_cris_any_v0_v10: 4210 return 4211 (iver == cris_ver_version_all 4212 || iver == cris_ver_warning 4213 || iver == cris_ver_v0_3 4214 || iver == cris_ver_v3p 4215 || iver == cris_ver_v0_10 4216 || iver == cris_ver_sim_v0_10 4217 || iver == cris_ver_v3_10 4218 || iver == cris_ver_v8 4219 || iver == cris_ver_v8p 4220 || iver == cris_ver_v8_10 4221 || iver == cris_ver_v10 4222 || iver == cris_ver_v10p); 4223 4224 case arch_crisv32: 4225 return 4226 (iver == cris_ver_version_all 4227 || iver == cris_ver_v3p 4228 || iver == cris_ver_v8p 4229 || iver == cris_ver_v10p 4230 || iver == cris_ver_v32p); 4231 4232 case arch_cris_common_v10_v32: 4233 return 4234 (iver == cris_ver_version_all 4235 || iver == cris_ver_v3p 4236 || iver == cris_ver_v8p 4237 || iver == cris_ver_v10p); 4238 4239 case arch_crisv0: 4240 return 4241 (iver == cris_ver_version_all 4242 || iver == cris_ver_v0_3 4243 || iver == cris_ver_v0_10 4244 || iver == cris_ver_sim_v0_10); 4245 4246 case arch_crisv3: 4247 return 4248 (iver == cris_ver_version_all 4249 || iver == cris_ver_v0_3 4250 || iver == cris_ver_v3p 4251 || iver == cris_ver_v0_10 4252 || iver == cris_ver_sim_v0_10 4253 || iver == cris_ver_v3_10); 4254 4255 case arch_crisv8: 4256 return 4257 (iver == cris_ver_version_all 4258 || iver == cris_ver_v3p 4259 || iver == cris_ver_v0_10 4260 || iver == cris_ver_sim_v0_10 4261 || iver == cris_ver_v3_10 4262 || iver == cris_ver_v8 4263 || iver == cris_ver_v8p 4264 || iver == cris_ver_v8_10); 4265 4266 case arch_crisv10: 4267 return 4268 (iver == cris_ver_version_all 4269 || iver == cris_ver_v3p 4270 || iver == cris_ver_v0_10 4271 || iver == cris_ver_sim_v0_10 4272 || iver == cris_ver_v3_10 4273 || iver == cris_ver_v8p 4274 || iver == cris_ver_v8_10 4275 || iver == cris_ver_v10 4276 || iver == cris_ver_v10p); 4277 4278 default: 4279 BAD_CASE (arch); 4280 } 4281} 4282 4283/* Assert that the .arch ARCHCHOICE1 is compatible with the specified or 4284 default --march=<ARCHCHOICE2> option. */ 4285 4286static void 4287s_cris_arch (int dummy ATTRIBUTE_UNUSED) 4288{ 4289 /* Right now we take the easy route and check for sameness. It's not 4290 obvious that allowing e.g. --march=v32 and .arch common_v0_v32 4291 would be more useful than confusing, implementation-wise and 4292 user-wise. */ 4293 4294 char *str = input_line_pointer; 4295 enum cris_archs arch = cris_arch_from_string (&str); 4296 4297 if (arch == arch_cris_unknown) 4298 { 4299 as_bad (_("unknown operand to .arch")); 4300 4301 /* For this one, str does not reflect the end of the operand, 4302 since there was no matching arch. Skip it manually; skip 4303 things that can be part of a word (a name). */ 4304 while (is_part_of_name (*str)) 4305 str++; 4306 } 4307 else if (arch != cris_arch) 4308 as_bad (_(".arch <arch> requires a matching --march=... option")); 4309 4310 input_line_pointer = str; 4311 demand_empty_rest_of_line (); 4312 return; 4313} 4314 4315/* 4316 * Local variables: 4317 * eval: (c-set-style "gnu") 4318 * indent-tabs-mode: t 4319 * End: 4320 */ 4321