1C PR rtl-optimization/42246 2C { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } 3C { dg-options "-O2 -fselective-scheduling -fsel-sched-pipelining -fsel-sched-pipelining-outer-loops" } 4 5 subroutine distance(x,clo) 6 implicit real*8 (a-h,o-z) 7 dimension x(2,6),x1(2,6),clo(6) 8 do 60 i=1,2 9 do 20 j=1,6 10 x(i,j)=clo(j) 11 20 continue 12 do 40 iq=1,6 13 x1(i,iq)=0.0d0 14 40 continue 15 do 50 j=1,6 16 x(i,j)=x1(i,j) 17 50 continue 18 60 continue 19 return 20 end 21 22