1/* { dg-require-effective-target vect_int } */
2/* { dg-do compile } */
3
4#define N 16
5
6const unsigned int in[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
7unsigned int out[N];
8
9__attribute__ ((noinline)) int
10main1 (void)
11{
12  const unsigned int *pin = &in[1];
13  unsigned int *pout = &out[0];
14
15  /* Misaligned load.  */
16  *pout++ = *pin++;
17  *pout++ = *pin++;
18  *pout++ = *pin++;
19  *pout++ = *pin++;
20
21  return 0;
22}
23
24/* Verify that the assembly contains vector instructions alone
25   with no word loads (lw, lwu, lwz, lwzu, or their indexed forms)
26   or word stores (stw, stwu, stwx, stwux, or their indexed forms).  */
27
28/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv)" } } */
29/* { dg-final { scan-assembler-not "\tlwz?u?x? " } } */
30/* { dg-final { scan-assembler-not "\tstwu?x? " } } */
31