1/* Definitions of target machine for GNU compiler, for Sun SPARC. 2 Copyright (C) 1987-2015 Free Software Foundation, Inc. 3 Contributed by Michael Tiemann (tiemann@cygnus.com). 4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 5 at Cygnus Support. 6 7This file is part of GCC. 8 9GCC is free software; you can redistribute it and/or modify 10it under the terms of the GNU General Public License as published by 11the Free Software Foundation; either version 3, or (at your option) 12any later version. 13 14GCC is distributed in the hope that it will be useful, 15but WITHOUT ANY WARRANTY; without even the implied warranty of 16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17GNU General Public License for more details. 18 19You should have received a copy of the GNU General Public License 20along with GCC; see the file COPYING3. If not see 21<http://www.gnu.org/licenses/>. */ 22 23#include "config/vxworks-dummy.h" 24 25/* Note that some other tm.h files include this one and then override 26 whatever definitions are necessary. */ 27 28#define TARGET_CPU_CPP_BUILTINS() sparc_target_macros () 29 30/* Specify this in a cover file to provide bi-architecture (32/64) support. */ 31/* #define SPARC_BI_ARCH */ 32 33/* Macro used later in this file to determine default architecture. */ 34#define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) 35 36/* TARGET_ARCH{32,64} are the main macros to decide which of the two 37 architectures to compile for. We allow targets to choose compile time or 38 runtime selection. */ 39#ifdef IN_LIBGCC2 40#if defined(__sparcv9) || defined(__arch64__) 41#define TARGET_ARCH32 0 42#else 43#define TARGET_ARCH32 1 44#endif /* sparc64 */ 45#else 46#ifdef SPARC_BI_ARCH 47#define TARGET_ARCH32 (! TARGET_64BIT) 48#else 49#define TARGET_ARCH32 (DEFAULT_ARCH32_P) 50#endif /* SPARC_BI_ARCH */ 51#endif /* IN_LIBGCC2 */ 52#define TARGET_ARCH64 (! TARGET_ARCH32) 53 54/* Code model selection in 64-bit environment. 55 56 The machine mode used for addresses is 32-bit wide: 57 58 TARGET_CM_32: 32-bit address space. 59 It is the code model used when generating 32-bit code. 60 61 The machine mode used for addresses is 64-bit wide: 62 63 TARGET_CM_MEDLOW: 32-bit address space. 64 The executable must be in the low 32 bits of memory. 65 This avoids generating %uhi and %ulo terms. Programs 66 can be statically or dynamically linked. 67 68 TARGET_CM_MEDMID: 44-bit address space. 69 The executable must be in the low 44 bits of memory, 70 and the %[hml]44 terms are used. The text and data 71 segments have a maximum size of 2GB (31-bit span). 72 The maximum offset from any instruction to the label 73 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 74 75 TARGET_CM_MEDANY: 64-bit address space. 76 The text and data segments have a maximum size of 2GB 77 (31-bit span) and may be located anywhere in memory. 78 The maximum offset from any instruction to the label 79 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 80 81 TARGET_CM_EMBMEDANY: 64-bit address space. 82 The text and data segments have a maximum size of 2GB 83 (31-bit span) and may be located anywhere in memory. 84 The global register %g4 contains the start address of 85 the data segment. Programs are statically linked and 86 PIC is not supported. 87 88 Different code models are not supported in 32-bit environment. */ 89 90enum cmodel { 91 CM_32, 92 CM_MEDLOW, 93 CM_MEDMID, 94 CM_MEDANY, 95 CM_EMBMEDANY 96}; 97 98/* One of CM_FOO. */ 99extern enum cmodel sparc_cmodel; 100 101/* V9 code model selection. */ 102#define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) 103#define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) 104#define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) 105#define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) 106 107#define SPARC_DEFAULT_CMODEL CM_32 108 109/* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO) 110 which requires the following macro to be true if enabled. Prior to V9, 111 there are no instructions to even talk about memory synchronization. 112 Note that the UltraSPARC III processors don't implement RMO, unlike the 113 UltraSPARC II processors. Niagara, Niagara-2, and Niagara-3 do not 114 implement RMO either. 115 116 Default to false; for example, Solaris never enables RMO, only ever uses 117 total memory ordering (TMO). */ 118#define SPARC_RELAXED_ORDERING false 119 120/* Do not use the .note.GNU-stack convention by default. */ 121#define NEED_INDICATE_EXEC_STACK 0 122 123/* This is call-clobbered in the normal ABI, but is reserved in the 124 home grown (aka upward compatible) embedded ABI. */ 125#define EMBMEDANY_BASE_REG "%g4" 126 127/* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, 128 and specified by the user via --with-cpu=foo. 129 This specifies the cpu implementation, not the architecture size. */ 130/* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit 131 capable cpu's. */ 132#define TARGET_CPU_sparc 0 133#define TARGET_CPU_v7 0 /* alias */ 134#define TARGET_CPU_cypress 0 /* alias */ 135#define TARGET_CPU_v8 1 /* generic v8 implementation */ 136#define TARGET_CPU_supersparc 2 137#define TARGET_CPU_hypersparc 3 138#define TARGET_CPU_leon 4 139#define TARGET_CPU_leon3 5 140#define TARGET_CPU_leon3v7 6 141#define TARGET_CPU_sparclite 7 142#define TARGET_CPU_f930 7 /* alias */ 143#define TARGET_CPU_f934 7 /* alias */ 144#define TARGET_CPU_sparclite86x 8 145#define TARGET_CPU_sparclet 9 146#define TARGET_CPU_tsc701 9 /* alias */ 147#define TARGET_CPU_v9 10 /* generic v9 implementation */ 148#define TARGET_CPU_sparcv9 10 /* alias */ 149#define TARGET_CPU_sparc64 10 /* alias */ 150#define TARGET_CPU_ultrasparc 11 151#define TARGET_CPU_ultrasparc3 12 152#define TARGET_CPU_niagara 13 153#define TARGET_CPU_niagara2 14 154#define TARGET_CPU_niagara3 15 155#define TARGET_CPU_niagara4 16 156 157#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ 158 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ 159 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ 160 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ 161 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \ 162 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \ 163 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 164 165#define CPP_CPU32_DEFAULT_SPEC "" 166#define ASM_CPU32_DEFAULT_SPEC "" 167 168#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 169/* ??? What does Sun's CC pass? */ 170#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 171/* ??? It's not clear how other assemblers will handle this, so by default 172 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case 173 is handled in sol2.h. */ 174#define ASM_CPU64_DEFAULT_SPEC "-Av9" 175#endif 176#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc 177#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 178#define ASM_CPU64_DEFAULT_SPEC "-Av9a" 179#endif 180#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 181#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 182#define ASM_CPU64_DEFAULT_SPEC "-Av9b" 183#endif 184#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara 185#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 186#define ASM_CPU64_DEFAULT_SPEC "-Av9b" 187#endif 188#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 189#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 190#define ASM_CPU64_DEFAULT_SPEC "-Av9b" 191#endif 192#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 193#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 194#define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG 195#endif 196#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 197#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 198#define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG 199#endif 200 201#else 202 203#define CPP_CPU64_DEFAULT_SPEC "" 204#define ASM_CPU64_DEFAULT_SPEC "" 205 206#if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ 207 || TARGET_CPU_DEFAULT == TARGET_CPU_v8 208#define CPP_CPU32_DEFAULT_SPEC "" 209#define ASM_CPU32_DEFAULT_SPEC "" 210#endif 211 212#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet 213#define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" 214#define ASM_CPU32_DEFAULT_SPEC "-Asparclet" 215#endif 216 217#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite 218#define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" 219#define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 220#endif 221 222#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x 223#define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" 224#define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 225#endif 226 227#if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc 228#define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" 229#define ASM_CPU32_DEFAULT_SPEC "" 230#endif 231 232#if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc 233#define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" 234#define ASM_CPU32_DEFAULT_SPEC "" 235#endif 236 237#if TARGET_CPU_DEFAULT == TARGET_CPU_leon \ 238 || TARGET_CPU_DEFAULT == TARGET_CPU_leon3 239#define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__" 240#define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG 241#endif 242 243#if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7 244#define CPP_CPU32_DEFAULT_SPEC "-D__leon__" 245#define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG 246#endif 247 248#endif 249 250#if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) 251 #error Unrecognized value in TARGET_CPU_DEFAULT. 252#endif 253 254#ifdef SPARC_BI_ARCH 255 256#define CPP_CPU_DEFAULT_SPEC \ 257(DEFAULT_ARCH32_P ? "\ 258%{m64:" CPP_CPU64_DEFAULT_SPEC "} \ 259%{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ 260" : "\ 261%{m32:" CPP_CPU32_DEFAULT_SPEC "} \ 262%{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ 263") 264#define ASM_CPU_DEFAULT_SPEC \ 265(DEFAULT_ARCH32_P ? "\ 266%{m64:" ASM_CPU64_DEFAULT_SPEC "} \ 267%{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ 268" : "\ 269%{m32:" ASM_CPU32_DEFAULT_SPEC "} \ 270%{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ 271") 272 273#else /* !SPARC_BI_ARCH */ 274 275#define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) 276#define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) 277 278#endif /* !SPARC_BI_ARCH */ 279 280/* Define macros to distinguish architectures. */ 281 282/* Common CPP definitions used by CPP_SPEC amongst the various targets 283 for handling -mcpu=xxx switches. */ 284#define CPP_CPU_SPEC "\ 285%{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ 286%{mcpu=sparclite:-D__sparclite__} \ 287%{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ 288%{mcpu=sparclite86x:-D__sparclite86x__} \ 289%{mcpu=v8:-D__sparc_v8__} \ 290%{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ 291%{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ 292%{mcpu=leon:-D__leon__ -D__sparc_v8__} \ 293%{mcpu=leon3:-D__leon__ -D__sparc_v8__} \ 294%{mcpu=leon3v7:-D__leon__} \ 295%{mcpu=v9:-D__sparc_v9__} \ 296%{mcpu=ultrasparc:-D__sparc_v9__} \ 297%{mcpu=ultrasparc3:-D__sparc_v9__} \ 298%{mcpu=niagara:-D__sparc_v9__} \ 299%{mcpu=niagara2:-D__sparc_v9__} \ 300%{mcpu=niagara3:-D__sparc_v9__} \ 301%{mcpu=niagara4:-D__sparc_v9__} \ 302%{!mcpu*:%(cpp_cpu_default)} \ 303" 304#define CPP_ARCH32_SPEC "" 305#define CPP_ARCH64_SPEC "-D__arch64__" 306 307#define CPP_ARCH_DEFAULT_SPEC \ 308(DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) 309 310#define CPP_ARCH_SPEC "\ 311%{m32:%(cpp_arch32)} \ 312%{m64:%(cpp_arch64)} \ 313%{!m32:%{!m64:%(cpp_arch_default)}} \ 314" 315 316/* Macros to distinguish the endianness, window model and FP support. */ 317#define CPP_OTHER_SPEC "\ 318%{mflat:-D_FLAT} \ 319%{msoft-float:-D_SOFT_FLOAT} \ 320" 321 322/* Macros to distinguish the particular subtarget. */ 323#define CPP_SUBTARGET_SPEC "" 324 325#define CPP_SPEC \ 326 "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_other) %(cpp_subtarget)" 327 328/* This used to translate -dalign to -malign, but that is no good 329 because it can't turn off the usual meaning of making debugging dumps. */ 330 331#define CC1_SPEC "" 332 333/* Override in target specific files. */ 334#define ASM_CPU_SPEC "\ 335%{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ 336%{mcpu=sparclite:-Asparclite} \ 337%{mcpu=sparclite86x:-Asparclite} \ 338%{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ 339%{mcpu=v8:-Av8} \ 340%{mcpu=supersparc:-Av8} \ 341%{mcpu=hypersparc:-Av8} \ 342%{mcpu=leon:" AS_LEON_FLAG "} \ 343%{mcpu=leon3:" AS_LEON_FLAG "} \ 344%{mcpu=leon3v7:" AS_LEONV7_FLAG "} \ 345%{mv8plus:-Av8plus} \ 346%{mcpu=v9:-Av9} \ 347%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ 348%{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ 349%{mcpu=niagara:%{!mv8plus:-Av9b}} \ 350%{mcpu=niagara2:%{!mv8plus:-Av9b}} \ 351%{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \ 352%{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \ 353%{!mcpu*:%(asm_cpu_default)} \ 354" 355 356/* Word size selection, among other things. 357 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ 358 359#define ASM_ARCH32_SPEC "-32" 360#ifdef HAVE_AS_REGISTER_PSEUDO_OP 361#define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" 362#else 363#define ASM_ARCH64_SPEC "-64" 364#endif 365#define ASM_ARCH_DEFAULT_SPEC \ 366(DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) 367 368#define ASM_ARCH_SPEC "\ 369%{m32:%(asm_arch32)} \ 370%{m64:%(asm_arch64)} \ 371%{!m32:%{!m64:%(asm_arch_default)}} \ 372" 373 374#ifdef HAVE_AS_RELAX_OPTION 375#define ASM_RELAX_SPEC "%{!mno-relax:-relax}" 376#else 377#define ASM_RELAX_SPEC "" 378#endif 379 380/* Special flags to the Sun-4 assembler when using pipe for input. */ 381 382#define ASM_SPEC "\ 383%{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \ 384%(asm_cpu) %(asm_relax)" 385 386/* This macro defines names of additional specifications to put in the specs 387 that can be used in various specifications like CC1_SPEC. Its definition 388 is an initializer with a subgrouping for each command option. 389 390 Each subgrouping contains a string constant, that defines the 391 specification name, and a string constant that used by the GCC driver 392 program. 393 394 Do not define this macro if it does not need to do anything. */ 395 396#define EXTRA_SPECS \ 397 { "cpp_cpu", CPP_CPU_SPEC }, \ 398 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 399 { "cpp_arch32", CPP_ARCH32_SPEC }, \ 400 { "cpp_arch64", CPP_ARCH64_SPEC }, \ 401 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ 402 { "cpp_arch", CPP_ARCH_SPEC }, \ 403 { "cpp_other", CPP_OTHER_SPEC }, \ 404 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ 405 { "asm_cpu", ASM_CPU_SPEC }, \ 406 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ 407 { "asm_arch32", ASM_ARCH32_SPEC }, \ 408 { "asm_arch64", ASM_ARCH64_SPEC }, \ 409 { "asm_relax", ASM_RELAX_SPEC }, \ 410 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ 411 { "asm_arch", ASM_ARCH_SPEC }, \ 412 SUBTARGET_EXTRA_SPECS 413 414#define SUBTARGET_EXTRA_SPECS 415 416/* Because libgcc can generate references back to libc (via .umul etc.) we have 417 to list libc again after the second libgcc. */ 418#define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L" 419 420 421#define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") 422#define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") 423 424/* ??? This should be 32 bits for v9 but what can we do? */ 425#define WCHAR_TYPE "short unsigned int" 426#define WCHAR_TYPE_SIZE 16 427 428/* Mask of all CPU selection flags. */ 429#define MASK_ISA \ 430 (MASK_SPARCLITE + MASK_SPARCLET \ 431 + MASK_V8 + MASK_V9 + MASK_DEPRECATED_V8_INSNS) 432 433/* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */ 434#define TARGET_HARD_MUL \ 435 (TARGET_SPARCLITE || TARGET_SPARCLET \ 436 || TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) 437 438/* TARGET_HARD_MUL32: Use 32-bit hardware multiply instructions with %y 439 to get high 32 bits. False in 64-bit or V8+ because multiply stores 440 a 64-bit result in a register. */ 441#define TARGET_HARD_MUL32 \ 442 (TARGET_HARD_MUL && TARGET_ARCH32 && !TARGET_V8PLUS) 443 444/* MASK_APP_REGS must always be the default because that's what 445 FIXED_REGISTERS is set to and -ffixed- is processed before 446 TARGET_CONDITIONAL_REGISTER_USAGE is called (where we process 447 -mno-app-regs). */ 448#define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) 449 450/* Recast the cpu class to be the cpu attribute. 451 Every file includes us, but not every file includes insn-attr.h. */ 452#define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) 453 454/* Support for a compile-time default CPU, et cetera. The rules are: 455 --with-cpu is ignored if -mcpu is specified. 456 --with-tune is ignored if -mtune is specified. 457 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu 458 are specified. */ 459#define OPTION_DEFAULT_SPECS \ 460 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 461 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 462 {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" } 463 464/* target machine storage layout */ 465 466/* Define this if most significant bit is lowest numbered 467 in instructions that operate on numbered bit-fields. */ 468#define BITS_BIG_ENDIAN 1 469 470/* Define this if most significant byte of a word is the lowest numbered. */ 471#define BYTES_BIG_ENDIAN 1 472 473/* Define this if most significant word of a multiword number is the lowest 474 numbered. */ 475#define WORDS_BIG_ENDIAN 1 476 477#define MAX_BITS_PER_WORD 64 478 479/* Width of a word, in units (bytes). */ 480#define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) 481#ifdef IN_LIBGCC2 482#define MIN_UNITS_PER_WORD UNITS_PER_WORD 483#else 484#define MIN_UNITS_PER_WORD 4 485#endif 486 487/* Now define the sizes of the C data types. */ 488#define SHORT_TYPE_SIZE 16 489#define INT_TYPE_SIZE 32 490#define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) 491#define LONG_LONG_TYPE_SIZE 64 492#define FLOAT_TYPE_SIZE 32 493#define DOUBLE_TYPE_SIZE 64 494 495/* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the 496 SPARC ABI says that it is 128-bit wide. */ 497/* #define LONG_DOUBLE_TYPE_SIZE 128 */ 498 499/* The widest floating-point format really supported by the hardware. */ 500#define WIDEST_HARDWARE_FP_SIZE 64 501 502/* Width in bits of a pointer. This is the size of ptr_mode. */ 503#define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) 504 505/* This is the machine mode used for addresses. */ 506#define Pmode (TARGET_ARCH64 ? DImode : SImode) 507 508/* If we have to extend pointers (only when TARGET_ARCH64 and not 509 TARGET_PTR64), we want to do it unsigned. This macro does nothing 510 if ptr_mode and Pmode are the same. */ 511#define POINTERS_EXTEND_UNSIGNED 1 512 513/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 514#define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 515 516/* Boundary (in *bits*) on which stack pointer should be aligned. */ 517/* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because 518 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */ 519#define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) 520/* Temporary hack until the FIXME above is fixed. */ 521#define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS) 522 523/* ALIGN FRAMES on double word boundaries */ 524#define SPARC_STACK_ALIGN(LOC) \ 525 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) 526 527/* Allocation boundary (in *bits*) for the code of a function. */ 528#define FUNCTION_BOUNDARY 32 529 530/* Alignment of field after `int : 0' in a structure. */ 531#define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 532 533/* Every structure's size must be a multiple of this. */ 534#define STRUCTURE_SIZE_BOUNDARY 8 535 536/* A bit-field declared as `int' forces `int' alignment for the struct. */ 537#define PCC_BITFIELD_TYPE_MATTERS 1 538 539/* No data type wants to be aligned rounder than this. */ 540#define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) 541 542/* The best alignment to use in cases where we have a choice. */ 543#define FASTEST_ALIGNMENT 64 544 545/* Define this macro as an expression for the alignment of a structure 546 (given by STRUCT as a tree node) if the alignment computed in the 547 usual way is COMPUTED and the alignment explicitly specified was 548 SPECIFIED. 549 550 The default is to use SPECIFIED if it is larger; otherwise, use 551 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ 552#define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ 553 (TARGET_FASTER_STRUCTS ? \ 554 ((TREE_CODE (STRUCT) == RECORD_TYPE \ 555 || TREE_CODE (STRUCT) == UNION_TYPE \ 556 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ 557 && TYPE_FIELDS (STRUCT) != 0 \ 558 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ 559 : MAX ((COMPUTED), (SPECIFIED))) \ 560 : MAX ((COMPUTED), (SPECIFIED))) 561 562/* An integer expression for the size in bits of the largest integer machine 563 mode that should actually be used. We allow pairs of registers. */ 564#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_ARCH64 ? TImode : DImode) 565 566/* We need 2 words, so we can save the stack pointer and the return register 567 of the function containing a non-local goto target. */ 568#define STACK_SAVEAREA_MODE(LEVEL) \ 569 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_ARCH64 ? TImode : DImode) : Pmode) 570 571/* Make strings word-aligned so strcpy from constants will be faster. */ 572#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 573 ((TREE_CODE (EXP) == STRING_CST \ 574 && (ALIGN) < FASTEST_ALIGNMENT) \ 575 ? FASTEST_ALIGNMENT : (ALIGN)) 576 577/* Make arrays of chars word-aligned for the same reasons. */ 578#define DATA_ALIGNMENT(TYPE, ALIGN) \ 579 (TREE_CODE (TYPE) == ARRAY_TYPE \ 580 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 581 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 582 583/* Make local arrays of chars word-aligned for the same reasons. */ 584#define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) 585 586/* Set this nonzero if move instructions will actually fail to work 587 when given unaligned data. */ 588#define STRICT_ALIGNMENT 1 589 590/* Things that must be doubleword aligned cannot go in the text section, 591 because the linker fails to align the text section enough! 592 Put them in the data section. This macro is only used in this file. */ 593#define MAX_TEXT_ALIGN 32 594 595/* Standard register usage. */ 596 597/* Number of actual hardware registers. 598 The hardware registers are assigned numbers for the compiler 599 from 0 to just below FIRST_PSEUDO_REGISTER. 600 All registers that the compiler knows about must be given numbers, 601 even those that are not normally considered general registers. 602 603 SPARC has 32 integer registers and 32 floating point registers. 604 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not 605 accessible. We still account for them to simplify register computations 606 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 607 32+32+32+4 == 100. 608 Register 100 is used as the integer condition code register. 609 Register 101 is used as the soft frame pointer register. */ 610 611#define FIRST_PSEUDO_REGISTER 103 612 613#define SPARC_FIRST_INT_REG 0 614#define SPARC_LAST_INT_REG 31 615#define SPARC_FIRST_FP_REG 32 616/* Additional V9 fp regs. */ 617#define SPARC_FIRST_V9_FP_REG 64 618#define SPARC_LAST_V9_FP_REG 95 619/* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ 620#define SPARC_FIRST_V9_FCC_REG 96 621#define SPARC_LAST_V9_FCC_REG 99 622/* V8 fcc reg. */ 623#define SPARC_FCC_REG 96 624/* Integer CC reg. We don't distinguish %icc from %xcc. */ 625#define SPARC_ICC_REG 100 626#define SPARC_GSR_REG 102 627 628/* Nonzero if REGNO is an fp reg. */ 629#define SPARC_FP_REG_P(REGNO) \ 630((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) 631 632/* Nonzero if REGNO is an int reg. */ 633#define SPARC_INT_REG_P(REGNO) \ 634(((unsigned) (REGNO)) <= SPARC_LAST_INT_REG) 635 636/* Argument passing regs. */ 637#define SPARC_OUTGOING_INT_ARG_FIRST 8 638#define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) 639#define SPARC_FP_ARG_FIRST 32 640 641/* 1 for registers that have pervasive standard uses 642 and are not available for the register allocator. 643 644 On non-v9 systems: 645 g1 is free to use as temporary. 646 g2-g4 are reserved for applications. Gcc normally uses them as 647 temporaries, but this can be disabled via the -mno-app-regs option. 648 g5 through g7 are reserved for the operating system. 649 650 On v9 systems: 651 g1,g5 are free to use as temporaries, and are free to use between calls 652 if the call is to an external function via the PLT. 653 g4 is free to use as a temporary in the non-embedded case. 654 g4 is reserved in the embedded case. 655 g2-g3 are reserved for applications. Gcc normally uses them as 656 temporaries, but this can be disabled via the -mno-app-regs option. 657 g6-g7 are reserved for the operating system (or application in 658 embedded case). 659 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must 660 currently be a fixed register until this pattern is rewritten. 661 Register 1 is also used when restoring call-preserved registers in large 662 stack frames. 663 664 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in 665 TARGET_CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. 666*/ 667 668#define FIXED_REGISTERS \ 669 {1, 0, 2, 2, 2, 2, 1, 1, \ 670 0, 0, 0, 0, 0, 0, 1, 0, \ 671 0, 0, 0, 0, 0, 0, 0, 0, \ 672 0, 0, 0, 0, 0, 0, 0, 1, \ 673 \ 674 0, 0, 0, 0, 0, 0, 0, 0, \ 675 0, 0, 0, 0, 0, 0, 0, 0, \ 676 0, 0, 0, 0, 0, 0, 0, 0, \ 677 0, 0, 0, 0, 0, 0, 0, 0, \ 678 \ 679 0, 0, 0, 0, 0, 0, 0, 0, \ 680 0, 0, 0, 0, 0, 0, 0, 0, \ 681 0, 0, 0, 0, 0, 0, 0, 0, \ 682 0, 0, 0, 0, 0, 0, 0, 0, \ 683 \ 684 0, 0, 0, 0, 0, 1, 1} 685 686/* 1 for registers not available across function calls. 687 These must include the FIXED_REGISTERS and also any 688 registers that can be used without being saved. 689 The latter must include the registers where values are returned 690 and the register where structure-value addresses are passed. 691 Aside from that, you can include as many other registers as you like. */ 692 693#define CALL_USED_REGISTERS \ 694 {1, 1, 1, 1, 1, 1, 1, 1, \ 695 1, 1, 1, 1, 1, 1, 1, 1, \ 696 0, 0, 0, 0, 0, 0, 0, 0, \ 697 0, 0, 0, 0, 0, 0, 0, 1, \ 698 \ 699 1, 1, 1, 1, 1, 1, 1, 1, \ 700 1, 1, 1, 1, 1, 1, 1, 1, \ 701 1, 1, 1, 1, 1, 1, 1, 1, \ 702 1, 1, 1, 1, 1, 1, 1, 1, \ 703 \ 704 1, 1, 1, 1, 1, 1, 1, 1, \ 705 1, 1, 1, 1, 1, 1, 1, 1, \ 706 1, 1, 1, 1, 1, 1, 1, 1, \ 707 1, 1, 1, 1, 1, 1, 1, 1, \ 708 \ 709 1, 1, 1, 1, 1, 1, 1} 710 711/* Return number of consecutive hard regs needed starting at reg REGNO 712 to hold something of mode MODE. 713 This is ordinarily the length in words of a value of mode MODE 714 but can be less for certain modes in special long registers. 715 716 On SPARC, ordinary registers hold 32 bits worth; 717 this means both integer and floating point registers. 718 On v9, integer regs hold 64 bits worth; floating point regs hold 719 32 bits worth (this includes the new fp regs as even the odd ones are 720 included in the hard register count). */ 721 722#define HARD_REGNO_NREGS(REGNO, MODE) \ 723 ((REGNO) == SPARC_GSR_REG ? 1 : \ 724 (TARGET_ARCH64 \ 725 ? (SPARC_INT_REG_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM \ 726 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ 727 : (GET_MODE_SIZE (MODE) + 3) / 4) \ 728 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 729 730/* Due to the ARCH64 discrepancy above we must override this next 731 macro too. */ 732#define REGMODE_NATURAL_SIZE(MODE) sparc_regmode_natural_size (MODE) 733 734/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 735 See sparc.c for how we initialize this. */ 736extern const int *hard_regno_mode_classes; 737extern int sparc_mode_class[]; 738 739/* ??? Because of the funny way we pass parameters we should allow certain 740 ??? types of float/complex values to be in integer registers during 741 ??? RTL generation. This only matters on arch32. */ 742#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 743 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) 744 745/* Value is 1 if it is OK to rename a hard register FROM to another hard 746 register TO. We cannot rename %g1 as it may be used before the save 747 register window instruction in the prologue. */ 748#define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1) 749 750#define MODES_TIEABLE_P(MODE1, MODE2) sparc_modes_tieable_p (MODE1, MODE2) 751 752/* Specify the registers used for certain standard purposes. 753 The values of these macros are register numbers. */ 754 755/* Register to use for pushing function arguments. */ 756#define STACK_POINTER_REGNUM 14 757 758/* The stack bias (amount by which the hardware register is offset by). */ 759#define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) 760 761/* Actual top-of-stack address is 92/176 greater than the contents of the 762 stack pointer register for !v9/v9. That is: 763 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return 764 address, and 6*4 bytes for the 6 register parameters. 765 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer 766 parameter regs. */ 767#define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) 768 769/* Base register for access to local variables of the function. */ 770#define HARD_FRAME_POINTER_REGNUM 30 771 772/* The soft frame pointer does not have the stack bias applied. */ 773#define FRAME_POINTER_REGNUM 101 774 775/* Given the stack bias, the stack pointer isn't actually aligned. */ 776#define INIT_EXPANDERS \ 777 do { \ 778 if (crtl->emit.regno_pointer_align && SPARC_STACK_BIAS) \ 779 { \ 780 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \ 781 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \ 782 } \ 783 } while (0) 784 785/* Base register for access to arguments of the function. */ 786#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 787 788/* Register in which static-chain is passed to a function. This must 789 not be a register used by the prologue. */ 790#define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) 791 792/* Register which holds the global offset table, if any. */ 793 794#define GLOBAL_OFFSET_TABLE_REGNUM 23 795 796/* Register which holds offset table for position-independent 797 data references. */ 798 799#define PIC_OFFSET_TABLE_REGNUM \ 800 (flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 801 802/* Pick a default value we can notice from override_options: 803 !v9: Default is on. 804 v9: Default is off. 805 Originally it was -1, but later on the container of options changed to 806 unsigned byte, so we decided to pick 127 as default value, which does 807 reflect an undefined default value in case of 0/1. */ 808 809#define DEFAULT_PCC_STRUCT_RETURN 127 810 811/* Functions which return large structures get the address 812 to place the wanted value at offset 64 from the frame. 813 Must reserve 64 bytes for the in and local registers. 814 v9: Functions which return large structures get the address to place the 815 wanted value from an invisible first argument. */ 816#define STRUCT_VALUE_OFFSET 64 817 818/* Define the classes of registers for register constraints in the 819 machine description. Also define ranges of constants. 820 821 One of the classes must always be named ALL_REGS and include all hard regs. 822 If there is more than one class, another class must be named NO_REGS 823 and contain no registers. 824 825 The name GENERAL_REGS must be the name of a class (or an alias for 826 another name such as ALL_REGS). This is the class of registers 827 that is allowed by "g" or "r" in a register constraint. 828 Also, registers outside this class are allocated only when 829 instructions express preferences for them. 830 831 The classes must be numbered in nondecreasing order; that is, 832 a larger-numbered class must never be contained completely 833 in a smaller-numbered class. 834 835 For any two classes, it is very desirable that there be another 836 class that represents their union. */ 837 838/* The SPARC has various kinds of registers: general, floating point, 839 and condition codes [well, it has others as well, but none that we 840 care directly about]. 841 842 For v9 we must distinguish between the upper and lower floating point 843 registers because the upper ones can't hold SFmode values. 844 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) 845 satisfying a group need for a class will also satisfy a single need for 846 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp 847 regs. 848 849 It is important that one class contains all the general and all the standard 850 fp regs. Otherwise find_reg() won't properly allocate int regs for moves, 851 because reg_class_record() will bias the selection in favor of fp regs, 852 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, 853 because FP_REGS > GENERAL_REGS. 854 855 It is also important that one class contain all the general and all 856 the fp regs. Otherwise when spilling a DFmode reg, it may be from 857 EXTRA_FP_REGS but find_reloads() may use class 858 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die 859 because the compiler thinks it doesn't have a spill reg when in 860 fact it does. 861 862 v9 also has 4 floating point condition code registers. Since we don't 863 have a class that is the union of FPCC_REGS with either of the others, 864 it is important that it appear first. Otherwise the compiler will die 865 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its 866 constraints. 867 868 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine 869 may try to use it to hold an SImode value. See register_operand. 870 ??? Should %fcc[0123] be handled similarly? 871*/ 872 873enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, 874 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, 875 ALL_REGS, LIM_REG_CLASSES }; 876 877#define N_REG_CLASSES (int) LIM_REG_CLASSES 878 879/* Give names of register classes as strings for dump file. */ 880 881#define REG_CLASS_NAMES \ 882 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ 883 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ 884 "ALL_REGS" } 885 886/* Define which registers fit in which classes. 887 This is an initializer for a vector of HARD_REG_SET 888 of length N_REG_CLASSES. */ 889 890#define REG_CLASS_CONTENTS \ 891 {{0, 0, 0, 0}, /* NO_REGS */ \ 892 {0, 0, 0, 0xf}, /* FPCC_REGS */ \ 893 {0xffff, 0, 0, 0}, /* I64_REGS */ \ 894 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ 895 {0, -1, 0, 0}, /* FP_REGS */ \ 896 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ 897 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ 898 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ 899 {-1, -1, -1, 0x7f}} /* ALL_REGS */ 900 901/* The same information, inverted: 902 Return the class number of the smallest class containing 903 reg number REGNO. This could be a conditional expression 904 or could index an array. */ 905 906extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 907 908#define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] 909 910/* Defines invalid mode changes. Borrowed from the PA port. 911 912 SImode loads to floating-point registers are not zero-extended. 913 The definition for LOAD_EXTEND_OP specifies that integer loads 914 narrower than BITS_PER_WORD will be zero-extended. As a result, 915 we inhibit changes from SImode unless they are to a mode that is 916 identical in size. 917 918 Likewise for SFmode, since word-mode paradoxical subregs are 919 problematic on big-endian architectures. */ 920 921#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 922 (TARGET_ARCH64 \ 923 && GET_MODE_SIZE (FROM) == 4 \ 924 && GET_MODE_SIZE (TO) != 4 \ 925 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) 926 927/* This is the order in which to allocate registers normally. 928 929 We put %f0-%f7 last among the float registers, so as to make it more 930 likely that a pseudo-register which dies in the float return register 931 area will get allocated to the float return register, thus saving a move 932 instruction at the end of the function. 933 934 Similarly for integer return value registers. 935 936 We know in this case that we will not end up with a leaf function. 937 938 The register allocator is given the global and out registers first 939 because these registers are call clobbered and thus less useful to 940 global register allocation. 941 942 Next we list the local and in registers. They are not call clobbered 943 and thus very useful for global register allocation. We list the input 944 registers before the locals so that it is more likely the incoming 945 arguments received in those registers can just stay there and not be 946 reloaded. */ 947 948#define REG_ALLOC_ORDER \ 949{ 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 950 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 951 15, /* %o7 */ \ 952 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 953 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ 954 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 955 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 956 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 957 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 958 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 959 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 960 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 961 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 962 96, 97, 98, 99, /* %fcc0-3 */ \ 963 100, 0, 14, 30, 101, 102 } /* %icc, %g0, %o6, %i6, %sfp, %gsr */ 964 965/* This is the order in which to allocate registers for 966 leaf functions. If all registers can fit in the global and 967 output registers, then we have the possibility of having a leaf 968 function. 969 970 The macro actually mentioned the input registers first, 971 because they get renumbered into the output registers once 972 we know really do have a leaf function. 973 974 To be more precise, this register allocation order is used 975 when %o7 is found to not be clobbered right before register 976 allocation. Normally, the reason %o7 would be clobbered is 977 due to a call which could not be transformed into a sibling 978 call. 979 980 As a consequence, it is possible to use the leaf register 981 allocation order and not end up with a leaf function. We will 982 not get suboptimal register allocation in that case because by 983 definition of being potentially leaf, there were no function 984 calls. Therefore, allocation order within the local register 985 window is not critical like it is when we do have function calls. */ 986 987#define REG_LEAF_ALLOC_ORDER \ 988{ 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 989 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ 990 15, /* %o7 */ \ 991 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 992 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 993 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 994 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 995 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 996 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 997 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 998 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 999 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 1000 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 1001 96, 97, 98, 99, /* %fcc0-3 */ \ 1002 100, 0, 14, 30, 31, 101, 102 } /* %icc, %g0, %o6, %i6, %i7, %sfp, %gsr */ 1003 1004#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () 1005 1006extern char sparc_leaf_regs[]; 1007#define LEAF_REGISTERS sparc_leaf_regs 1008 1009extern char leaf_reg_remap[]; 1010#define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) 1011 1012/* The class value for index registers, and the one for base regs. */ 1013#define INDEX_REG_CLASS GENERAL_REGS 1014#define BASE_REG_CLASS GENERAL_REGS 1015 1016/* Local macro to handle the two v9 classes of FP regs. */ 1017#define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) 1018 1019/* Predicates for 5-bit, 10-bit, 11-bit and 13-bit signed constants. */ 1020#define SPARC_SIMM5_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x10 < 0x20) 1021#define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) 1022#define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) 1023#define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) 1024 1025/* 10- and 11-bit immediates are only used for a few specific insns. 1026 SMALL_INT is used throughout the port so we continue to use it. */ 1027#define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) 1028 1029/* Predicate for constants that can be loaded with a sethi instruction. 1030 This is the general, 64-bit aware, bitwise version that ensures that 1031 only constants whose representation fits in the mask 1032 1033 0x00000000fffffc00 1034 1035 are accepted. It will reject, for example, negative SImode constants 1036 on 64-bit hosts, so correct handling is to mask the value beforehand 1037 according to the mode of the instruction. */ 1038#define SPARC_SETHI_P(X) \ 1039 (((unsigned HOST_WIDE_INT) (X) \ 1040 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) 1041 1042/* Version of the above predicate for SImode constants and below. */ 1043#define SPARC_SETHI32_P(X) \ 1044 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) 1045 1046/* On SPARC when not VIS3 it is not possible to directly move data 1047 between GENERAL_REGS and FP_REGS. */ 1048#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1049 ((FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) \ 1050 && (! TARGET_VIS3 \ 1051 || GET_MODE_SIZE (MODE) > 8 \ 1052 || GET_MODE_SIZE (MODE) < 4)) 1053 1054/* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9 1055 because the movsi and movsf patterns don't handle r/f moves. 1056 For v8 we copy the default definition. */ 1057#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1058 (TARGET_ARCH64 \ 1059 ? (GET_MODE_BITSIZE (MODE) < 32 \ 1060 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1061 : MODE) \ 1062 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ 1063 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ 1064 : MODE)) 1065 1066/* Return the maximum number of consecutive registers 1067 needed to represent mode MODE in a register of class CLASS. */ 1068/* On SPARC, this is the size of MODE in words. */ 1069#define CLASS_MAX_NREGS(CLASS, MODE) \ 1070 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ 1071 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1072 1073/* Stack layout; function entry, exit and calling. */ 1074 1075/* Define this if pushing a word on the stack 1076 makes the stack pointer a smaller address. */ 1077#define STACK_GROWS_DOWNWARD 1078 1079/* Define this to nonzero if the nominal address of the stack frame 1080 is at the high-address end of the local variables; 1081 that is, each additional local variable allocated 1082 goes at a more negative offset in the frame. */ 1083#define FRAME_GROWS_DOWNWARD 1 1084 1085/* Offset within stack frame to start allocating local variables at. 1086 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1087 first local allocated. Otherwise, it is the offset to the BEGINNING 1088 of the first local allocated. */ 1089#define STARTING_FRAME_OFFSET 0 1090 1091/* Offset of first parameter from the argument pointer register value. 1092 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg 1093 even if this function isn't going to use it. 1094 v9: This is 128 for the ins and locals. */ 1095#define FIRST_PARM_OFFSET(FNDECL) \ 1096 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) 1097 1098/* Offset from the argument pointer register value to the CFA. 1099 This is different from FIRST_PARM_OFFSET because the register window 1100 comes between the CFA and the arguments. */ 1101#define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1102 1103/* When a parameter is passed in a register, stack space is still 1104 allocated for it. 1105 !v9: All 6 possible integer registers have backing store allocated. 1106 v9: Only space for the arguments passed is allocated. */ 1107/* ??? Ideally, we'd use zero here (as the minimum), but zero has special 1108 meaning to the backend. Further, we need to be able to detect if a 1109 varargs/unprototyped function is called, as they may want to spill more 1110 registers than we've provided space. Ugly, ugly. So for now we retain 1111 all 6 slots even for v9. */ 1112#define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) 1113 1114/* Definitions for register elimination. */ 1115 1116#define ELIMINABLE_REGS \ 1117 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1118 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } 1119 1120#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1121 do \ 1122 { \ 1123 (OFFSET) = sparc_initial_elimination_offset ((TO)); \ 1124 } \ 1125 while (0) 1126 1127/* Keep the stack pointer constant throughout the function. 1128 This is both an optimization and a necessity: longjmp 1129 doesn't behave itself when the stack pointer moves within 1130 the function! */ 1131#define ACCUMULATE_OUTGOING_ARGS 1 1132 1133/* Define this macro if the target machine has "register windows". This 1134 C expression returns the register number as seen by the called function 1135 corresponding to register number OUT as seen by the calling function. 1136 Return OUT if register number OUT is not an outbound register. */ 1137 1138#define INCOMING_REGNO(OUT) \ 1139 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) 1140 1141/* Define this macro if the target machine has "register windows". This 1142 C expression returns the register number as seen by the calling function 1143 corresponding to register number IN as seen by the called function. 1144 Return IN if register number IN is not an inbound register. */ 1145 1146#define OUTGOING_REGNO(IN) \ 1147 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) 1148 1149/* Define this macro if the target machine has register windows. This 1150 C expression returns true if the register is call-saved but is in the 1151 register window. */ 1152 1153#define LOCAL_REGNO(REGNO) \ 1154 (!TARGET_FLAT && (REGNO) >= 16 && (REGNO) <= 31) 1155 1156/* Define the size of space to allocate for the return value of an 1157 untyped_call. */ 1158 1159#define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16) 1160 1161/* 1 if N is a possible register number for function argument passing. 1162 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ 1163 1164#define FUNCTION_ARG_REGNO_P(N) \ 1165(TARGET_ARCH64 \ 1166 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \ 1167 : ((N) >= 8 && (N) <= 13)) 1168 1169/* Define a data type for recording info about an argument list 1170 during the scan of that argument list. This data type should 1171 hold all necessary information about the function itself 1172 and about the args processed so far, enough to enable macros 1173 such as FUNCTION_ARG to determine where the next arg should go. 1174 1175 On SPARC (!v9), this is a single integer, which is a number of words 1176 of arguments scanned so far (including the invisible argument, 1177 if any, which holds the structure-value-address). 1178 Thus 7 or more means all following args should go on the stack. 1179 1180 For v9, we also need to know whether a prototype is present. */ 1181 1182struct sparc_args { 1183 int words; /* number of words passed so far */ 1184 int prototype_p; /* nonzero if a prototype is present */ 1185 int libcall_p; /* nonzero if a library call */ 1186}; 1187#define CUMULATIVE_ARGS struct sparc_args 1188 1189/* Initialize a variable CUM of type CUMULATIVE_ARGS 1190 for a call to a function whose data type is FNTYPE. 1191 For a library call, FNTYPE is 0. */ 1192 1193#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1194init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); 1195 1196/* If defined, a C expression which determines whether, and in which direction, 1197 to pad out an argument with extra space. The value should be of type 1198 `enum direction': either `upward' to pad above the argument, 1199 `downward' to pad below, or `none' to inhibit padding. */ 1200 1201#define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1202function_arg_padding ((MODE), (TYPE)) 1203 1204 1205/* Generate the special assembly code needed to tell the assembler whatever 1206 it might need to know about the return value of a function. 1207 1208 For SPARC assemblers, we need to output a .proc pseudo-op which conveys 1209 information to the assembler relating to peephole optimization (done in 1210 the assembler). */ 1211 1212#define ASM_DECLARE_RESULT(FILE, RESULT) \ 1213 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) 1214 1215/* Output the special assembly code needed to tell the assembler some 1216 register is used as global register variable. 1217 1218 SPARC 64bit psABI declares registers %g2 and %g3 as application 1219 registers and %g6 and %g7 as OS registers. Any object using them 1220 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them 1221 and how they are used (scratch or some global variable). 1222 Linker will then refuse to link together objects which use those 1223 registers incompatibly. 1224 1225 Unless the registers are used for scratch, two different global 1226 registers cannot be declared to the same name, so in the unlikely 1227 case of a global register variable occupying more than one register 1228 we prefix the second and following registers with .gnu.part1. etc. */ 1229 1230extern GTY(()) char sparc_hard_reg_printed[8]; 1231 1232#ifdef HAVE_AS_REGISTER_PSEUDO_OP 1233#define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ 1234do { \ 1235 if (TARGET_ARCH64) \ 1236 { \ 1237 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \ 1238 int reg; \ 1239 for (reg = (REGNO); reg < 8 && reg < end; reg++) \ 1240 if ((reg & ~1) == 2 || (reg & ~1) == 6) \ 1241 { \ 1242 if (reg == (REGNO)) \ 1243 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ 1244 else \ 1245 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ 1246 reg, reg - (REGNO), (NAME)); \ 1247 sparc_hard_reg_printed[reg] = 1; \ 1248 } \ 1249 } \ 1250} while (0) 1251#endif 1252 1253 1254/* Emit rtl for profiling. */ 1255#define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) 1256 1257/* All the work done in PROFILE_HOOK, but still required. */ 1258#define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) 1259 1260/* Set the name of the mcount function for the system. */ 1261#define MCOUNT_FUNCTION "*mcount" 1262 1263/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1264 the stack pointer does not matter. The value is tested only in 1265 functions that have frame pointers. */ 1266#define EXIT_IGNORE_STACK 1 1267 1268/* Length in units of the trampoline for entering a nested function. */ 1269#define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) 1270 1271/* Alignment required for trampolines, in bits. */ 1272#define TRAMPOLINE_ALIGNMENT 128 1273 1274/* Generate RTL to flush the register windows so as to make arbitrary frames 1275 available. */ 1276#define SETUP_FRAME_ADDRESSES() \ 1277 do { \ 1278 if (!TARGET_FLAT) \ 1279 emit_insn (gen_flush_register_windows ());\ 1280 } while (0) 1281 1282/* Given an rtx for the address of a frame, 1283 return an rtx for the address of the word in the frame 1284 that holds the dynamic chain--the previous frame's address. */ 1285#define DYNAMIC_CHAIN_ADDRESS(frame) \ 1286 plus_constant (Pmode, frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) 1287 1288/* Given an rtx for the frame pointer, 1289 return an rtx for the address of the frame. */ 1290#define FRAME_ADDR_RTX(frame) plus_constant (Pmode, frame, SPARC_STACK_BIAS) 1291 1292/* The return address isn't on the stack, it is in a register, so we can't 1293 access it from the current frame pointer. We can access it from the 1294 previous frame pointer though by reading a value from the register window 1295 save area. */ 1296#define RETURN_ADDR_IN_PREVIOUS_FRAME 1 1297 1298/* This is the offset of the return address to the true next instruction to be 1299 executed for the current function. */ 1300#define RETURN_ADDR_OFFSET \ 1301 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct)) 1302 1303/* The current return address is in %i7. The return address of anything 1304 farther back is in the register window save area at [%fp+60]. */ 1305/* ??? This ignores the fact that the actual return address is +8 for normal 1306 returns, and +12 for structure returns. */ 1307#define RETURN_ADDR_REGNUM 31 1308#define RETURN_ADDR_RTX(count, frame) \ 1309 ((count == -1) \ 1310 ? gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) \ 1311 : gen_rtx_MEM (Pmode, \ 1312 memory_address (Pmode, plus_constant (Pmode, frame, \ 1313 15 * UNITS_PER_WORD \ 1314 + SPARC_STACK_BIAS)))) 1315 1316/* Before the prologue, the return address is %o7 + 8. OK, sometimes it's 1317 +12, but always using +8 is close enough for frame unwind purposes. 1318 Actually, just using %o7 is close enough for unwinding, but %o7+8 1319 is something you can return to. */ 1320#define INCOMING_RETURN_ADDR_REGNUM 15 1321#define INCOMING_RETURN_ADDR_RTX \ 1322 plus_constant (word_mode, \ 1323 gen_rtx_REG (word_mode, INCOMING_RETURN_ADDR_REGNUM), 8) 1324#define DWARF_FRAME_RETURN_COLUMN \ 1325 DWARF_FRAME_REGNUM (INCOMING_RETURN_ADDR_REGNUM) 1326 1327/* The offset from the incoming value of %sp to the top of the stack frame 1328 for the current function. On sparc64, we have to account for the stack 1329 bias if present. */ 1330#define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS 1331 1332/* Describe how we implement __builtin_eh_return. */ 1333#define EH_RETURN_REGNUM 1 1334#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) 1335#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM) 1336 1337/* Define registers used by the epilogue and return instruction. */ 1338#define EPILOGUE_USES(REGNO) \ 1339 ((REGNO) == RETURN_ADDR_REGNUM \ 1340 || (TARGET_FLAT \ 1341 && epilogue_completed \ 1342 && (REGNO) == INCOMING_RETURN_ADDR_REGNUM) \ 1343 || (crtl->calls_eh_return && (REGNO) == EH_RETURN_REGNUM)) 1344 1345/* Select a format to encode pointers in exception handling data. CODE 1346 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1347 true if the symbol may be affected by dynamic relocations. 1348 1349 If assembler and linker properly support .uaword %r_disp32(foo), 1350 then use PC relative 32-bit relocations instead of absolute relocs 1351 for shared libraries. On sparc64, use pc relative 32-bit relocs even 1352 for binaries, to save memory. 1353 1354 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the 1355 symbol %r_disp32() is against was not local, but .hidden. In that 1356 case, we have to use DW_EH_PE_absptr for pic personality. */ 1357#ifdef HAVE_AS_SPARC_UA_PCREL 1358#ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN 1359#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1360 (flag_pic \ 1361 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 1362 : ((TARGET_ARCH64 && ! GLOBAL) \ 1363 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1364 : DW_EH_PE_absptr)) 1365#else 1366#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1367 (flag_pic \ 1368 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ 1369 : ((TARGET_ARCH64 && ! GLOBAL) \ 1370 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1371 : DW_EH_PE_absptr)) 1372#endif 1373 1374/* Emit a PC-relative relocation. */ 1375#define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 1376 do { \ 1377 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1378 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ 1379 assemble_name (FILE, LABEL); \ 1380 fputc (')', FILE); \ 1381 } while (0) 1382#endif 1383 1384/* Addressing modes, and classification of registers for them. */ 1385 1386/* Macros to check register numbers against specific register classes. */ 1387 1388/* These assume that REGNO is a hard or pseudo reg number. 1389 They give nonzero only if REGNO is a hard reg of the suitable class 1390 or a pseudo reg currently allocated to a suitable hard reg. 1391 Since they use reg_renumber, they are safe only once reg_renumber 1392 has been allocated, which happens in reginfo.c during register 1393 allocation. */ 1394 1395#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1396(SPARC_INT_REG_P (REGNO) || SPARC_INT_REG_P (reg_renumber[REGNO]) \ 1397 || (REGNO) == FRAME_POINTER_REGNUM \ 1398 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) 1399 1400#define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 1401 1402#define REGNO_OK_FOR_FP_P(REGNO) \ 1403 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ 1404 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) 1405 1406#define REGNO_OK_FOR_CCFP_P(REGNO) \ 1407 (TARGET_V9 \ 1408 && (((unsigned) (REGNO) - 96 < (unsigned)4) \ 1409 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) 1410 1411/* Maximum number of registers that can appear in a valid memory address. */ 1412 1413#define MAX_REGS_PER_ADDRESS 2 1414 1415/* Recognize any constant value that is a valid address. 1416 When PIC, we do not accept an address that would require a scratch reg 1417 to load into a register. */ 1418 1419#define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1420 1421/* Define this, so that when PIC, reload won't try to reload invalid 1422 addresses which require two reload registers. */ 1423 1424#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1425 1426/* Should gcc use [%reg+%lo(xx)+offset] addresses? */ 1427 1428#ifdef HAVE_AS_OFFSETABLE_LO10 1429#define USE_AS_OFFSETABLE_LO10 1 1430#else 1431#define USE_AS_OFFSETABLE_LO10 0 1432#endif 1433 1434/* Try a machine-dependent way of reloading an illegitimate address 1435 operand. If we find one, push the reload and jump to WIN. This 1436 macro is used in only one place: `find_reloads_address' in reload.c. */ 1437#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1438do { \ 1439 int win; \ 1440 (X) = sparc_legitimize_reload_address ((X), (MODE), (OPNUM), \ 1441 (int)(TYPE), (IND_LEVELS), &win); \ 1442 if (win) \ 1443 goto WIN; \ 1444} while (0) 1445 1446/* Specify the machine mode that this machine uses 1447 for the index in the tablejump instruction. */ 1448/* If we ever implement any of the full models (such as CM_FULLANY), 1449 this has to be DImode in that case */ 1450#ifdef HAVE_GAS_SUBSECTION_ORDERING 1451#define CASE_VECTOR_MODE \ 1452(! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) 1453#else 1454/* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise 1455 we have to sign extend which slows things down. */ 1456#define CASE_VECTOR_MODE \ 1457(! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) 1458#endif 1459 1460/* Define this as 1 if `char' should by default be signed; else as 0. */ 1461#define DEFAULT_SIGNED_CHAR 1 1462 1463/* Max number of bytes we can move from memory to memory 1464 in one reasonably fast instruction. */ 1465#define MOVE_MAX 8 1466 1467/* If a memory-to-memory move would take MOVE_RATIO or more simple 1468 move-instruction pairs, we will do a movmem or libcall instead. */ 1469 1470#define MOVE_RATIO(speed) ((speed) ? 8 : 3) 1471 1472/* Define if operations between registers always perform the operation 1473 on the full register even if a narrower mode is specified. */ 1474#define WORD_REGISTER_OPERATIONS 1475 1476/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1477 will either zero-extend or sign-extend. The value of this macro should 1478 be the code that says which one of the two operations is implicitly 1479 done, UNKNOWN if none. */ 1480#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1481 1482/* Nonzero if access to memory by bytes is slow and undesirable. 1483 For RISC chips, it means that access to memory by bytes is no 1484 better than access by words when possible, so grab a whole word 1485 and maybe make use of that. */ 1486#define SLOW_BYTE_ACCESS 1 1487 1488/* Define this to be nonzero if shift instructions ignore all but the low-order 1489 few bits. */ 1490#define SHIFT_COUNT_TRUNCATED 1 1491 1492/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1493 is done just by pretending it is already truncated. */ 1494#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1495 1496/* For SImode, we make sure the top 32-bits of the register are clear and 1497 then we subtract 32 from the lzd instruction result. */ 1498#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1499 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) 1500 1501/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1502 return the mode to be used for the comparison. For floating-point, 1503 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand 1504 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 1505 processing is needed. */ 1506#define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) 1507 1508/* Return nonzero if MODE implies a floating point inequality can be 1509 reversed. For SPARC this is always true because we have a full 1510 compliment of ordered and unordered comparisons, but until generic 1511 code knows how to reverse it correctly we keep the old definition. */ 1512#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) 1513 1514/* A function address in a call instruction for indexing purposes. */ 1515#define FUNCTION_MODE Pmode 1516 1517/* Define this if addresses of constant functions 1518 shouldn't be put through pseudo regs where they can be cse'd. 1519 Desirable on machines where ordinary constants are expensive 1520 but a CALL with constant address is cheap. */ 1521#define NO_FUNCTION_CSE 1522 1523/* The _Q_* comparison libcalls return booleans. */ 1524#define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) 1525 1526/* Assume by default that the _Qp_* 64-bit libcalls are implemented such 1527 that the inputs are fully consumed before the output memory is clobbered. */ 1528 1529#define TARGET_BUGGY_QP_LIB 0 1530 1531/* Assume by default that we do not have the Solaris-specific conversion 1532 routines nor 64-bit integer multiply and divide routines. */ 1533 1534#define SUN_CONVERSION_LIBFUNCS 0 1535#define DITF_CONVERSION_LIBFUNCS 0 1536#define SUN_INTEGER_MULTIPLY_64 0 1537 1538/* Provide the cost of a branch. For pre-v9 processors we use 1539 a value of 3 to take into account the potential annulling of 1540 the delay slot (which ends up being a bubble in the pipeline slot) 1541 plus a cycle to take into consideration the instruction cache 1542 effects. 1543 1544 On v9 and later, which have branch prediction facilities, we set 1545 it to the depth of the pipeline as that is the cost of a 1546 mispredicted branch. 1547 1548 On Niagara, normal branches insert 3 bubbles into the pipe 1549 and annulled branches insert 4 bubbles. 1550 1551 On Niagara-2 and Niagara-3, a not-taken branch costs 1 cycle whereas 1552 a taken branch costs 6 cycles. */ 1553 1554#define BRANCH_COST(speed_p, predictable_p) \ 1555 ((sparc_cpu == PROCESSOR_V9 \ 1556 || sparc_cpu == PROCESSOR_ULTRASPARC) \ 1557 ? 7 \ 1558 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ 1559 ? 9 \ 1560 : (sparc_cpu == PROCESSOR_NIAGARA \ 1561 ? 4 \ 1562 : ((sparc_cpu == PROCESSOR_NIAGARA2 \ 1563 || sparc_cpu == PROCESSOR_NIAGARA3) \ 1564 ? 5 \ 1565 : 3)))) 1566 1567/* Control the assembler format that we output. */ 1568 1569/* A C string constant describing how to begin a comment in the target 1570 assembler language. The compiler assumes that the comment will end at 1571 the end of the line. */ 1572 1573#define ASM_COMMENT_START "!" 1574 1575/* Output to assembler file text saying following lines 1576 may contain character constants, extra white space, comments, etc. */ 1577 1578#define ASM_APP_ON "" 1579 1580/* Output to assembler file text saying following lines 1581 no longer contain unusual constructs. */ 1582 1583#define ASM_APP_OFF "" 1584 1585/* How to refer to registers in assembler output. 1586 This sequence is indexed by compiler's hard-register-number (see above). */ 1587 1588#define REGISTER_NAMES \ 1589{"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 1590 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 1591 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 1592 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 1593 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 1594 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 1595 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 1596 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ 1597 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ 1598 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ 1599 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ 1600 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ 1601 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp", "%gsr" } 1602 1603/* Define additional names for use in asm clobbers and asm declarations. */ 1604 1605#define ADDITIONAL_REGISTER_NAMES \ 1606{{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} 1607 1608/* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length 1609 can run past this up to a continuation point. Once we used 1500, but 1610 a single entry in C++ can run more than 500 bytes, due to the length of 1611 mangled symbol names. dbxout.c should really be fixed to do 1612 continuations when they are actually needed instead of trying to 1613 guess... */ 1614#define DBX_CONTIN_LENGTH 1000 1615 1616/* This is how to output a command to make the user-level label named NAME 1617 defined for reference from other files. */ 1618 1619/* Globalizing directive for a label. */ 1620#define GLOBAL_ASM_OP "\t.global " 1621 1622/* The prefix to add to user-visible assembler symbols. */ 1623 1624#define USER_LABEL_PREFIX "_" 1625 1626/* This is how to store into the string LABEL 1627 the symbol_ref name of an internal numbered label where 1628 PREFIX is the class of label and NUM is the number within the class. 1629 This is suitable for output with `assemble_name'. */ 1630 1631#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1632 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) 1633 1634/* This is how we hook in and defer the case-vector until the end of 1635 the function. */ 1636#define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ 1637 sparc_defer_case_vector ((LAB),(VEC), 0) 1638 1639#define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ 1640 sparc_defer_case_vector ((LAB),(VEC), 1) 1641 1642/* This is how to output an element of a case-vector that is absolute. */ 1643 1644#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1645do { \ 1646 char label[30]; \ 1647 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1648 if (CASE_VECTOR_MODE == SImode) \ 1649 fprintf (FILE, "\t.word\t"); \ 1650 else \ 1651 fprintf (FILE, "\t.xword\t"); \ 1652 assemble_name (FILE, label); \ 1653 fputc ('\n', FILE); \ 1654} while (0) 1655 1656/* This is how to output an element of a case-vector that is relative. 1657 (SPARC uses such vectors only when generating PIC.) */ 1658 1659#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1660do { \ 1661 char label[30]; \ 1662 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ 1663 if (CASE_VECTOR_MODE == SImode) \ 1664 fprintf (FILE, "\t.word\t"); \ 1665 else \ 1666 fprintf (FILE, "\t.xword\t"); \ 1667 assemble_name (FILE, label); \ 1668 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ 1669 fputc ('-', FILE); \ 1670 assemble_name (FILE, label); \ 1671 fputc ('\n', FILE); \ 1672} while (0) 1673 1674/* This is what to output before and after case-vector (both 1675 relative and absolute). If .subsection -1 works, we put case-vectors 1676 at the beginning of the current section. */ 1677 1678#ifdef HAVE_GAS_SUBSECTION_ORDERING 1679 1680#define ASM_OUTPUT_ADDR_VEC_START(FILE) \ 1681 fprintf(FILE, "\t.subsection\t-1\n") 1682 1683#define ASM_OUTPUT_ADDR_VEC_END(FILE) \ 1684 fprintf(FILE, "\t.previous\n") 1685 1686#endif 1687 1688/* This is how to output an assembler line 1689 that says to advance the location counter 1690 to a multiple of 2**LOG bytes. */ 1691 1692#define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1693 if ((LOG) != 0) \ 1694 fprintf (FILE, "\t.align %d\n", (1<<(LOG))) 1695 1696#define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1697 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 1698 1699/* This says how to output an assembler line 1700 to define a global common symbol. */ 1701 1702#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1703( fputs ("\t.common ", (FILE)), \ 1704 assemble_name ((FILE), (NAME)), \ 1705 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) 1706 1707/* This says how to output an assembler line to define a local common 1708 symbol. */ 1709 1710#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ 1711( fputs ("\t.reserve ", (FILE)), \ 1712 assemble_name ((FILE), (NAME)), \ 1713 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ 1714 (SIZE), ((ALIGNED) / BITS_PER_UNIT))) 1715 1716/* A C statement (sans semicolon) to output to the stdio stream 1717 FILE the assembler definition of uninitialized global DECL named 1718 NAME whose size is SIZE bytes and alignment is ALIGN bytes. 1719 Try to use asm_output_aligned_bss to implement this macro. */ 1720 1721#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 1722 do { \ 1723 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ 1724 } while (0) 1725 1726/* Output #ident as a .ident. */ 1727 1728#undef TARGET_ASM_OUTPUT_IDENT 1729#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive 1730 1731/* Prettify the assembly. */ 1732 1733extern int sparc_indent_opcode; 1734 1735#define ASM_OUTPUT_OPCODE(FILE, PTR) \ 1736 do { \ 1737 if (sparc_indent_opcode) \ 1738 { \ 1739 putc (' ', FILE); \ 1740 sparc_indent_opcode = 0; \ 1741 } \ 1742 } while (0) 1743 1744/* TLS support defaulting to original Sun flavor. GNU extensions 1745 must be activated in separate configuration files. */ 1746#ifdef HAVE_AS_TLS 1747#define TARGET_TLS 1 1748#else 1749#define TARGET_TLS 0 1750#endif 1751 1752#define TARGET_SUN_TLS TARGET_TLS 1753#define TARGET_GNU_TLS 0 1754 1755#ifdef HAVE_AS_FMAF_HPC_VIS3 1756#define AS_NIAGARA3_FLAG "d" 1757#else 1758#define AS_NIAGARA3_FLAG "b" 1759#endif 1760 1761#ifdef HAVE_AS_SPARC4 1762#define AS_NIAGARA4_FLAG "-xarch=sparc4" 1763#else 1764#define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG 1765#endif 1766 1767#ifdef HAVE_AS_LEON 1768#define AS_LEON_FLAG "-Aleon" 1769#define AS_LEONV7_FLAG "-Aleon" 1770#else 1771#define AS_LEON_FLAG "-Av8" 1772#define AS_LEONV7_FLAG "-Av7" 1773#endif 1774 1775/* We use gcc _mcount for profiling. */ 1776#define NO_PROFILE_COUNTERS 0 1777 1778/* Debug support */ 1779#define MASK_DEBUG_OPTIONS 0x01 /* debug option handling */ 1780#define MASK_DEBUG_ALL MASK_DEBUG_OPTIONS 1781 1782#define TARGET_DEBUG_OPTIONS (sparc_debug & MASK_DEBUG_OPTIONS) 1783 1784/* By default, use the weakest memory model for the cpu. */ 1785#ifndef SUBTARGET_DEFAULT_MEMORY_MODEL 1786#define SUBTARGET_DEFAULT_MEMORY_MODEL SMM_DEFAULT 1787#endif 1788 1789/* Define this to 1 if the FE_EXCEPT values defined in fenv.h start at 1. */ 1790#define SPARC_LOW_FE_EXCEPT_VALUES 0 1791