1;; Constraint definitions for MIPS.
2;; Copyright (C) 2006-2015 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify
7;; it under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 3, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful,
12;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14;; GNU General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING3.  If not see
18;; <http://www.gnu.org/licenses/>.
19
20;; Register constraints
21
22(define_register_constraint "d" "TARGET_MIPS16 ? M16_REGS : GR_REGS"
23  "An address register.  This is equivalent to @code{r} unless
24   generating MIPS16 code.")
25
26(define_register_constraint "t" "T_REG"
27  "@internal")
28
29(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
30  "A floating-point register (if available).")
31
32(define_register_constraint "h" "NO_REGS"
33  "Formerly the @code{hi} register.  This constraint is no longer supported.")
34
35(define_register_constraint "l" "TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG"
36  "The @code{lo} register.  Use this register to store values that are
37   no bigger than a word.")
38
39(define_register_constraint "x" "MD_REGS"
40  "The concatenated @code{hi} and @code{lo} registers.  Use this register
41   to store doubleword values.")
42
43(define_register_constraint "b" "ALL_REGS"
44  "@internal")
45
46(define_register_constraint "u" "M16_REGS"
47  "@internal")
48
49;; MIPS16 code always calls through a MIPS16 register; see mips_emit_call_insn
50;; for details.
51(define_register_constraint "c" "TARGET_MIPS16 ? M16_REGS
52				 : TARGET_USE_PIC_FN_ADDR_REG ? PIC_FN_ADDR_REG
53				 : GR_REGS"
54  "A register suitable for use in an indirect jump.  This will always be
55   @code{$25} for @option{-mabicalls}.")
56
57(define_register_constraint "e" "LEA_REGS"
58  "@internal")
59
60(define_register_constraint "j" "PIC_FN_ADDR_REG"
61  "@internal")
62
63;; Don't use this constraint in gcc code!  It runs the risk of
64;; introducing a spill failure; see tls_get_tp_<mode>.
65(define_register_constraint "v" "V1_REG"
66  "Register @code{$3}.  Do not use this constraint in new code;
67   it is retained only for compatibility with glibc.")
68
69(define_register_constraint "y" "GR_REGS"
70  "Equivalent to @code{r}; retained for backwards compatibility.")
71
72(define_register_constraint "z" "ST_REGS"
73  "A floating-point condition code register.")
74
75(define_register_constraint "A" "DSP_ACC_REGS"
76  "@internal")
77
78(define_register_constraint "a" "ACC_REGS"
79  "@internal")
80
81(define_register_constraint "B" "COP0_REGS"
82  "@internal")
83
84(define_register_constraint "C" "COP2_REGS"
85  "@internal")
86
87(define_register_constraint "D" "COP3_REGS"
88  "@internal")
89
90;; Registers that can be used as the target of multiply-accumulate
91;; instructions.  The core MIPS32 ISA provides a hi/lo madd,
92;; but the DSP version allows any accumulator target.
93(define_register_constraint "ka" "ISA_HAS_DSP_MULT ? ACC_REGS : MD_REGS")
94
95(define_register_constraint "kb" "M16_STORE_REGS"
96  "@internal")
97
98(define_constraint "kf"
99  "@internal"
100  (match_operand 0 "force_to_mem_operand"))
101
102;; This is a normal rather than a register constraint because we can
103;; never use the stack pointer as a reload register.
104(define_constraint "ks"
105  "@internal"
106  (and (match_code "reg")
107       (match_test "REGNO (op) == STACK_POINTER_REGNUM")))
108
109;; Integer constraints
110
111(define_constraint "I"
112  "A signed 16-bit constant (for arithmetic instructions)."
113  (and (match_code "const_int")
114       (match_test "SMALL_OPERAND (ival)")))
115
116(define_constraint "J"
117  "Integer zero."
118  (and (match_code "const_int")
119       (match_test "ival == 0")))
120
121(define_constraint "K"
122  "An unsigned 16-bit constant (for logic instructions)."
123  (and (match_code "const_int")
124       (match_test "SMALL_OPERAND_UNSIGNED (ival)")))
125 
126(define_constraint "L"
127  "A signed 32-bit constant in which the lower 16 bits are zero.
128   Such constants can be loaded using @code{lui}."
129  (and (match_code "const_int")
130       (match_test "LUI_OPERAND (ival)")))
131
132(define_constraint "M"
133  "A constant that cannot be loaded using @code{lui}, @code{addiu}
134   or @code{ori}."
135  (and (match_code "const_int")
136       (not (match_test "SMALL_OPERAND (ival)"))
137       (not (match_test "SMALL_OPERAND_UNSIGNED (ival)"))
138       (not (match_test "LUI_OPERAND (ival)"))))
139
140(define_constraint "N"
141  "A constant in the range -65535 to -1 (inclusive)."
142  (and (match_code "const_int")
143       (match_test "ival >= -0xffff && ival < 0")))
144
145(define_constraint "O"
146  "A signed 15-bit constant."
147  (and (match_code "const_int")
148       (match_test "ival >= -0x4000 && ival < 0x4000")))
149
150(define_constraint "P"
151  "A constant in the range 1 to 65535 (inclusive)."
152  (and (match_code "const_int")
153       (match_test "ival > 0 && ival < 0x10000")))
154
155;; Floating-point constraints
156
157(define_constraint "G"
158  "Floating-point zero."
159  (and (match_code "const_double")
160       (match_test "op == CONST0_RTX (mode)")))
161
162;; General constraints
163
164(define_constraint "Q"
165  "@internal"
166  (match_operand 0 "const_arith_operand"))
167
168(define_memory_constraint "R"
169  "An address that can be used in a non-macro load or store."
170  (and (match_code "mem")
171       (match_test "mips_address_insns (XEXP (op, 0), mode, false) == 1")))
172
173(define_constraint "S"
174  "@internal
175   A constant call address."
176  (and (match_operand 0 "call_insn_operand")
177       (match_test "CONSTANT_P (op)")))
178
179(define_constraint "Udb7"
180  "@internal
181   A decremented unsigned constant of 7 bits."
182  (match_operand 0 "db7_operand"))
183
184(define_constraint "Udb8"
185  "@internal
186   A decremented unsigned constant of 8 bits."
187  (match_operand 0 "db8_operand"))
188
189(define_constraint "Uead"
190  "@internal
191   A microMIPS encoded ADDIUR2 immediate operand."
192  (match_operand 0 "addiur2_operand"))
193  
194(define_constraint "Uean"
195  "@internal
196   A microMIPS encoded ANDI operand."
197  (match_operand 0 "andi16_operand"))
198
199(define_constraint "Uesp"
200  "@internal
201   A microMIPS encoded ADDIUSP operand."
202  (match_operand 0 "addiusp_operand"))
203
204(define_constraint "Uib3"
205  "@internal
206   An unsigned, incremented constant of 3 bits."
207  (match_operand 0 "ib3_operand"))
208
209(define_constraint "Usb4"
210  "@internal
211   A signed constant of 4 bits."
212  (match_operand 0 "sb4_operand"))
213
214(define_constraint "Usb5"
215  "@internal
216   A signed constant of 5 bits."
217  (match_operand 0 "sb5_operand"))
218
219(define_constraint "Usb8"
220  "@internal
221   A signed constant of 8 bits."
222  (match_operand 0 "sb8_operand"))
223
224(define_constraint "Usd8"
225  "@internal
226   A signed constant of 8 bits, shifted left three places."
227  (match_operand 0 "sd8_operand"))
228
229(define_constraint "Uub8"
230  "@internal
231   An unsigned constant of 8 bits."
232  (match_operand 0 "ub8_operand"))
233
234(define_constraint "Uuw5"
235  "@internal
236   An unsigned constant of 5 bits, shifted left two places."
237  (match_operand 0 "uw5_operand"))
238
239(define_constraint "Uuw6"
240  "@internal
241   An unsigned constant of 6 bits, shifted left two places."
242  (match_operand 0 "uw6_operand"))
243
244(define_constraint "Uuw8"
245  "@internal
246   An unsigned constant of 8 bits, shifted left two places."
247  (match_operand 0 "uw8_operand"))
248
249(define_memory_constraint "W"
250  "@internal
251   A memory address based on a member of @code{BASE_REG_CLASS}.  This is
252   true for all non-mips16 references (although it can sometimes be implicit
253   if @samp{!TARGET_EXPLICIT_RELOCS}).  For MIPS16, it excludes stack and
254   constant-pool references."
255  (and (match_code "mem")
256       (match_operand 0 "memory_operand")
257       (ior (not (match_test "TARGET_MIPS16"))
258	    (and (not (match_operand 0 "stack_operand"))
259		 (not (match_test "CONSTANT_P (XEXP (op, 0))"))))))
260
261(define_constraint "YG"
262  "@internal
263   A vector zero."
264  (and (match_code "const_vector")
265       (match_test "op == CONST0_RTX (mode)")))
266
267(define_constraint "YA"
268  "@internal
269   An unsigned 6-bit constant."
270  (and (match_code "const_int")
271       (match_test "UIMM6_OPERAND (ival)")))
272
273(define_constraint "YB"
274  "@internal
275   A signed 10-bit constant."
276  (and (match_code "const_int")
277       (match_test "IMM10_OPERAND (ival)")))
278
279(define_constraint "Yb"
280   "@internal"
281   (match_operand 0 "qi_mask_operand"))
282
283(define_constraint "Yd"
284  "@internal
285   A constant @code{move_operand} that can be safely loaded into @code{$25}
286   using @code{la}."
287  (and (match_operand 0 "move_operand")
288       (match_test "CONSTANT_P (op)")
289       (not (match_test "mips_dangerous_for_la25_p (op)"))))
290
291(define_constraint "Yf"
292  "@internal
293   A constant @code{move_operand} that cannot be safely loaded into @code{$25}
294   using @code{la}."
295  (and (match_operand 0 "move_operand")
296       (match_test "CONSTANT_P (op)")
297       (match_test "mips_dangerous_for_la25_p (op)")))
298
299(define_constraint "Yh"
300   "@internal"
301    (match_operand 0 "hi_mask_operand"))
302
303(define_constraint "Yw"
304   "@internal"
305    (match_operand 0 "si_mask_operand"))
306
307(define_constraint "Yx"
308   "@internal"
309   (match_operand 0 "low_bitmask_operand"))
310
311(define_memory_constraint "ZC"
312  "A memory operand whose address is formed by a base register and offset
313   that is suitable for use in instructions with the same addressing mode
314   as @code{ll} and @code{sc}."
315  (and (match_code "mem")
316       (if_then_else
317	 (match_test "TARGET_MICROMIPS")
318	 (match_test "umips_12bit_offset_address_p (XEXP (op, 0), mode)")
319	 (if_then_else (match_test "ISA_HAS_9BIT_DISPLACEMENT")
320	   (match_test "mips_9bit_offset_address_p (XEXP (op, 0), mode)")
321	   (match_test "mips_address_insns (XEXP (op, 0), mode, false)")))))
322
323(define_address_constraint "ZD"
324  "An address suitable for a @code{prefetch} instruction, or for any other
325   instruction with the same addressing mode as @code{prefetch}."
326   (if_then_else (match_test "TARGET_MICROMIPS")
327		 (match_test "umips_12bit_offset_address_p (op, mode)")
328	  (if_then_else (match_test "ISA_HAS_9BIT_DISPLACEMENT")
329			(match_test "mips_9bit_offset_address_p (op, mode)")
330			(match_test "mips_address_insns (op, mode, false)"))))
331
332(define_memory_constraint "ZR"
333 "@internal
334  An address valid for loading/storing register exclusive"
335 (match_operand 0 "mem_noofs_operand"))
336
337(define_memory_constraint "ZS"
338  "@internal
339   A microMIPS memory operand for use with the LWSP/SWSP insns."
340  (and (match_code "mem")
341       (match_operand 0 "lwsp_swsp_operand")))
342
343(define_memory_constraint "ZT"
344  "@internal
345   A microMIPS memory operand for use with the LW16/SW16 insns."
346  (and (match_code "mem")
347       (match_operand 0 "lw16_sw16_operand")))
348
349(define_memory_constraint "ZU"
350  "@internal
351   A microMIPS memory operand for use with the LHU16/SH16 insns."
352  (and (match_code "mem")
353       (match_operand 0 "lhu16_sh16_operand")))
354
355(define_memory_constraint "ZV"
356  "@internal
357   A microMIPS memory operand for use with the SB16 insn."
358  (and (match_code "mem")
359       (match_operand 0 "sb16_operand")))
360
361(define_memory_constraint "ZW"
362  "@internal
363   A microMIPS memory operand for use with the LBU16 insn."
364  (and (match_code "mem")
365       (match_operand 0 "lbu16_operand")))
366
367