1;; Copyright (C) 2002-2015 Free Software Foundation, Inc. 2;; 3;; This file is part of GCC. 4;; 5;; GCC is free software; you can redistribute it and/or modify 6;; it under the terms of the GNU General Public License as published by 7;; the Free Software Foundation; either version 3, or (at your option) 8;; any later version. 9;; 10;; GCC is distributed in the hope that it will be useful, 11;; but WITHOUT ANY WARRANTY; without even the implied warranty of 12;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13;; GNU General Public License for more details. 14;; 15;; You should have received a copy of the GNU General Public License 16;; along with GCC; see the file COPYING3. If not see 17;; <http://www.gnu.org/licenses/>. 18;; 19;; DFA-based pipeline description for 5500 20(define_automaton "vr55") 21(define_cpu_unit "vr55_dp0" "vr55") 22(define_cpu_unit "vr55_dp1" "vr55") 23(define_cpu_unit "vr55_mem" "vr55") 24(define_cpu_unit "vr55_mac" "vr55") 25(define_cpu_unit "vr55_fp" "vr55") 26(define_cpu_unit "vr55_bru" "vr55") 27 28;; 29;; The ordering of the instruction-execution-path/resource-usage 30;; descriptions (also known as reservation RTL) is roughly ordered 31;; based on the define attribute RTL for the "type" classification. 32;; When modifying, remember that the first test that matches is the 33;; reservation used! 34;; 35 36(define_insn_reservation "ir_vr55_unknown" 1 37 (and (eq_attr "cpu" "r5500") 38 (eq_attr "type" "unknown,atomic,syncloop")) 39 "vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru") 40 41;; Assume prediction fails. 42(define_insn_reservation "ir_vr55_branch" 2 43 (and (eq_attr "cpu" "r5500") 44 (eq_attr "type" "branch,jump,call")) 45 "vr55_bru") 46 47(define_insn_reservation "ir_vr55_load" 3 48 (and (eq_attr "cpu" "r5500") 49 (eq_attr "type" "load,fpload,fpidxload")) 50 "vr55_mem") 51 52(define_bypass 4 53 "ir_vr55_load" 54 "ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd, 55 ir_vr55_idiv_si,ir_vr55_idiv_di") 56 57(define_insn_reservation "ir_vr55_store" 0 58 (and (eq_attr "cpu" "r5500") 59 (eq_attr "type" "store,fpstore,fpidxstore")) 60 "vr55_mem") 61 62;; This reservation is for conditional move based on integer 63;; or floating point CC. 64(define_insn_reservation "ir_vr55_condmove" 2 65 (and (eq_attr "cpu" "r5500") 66 (eq_attr "type" "condmove")) 67 "vr55_dp0|vr55_dp1") 68 69;; Move to/from FPU registers 70(define_insn_reservation "ir_vr55_xfer" 2 71 (and (eq_attr "cpu" "r5500") 72 (eq_attr "type" "mfc,mtc")) 73 "vr55_dp0|vr55_dp1") 74 75(define_insn_reservation "ir_vr55_arith" 1 76 (and (eq_attr "cpu" "r5500") 77 (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,nop,trap")) 78 "vr55_dp0|vr55_dp1") 79 80(define_bypass 2 81 "ir_vr55_arith" 82 "ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd, 83 ir_vr55_idiv_si,ir_vr55_idiv_di") 84 85(define_insn_reservation "ir_vr55_mthilo" 1 86 (and (eq_attr "cpu" "r5500") 87 (eq_attr "type" "mthi,mtlo")) 88 "vr55_mac") 89 90(define_insn_reservation "ir_vr55_mfhilo" 5 91 (and (eq_attr "cpu" "r5500") 92 (eq_attr "type" "mfhi,mflo")) 93 "vr55_mac") 94 95;; The default latency is for the GPR result of a mul. Bypasses handle the 96;; latency of {mul,mult}->{mfhi,mflo}. 97(define_insn_reservation "ir_vr55_imul_si" 5 98 (and (eq_attr "cpu" "r5500") 99 (and (eq_attr "type" "imul,imul3") 100 (eq_attr "mode" "SI"))) 101 "vr55_mac") 102 103;; The default latency is for pre-reload scheduling and handles the case 104;; where a pseudo destination will be stored in a GPR (as it usually is). 105;; The delay includes the latency of the dmult itself and the anticipated 106;; mflo or mfhi. 107;; 108;; Once the mflo or mfhi has been created, bypasses handle the latency 109;; between it and the dmult. 110(define_insn_reservation "ir_vr55_imul_di" 9 111 (and (eq_attr "cpu" "r5500") 112 (and (eq_attr "type" "imul,imul3") 113 (eq_attr "mode" "DI"))) 114 "vr55_mac*4") 115 116;; The default latency is as for ir_vr55_imul_si. 117(define_insn_reservation "ir_vr55_imadd" 5 118 (and (eq_attr "cpu" "r5500") 119 (eq_attr "type" "imadd")) 120 "vr55_mac") 121 122(define_bypass 1 123 "ir_vr55_imul_si,ir_vr55_imadd" 124 "ir_vr55_imadd" 125 "mips_linked_madd_p") 126 127(define_bypass 2 128 "ir_vr55_imul_si,ir_vr55_imadd" 129 "ir_vr55_mfhilo") 130 131(define_bypass 4 132 "ir_vr55_imul_di" 133 "ir_vr55_mfhilo") 134 135;; Divide algorithm is early out with best latency of 7 pcycles. 136;; Use worst case for scheduling purposes. 137(define_insn_reservation "ir_vr55_idiv_si" 42 138 (and (eq_attr "cpu" "r5500") 139 (and (eq_attr "type" "idiv") 140 (eq_attr "mode" "SI"))) 141 "vr55_mac") 142 143(define_insn_reservation "ir_vr55_idiv_di" 74 144 (and (eq_attr "cpu" "r5500") 145 (and (eq_attr "type" "idiv") 146 (eq_attr "mode" "DI"))) 147 "vr55_mac") 148 149(define_insn_reservation "ir_vr55_fadd" 4 150 (and (eq_attr "cpu" "r5500") 151 (eq_attr "type" "fadd")) 152 "vr55_fp") 153 154(define_insn_reservation "ir_vr55_fmul_sf" 5 155 (and (eq_attr "cpu" "r5500") 156 (and (eq_attr "type" "fmul") 157 (eq_attr "mode" "SF"))) 158 "vr55_mac") 159 160(define_insn_reservation "ir_vr55_fmul_df" 6 161 (and (eq_attr "cpu" "r5500") 162 (and (eq_attr "type" "fmul") 163 (eq_attr "mode" "DF"))) 164 "vr55_mac") 165 166(define_insn_reservation "ir_vr55_fmadd_sf" 9 167 (and (eq_attr "cpu" "r5500") 168 (and (eq_attr "type" "fmadd") 169 (eq_attr "mode" "SF"))) 170 "vr55_mac") 171 172(define_insn_reservation "ir_vr55_fmadd_df" 10 173 (and (eq_attr "cpu" "r5500") 174 (and (eq_attr "type" "fmadd") 175 (eq_attr "mode" "DF"))) 176 "vr55_mac") 177 178(define_insn_reservation "ir_vr55_fdiv_sf" 30 179 (and (eq_attr "cpu" "r5500") 180 (and (eq_attr "type" "fdiv,frdiv,fsqrt") 181 (eq_attr "mode" "SF"))) 182 "vr55_mac") 183 184(define_insn_reservation "ir_vr55_fdiv_df" 59 185 (and (eq_attr "cpu" "r5500") 186 (and (eq_attr "type" "fdiv,frdiv,fsqrt") 187 (eq_attr "mode" "DF"))) 188 "vr55_mac") 189 190(define_insn_reservation "ir_vr55_fabs" 2 191 (and (eq_attr "cpu" "r5500") 192 (eq_attr "type" "fabs,fneg,fmove")) 193 "vr55_fp") 194 195(define_insn_reservation "ir_vr55_fcmp" 2 196 (and (eq_attr "cpu" "r5500") 197 (eq_attr "type" "fcmp")) 198 "vr55_fp") 199 200(define_insn_reservation "ir_vr55_fcvt_sf" 4 201 (and (eq_attr "cpu" "r5500") 202 (and (eq_attr "type" "fcvt") 203 (eq_attr "mode" "SF"))) 204 "vr55_fp") 205 206(define_insn_reservation "ir_vr55_fcvt_df" 6 207 (and (eq_attr "cpu" "r5500") 208 (and (eq_attr "type" "fcvt") 209 (eq_attr "mode" "DF"))) 210 "vr55_fp") 211 212(define_insn_reservation "ir_vr55_frsqrt_sf" 60 213 (and (eq_attr "cpu" "r5500") 214 (and (eq_attr "type" "frsqrt") 215 (eq_attr "mode" "SF"))) 216 "vr55_mac") 217 218(define_insn_reservation "ir_vr55_frsqrt_df" 118 219 (and (eq_attr "cpu" "r5500") 220 (and (eq_attr "type" "frsqrt") 221 (eq_attr "mode" "DF"))) 222 "vr55_mac") 223 224(define_insn_reservation "ir_vr55_multi" 1 225 (and (eq_attr "cpu" "r5500") 226 (eq_attr "type" "multi")) 227 "vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru") 228