1;; DFA-based pipeline descriptions for MIPS32 4K processor family
2;; Contributed by Nigel Stephens (nigel@mips.com)
3;;   and David Ung (davidu@mips.com)
4;;
5;; References:
6;;   "MIPS32 4K Processor Core Family Software User's Manual,
7;;     Doc no: MD00016, Rev 1.18, Nov 15, 2004."
8;;
9;; 4Kc - pipelined multiplier and translation lookaside buffer (TLB)
10;; 4km - pipelined multiplier and block address translator (BAT)
11;; 4kp - non-pipelined multiplier and block address translator (BAT)
12;;
13;; Copyright (C) 2005-2015 Free Software Foundation, Inc.
14;;
15;; This file is part of GCC.
16;;
17;; GCC is free software; you can redistribute it and/or modify it
18;; under the terms of the GNU General Public License as published
19;; by the Free Software Foundation; either version 3, or (at your
20;; option) any later version.
21
22;; GCC is distributed in the hope that it will be useful, but WITHOUT
23;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
25;; License for more details.
26
27;; You should have received a copy of the GNU General Public License
28;; along with GCC; see the file COPYING3.  If not see
29;; <http://www.gnu.org/licenses/>.
30
31(define_automaton "r4k_cpu, r4k_mdu")
32
33;; Integer execution unit.
34(define_cpu_unit "r4k_ixu_arith"       "r4k_cpu")
35(define_cpu_unit "r4k_ixu_mpydiv"      "r4k_mdu")
36
37(define_insn_reservation "r4k_int_load" 2
38  (and (eq_attr "cpu" "4kc,4kp")
39       (eq_attr "type" "load"))
40  "r4k_ixu_arith")
41
42(define_insn_reservation "r4k_int_prefetch" 1
43  (and (eq_attr "cpu" "4kc,4kp")
44       (eq_attr "type" "prefetch"))
45  "r4k_ixu_arith")
46
47(define_insn_reservation "r4k_int_store" 1
48  (and (eq_attr "cpu" "4kc,4kp")
49       (eq_attr "type" "store"))
50  "r4k_ixu_arith")
51
52;; 4Kc/4Km 
53;; unsigned divide - 8/16/24/32-bit operand have latencies  9/17/25/33
54;;   signed divide - 8/16/24/32-bit operand have latencies 10/18/26/34
55(define_insn_reservation "r4k_idiv_4kc" 34
56  (and (eq_attr "cpu" "4kc")
57       (and (eq_attr "type" "idiv")
58	    (eq_attr "mode" "!DI")))
59  "r4k_ixu_arith+(r4k_ixu_mpydiv*34)")
60
61;; 4Kp
62;; unsigned divide - 33
63;;   signed divide - 33-35
64(define_insn_reservation "r4k_idiv_4kp" 35
65  (and (eq_attr "cpu" "4kp")
66       (and (eq_attr "type" "idiv")
67	    (eq_attr "mode" "!DI")))
68  "r4k_ixu_arith+(r4k_ixu_mpydiv*35)")
69
70;; 4Kc/4Km fast 32x32 multiply
71;; 16x32 is faster, but there's no way to detect this
72(define_insn_reservation "r4k_mult_4kc" 2
73  (and (eq_attr "cpu" "4kc")
74       (and (eq_attr "type" "imul,imadd")
75	    (eq_attr "mode" "SI")))
76  "r4k_ixu_arith+(r4k_ixu_mpydiv*2)")
77
78;; 4Kc/4Km MUL has 2 cycle latency, but has the special property that it will
79;; stall the integer unit pipeline. MUL 16x16 or 32x16 forces 1 cycle stall,
80;; while MUL 32x32 forces 2 cycle stall.  If next insn use the result, an
81;; additional stall is forced.
82(define_insn_reservation "r4k_mul_4kc" 4
83  (and (eq_attr "cpu" "4kc")
84       (and (eq_attr "type" "imul3")
85	    (eq_attr "mode" "SI")))
86  "(r4k_ixu_arith+r4k_ixu_mpydiv)*3")
87
88;; 4Kp slow iterative 2-op MULT
89;; Latency of 32 if next insn is MADD/MSUB,MFHI/MFLO.
90;; Repeat rate of 33 cycles.
91(define_insn_reservation "r4k_mult_4kp" 32
92  (and (eq_attr "cpu" "4kp")
93       (and (eq_attr "type" "imul")
94	    (eq_attr "mode" "SI")))
95  "r4k_ixu_arith+(r4k_ixu_mpydiv*32)")
96
97;; 4Kp slow iterative 3-op MUL
98;; Latency of 32 cycles, but stalls the whole pipeline until complete.
99(define_insn_reservation "r4k_mul_4kp" 32
100  (and (eq_attr "cpu" "4kp")
101       (and (eq_attr "type" "imul3")
102	    (eq_attr "mode" "SI")))
103  "(r4k_ixu_arith+r4k_ixu_mpydiv)*32")
104
105;; 4Kp slow iterative MADD
106;; Latency of 34 if next use insn is MADD/MSUB,MFHI/MFLO.
107;; Repeat rate of 35 cycles.
108(define_insn_reservation "r4k_madd_4kp" 34
109  (and (eq_attr "cpu" "4kp")
110       (and (eq_attr "type" "imadd")
111	    (eq_attr "mode" "SI")))
112  "r4k_ixu_arith+(r4k_ixu_mpydiv*34)")
113
114;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
115(define_insn_reservation "r4k_int_mthilo" 1
116  (and (eq_attr "cpu" "4kc,4kp")
117       (eq_attr "type" "mthi,mtlo"))
118  "r4k_ixu_arith+r4k_ixu_mpydiv")
119
120;; Move from HI/LO -> integer operation has a 2 cycle latency.
121(define_insn_reservation "r4k_int_mfhilo" 2
122  (and (eq_attr "cpu" "4kc,4kp")
123       (eq_attr "type" "mfhi,mflo"))
124  "r4k_ixu_arith+r4k_ixu_mpydiv")
125
126;; All other integer insns.
127(define_insn_reservation "r4k_int_alu" 1
128  (and (eq_attr "cpu" "4kc,4kp")
129       (eq_attr "type" "arith,condmove,const,logical,move,nop,shift,signext,slt"))
130  "r4k_ixu_arith")
131
132(define_insn_reservation "r4k_int_branch" 1
133  (and (eq_attr "cpu" "4kc,4kp")
134       (eq_attr "type" "branch"))
135  "r4k_ixu_arith")
136
137(define_insn_reservation "r4k_int_jump_4k" 1
138  (and (eq_attr "cpu" "4kc,4kp")
139       (eq_attr "type" "jump,call"))
140  "r4k_ixu_arith")
141
142;; mfcx/mtcx - non FPU
143;; (Disabled until we add cop0 support)
144;; (define_insn_reservation "r4k_int_cop" 2
145;;   (and (eq_attr "cpu" "4kc,4kp")
146;;      (eq_attr "type" "cop0"))
147;;  "r4k_ixu_arith")
148
149;; Unknown or multi - single issue
150(define_insn_reservation "r4k_unknown" 1
151  (and (eq_attr "cpu" "4kc,4kp")
152       (eq_attr "type" "unknown,multi,atomic,syncloop"))
153  "r4k_ixu_arith+r4k_ixu_mpydiv")
154