1;; R4600, R4650, and R4700 pipeline description. 2;; Copyright (C) 2004-2015 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5 6;; GCC is free software; you can redistribute it and/or modify it 7;; under the terms of the GNU General Public License as published 8;; by the Free Software Foundation; either version 3, or (at your 9;; option) any later version. 10 11;; GCC is distributed in the hope that it will be useful, but WITHOUT 12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14;; License for more details. 15 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20 21;; This file overrides parts of generic.md. It is derived from the 22;; old define_function_unit description. 23;; 24;; We handle the R4600, R4650, and R4700 in much the same way. The only 25;; differences between R4600 and R4650 are the integer multiplication and 26;; division costs. The only differences between R4600 and R4700 are the 27;; integer and floating-point multiplication costs. 28 29(define_insn_reservation "r4600_imul_si" 10 30 (and (eq_attr "cpu" "r4600") 31 (eq_attr "type" "imul,imul3,imadd") 32 (eq_attr "mode" "SI")) 33 "imuldiv*10") 34 35(define_insn_reservation "r4600_imul_di" 12 36 (and (eq_attr "cpu" "r4600") 37 (eq_attr "type" "imul,imul3,imadd") 38 (eq_attr "mode" "DI")) 39 "imuldiv*12") 40 41(define_insn_reservation "r4600_idiv_si" 42 42 (and (eq_attr "cpu" "r4600,r4700") 43 (eq_attr "type" "idiv") 44 (eq_attr "mode" "SI")) 45 "imuldiv*42") 46 47(define_insn_reservation "r4600_idiv_di" 74 48 (and (eq_attr "cpu" "r4600,r4700") 49 (eq_attr "type" "idiv") 50 (eq_attr "mode" "DI")) 51 "imuldiv*74") 52 53 54(define_insn_reservation "r4650_imul" 4 55 (and (eq_attr "cpu" "r4650") 56 (eq_attr "type" "imul,imul3,imadd")) 57 "imuldiv*4") 58 59(define_insn_reservation "r4650_idiv" 36 60 (and (eq_attr "cpu" "r4650") 61 (eq_attr "type" "idiv")) 62 "imuldiv*36") 63 64 65(define_insn_reservation "r4700_imul_si" 8 66 (and (eq_attr "cpu" "r4700") 67 (eq_attr "type" "imul,imul3,imadd") 68 (eq_attr "mode" "SI")) 69 "imuldiv*8") 70 71(define_insn_reservation "r4700_imul_di" 10 72 (and (eq_attr "cpu" "r4700") 73 (eq_attr "type" "imul,imul3,imadd") 74 (eq_attr "mode" "DI")) 75 "imuldiv*10") 76 77 78(define_insn_reservation "r4600_load" 2 79 (and (eq_attr "cpu" "r4600,r4650,r4700") 80 (eq_attr "type" "load,fpload,fpidxload")) 81 "alu") 82 83(define_insn_reservation "r4600_fmove" 1 84 (and (eq_attr "cpu" "r4600,r4650,r4700") 85 (eq_attr "type" "fabs,fneg,fmove")) 86 "alu") 87 88(define_insn_reservation "r4600_fmul_single" 8 89 (and (eq_attr "cpu" "r4600,r4650") 90 (and (eq_attr "type" "fmul,fmadd") 91 (eq_attr "mode" "SF"))) 92 "alu") 93 94 95(define_insn_reservation "r4700_fmul_single" 4 96 (and (eq_attr "cpu" "r4700") 97 (and (eq_attr "type" "fmul,fmadd") 98 (eq_attr "mode" "SF"))) 99 "alu") 100 101(define_insn_reservation "r4700_fmul_double" 5 102 (and (eq_attr "cpu" "r4700") 103 (and (eq_attr "type" "fmul,fmadd") 104 (eq_attr "mode" "DF"))) 105 "alu") 106 107 108(define_insn_reservation "r4600_fdiv_single" 32 109 (and (eq_attr "cpu" "r4600,r4650,r4700") 110 (and (eq_attr "type" "fdiv,frdiv") 111 (eq_attr "mode" "SF"))) 112 "alu") 113 114(define_insn_reservation "r4600_fdiv_double" 61 115 (and (eq_attr "cpu" "r4600,r4650,r4700") 116 (and (eq_attr "type" "fdiv,frdiv") 117 (eq_attr "mode" "DF"))) 118 "alu") 119 120(define_insn_reservation "r4600_fsqrt_single" 31 121 (and (eq_attr "cpu" "r4600,r4650,r4700") 122 (and (eq_attr "type" "fsqrt,frsqrt") 123 (eq_attr "mode" "SF"))) 124 "alu") 125 126(define_insn_reservation "r4600_fsqrt_double" 60 127 (and (eq_attr "cpu" "r4600,r4650,r4700") 128 (and (eq_attr "type" "fsqrt,frsqrt") 129 (eq_attr "mode" "DF"))) 130 "alu") 131