1261287Sdes;; Constraint definitions for IA-32 and x86-64. 2261287Sdes;; Copyright (C) 2006-2015 Free Software Foundation, Inc. 3261287Sdes;; 4261287Sdes;; This file is part of GCC. 5261287Sdes;; 6261287Sdes;; GCC is free software; you can redistribute it and/or modify 7261287Sdes;; it under the terms of the GNU General Public License as published by 8261287Sdes;; the Free Software Foundation; either version 3, or (at your option) 9261287Sdes;; any later version. 10261287Sdes;; 11261287Sdes;; GCC is distributed in the hope that it will be useful, 12261287Sdes;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13261287Sdes;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14261287Sdes;; GNU General Public License for more details. 15261287Sdes;; 16261287Sdes;; You should have received a copy of the GNU General Public License 17261287Sdes;; along with GCC; see the file COPYING3. If not see 18261287Sdes;; <http://www.gnu.org/licenses/>. 19261287Sdes 20261287Sdes;;; Unused letters: 21261287Sdes;;; H 22261287Sdes;;; h j z 23261287Sdes 24261287Sdes;; Integer register constraints. 25261287Sdes;; It is not necessary to define 'r' here. 26261287Sdes(define_register_constraint "R" "LEGACY_REGS" 27261287Sdes "Legacy register---the eight integer registers available on all 28261287Sdes i386 processors (@code{a}, @code{b}, @code{c}, @code{d}, 29261287Sdes @code{si}, @code{di}, @code{bp}, @code{sp}).") 30261287Sdes 31261287Sdes(define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS" 32261287Sdes "Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a}, 33261287Sdes @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.") 34261287Sdes 35261287Sdes(define_register_constraint "Q" "Q_REGS" 36261287Sdes "Any register accessible as @code{@var{r}h}: @code{a}, @code{b}, 37261287Sdes @code{c}, and @code{d}.") 38261287Sdes 39261287Sdes(define_register_constraint "l" "INDEX_REGS" 40261287Sdes "@internal Any register that can be used as the index in a base+index 41261287Sdes memory access: that is, any general register except the stack pointer.") 42261287Sdes 43261287Sdes(define_register_constraint "a" "AREG" 44261287Sdes "The @code{a} register.") 45261287Sdes 46261287Sdes(define_register_constraint "b" "BREG" 47261287Sdes "The @code{b} register.") 48261287Sdes 49261287Sdes(define_register_constraint "c" "CREG" 50261287Sdes "The @code{c} register.") 51261287Sdes 52261287Sdes(define_register_constraint "d" "DREG" 53261287Sdes "The @code{d} register.") 54261287Sdes 55261287Sdes(define_register_constraint "S" "SIREG" 56261287Sdes "The @code{si} register.") 57261287Sdes 58261287Sdes(define_register_constraint "D" "DIREG" 59261287Sdes "The @code{di} register.") 60261287Sdes 61261287Sdes(define_register_constraint "A" "AD_REGS" 62261287Sdes "The @code{a} and @code{d} registers, as a pair (for instructions 63261287Sdes that return half the result in one and half in the other).") 64261287Sdes 65261287Sdes(define_register_constraint "U" "CLOBBERED_REGS" 66261287Sdes "The call-clobbered integer registers.") 67261287Sdes 68261287Sdes;; Floating-point register constraints. 69261287Sdes(define_register_constraint "f" 70261287Sdes "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS" 71261287Sdes "Any 80387 floating-point (stack) register.") 72261287Sdes 73261287Sdes(define_register_constraint "t" 74261287Sdes "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS" 75261287Sdes "Top of 80387 floating-point stack (@code{%st(0)}).") 76261287Sdes 77261287Sdes(define_register_constraint "u" 78261287Sdes "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS" 79261287Sdes "Second from top of 80387 floating-point stack (@code{%st(1)}).") 80261287Sdes 81261287Sdes(define_register_constraint "Yk" "TARGET_AVX512F ? MASK_EVEX_REGS : NO_REGS" 82261287Sdes"@internal Any mask register that can be used as predicate, i.e. k1-k7.") 83261287Sdes 84261287Sdes(define_register_constraint "k" "TARGET_AVX512F ? MASK_REGS : NO_REGS" 85261287Sdes"@internal Any mask register.") 86261287Sdes 87261287Sdes;; Vector registers (also used for plain floating point nowadays). 88261287Sdes(define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS" 89261287Sdes "Any MMX register.") 90261287Sdes 91261287Sdes(define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS" 92261287Sdes "Any SSE register.") 93261287Sdes 94261287Sdes(define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS" 95261287Sdes "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).") 96261287Sdes 97261287Sdes(define_register_constraint "w" "TARGET_MPX ? BND_REGS : NO_REGS" 98261287Sdes "@internal Any bound register.") 99261287Sdes 100261287Sdes;; We use the Y prefix to denote any number of conditional register sets: 101261287Sdes;; z First SSE register. 102261287Sdes;; i SSE2 inter-unit moves to SSE register enabled 103261287Sdes;; j SSE2 inter-unit moves from SSE register enabled 104261287Sdes;; m MMX inter-unit moves to MMX register enabled 105261287Sdes;; n MMX inter-unit moves from MMX register enabled 106261287Sdes;; a Integer register when zero extensions with AND are disabled 107261287Sdes;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled 108261287Sdes;; f x87 register when 80387 floating point arithmetic is enabled 109261287Sdes;; r SSE regs not requiring REX prefix when prefixes avoidance is enabled 110261287Sdes;; and all SSE regs otherwise 111261287Sdes 112261287Sdes(define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS" 113261287Sdes "First SSE register (@code{%xmm0}).") 114261287Sdes 115261287Sdes(define_register_constraint "Yi" 116261287Sdes "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS" 117261287Sdes "@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.") 118261287Sdes 119261287Sdes(define_register_constraint "Yj" 120261287Sdes "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC ? ALL_SSE_REGS : NO_REGS" 121261287Sdes "@internal Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.") 122261287Sdes 123261287Sdes(define_register_constraint "Ym" 124261287Sdes "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS" 125261287Sdes "@internal Any MMX register, when inter-unit moves to vector registers are enabled.") 126261287Sdes 127261287Sdes(define_register_constraint "Yn" 128261287Sdes "TARGET_MMX && TARGET_INTER_UNIT_MOVES_FROM_VEC ? MMX_REGS : NO_REGS" 129261287Sdes "@internal Any MMX register, when inter-unit moves from vector registers are enabled.") 130261287Sdes 131261287Sdes(define_register_constraint "Yp" 132261287Sdes "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS" 133261287Sdes "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.") 134261287Sdes 135261287Sdes(define_register_constraint "Ya" 136261287Sdes "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun) 137261287Sdes ? NO_REGS : GENERAL_REGS" 138261287Sdes "@internal Any integer register when zero extensions with AND are disabled.") 139261287Sdes 140261287Sdes(define_register_constraint "Yf" 141261287Sdes "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS" 142261287Sdes "@internal Any x87 register when 80387 FP arithmetic is enabled.") 143261287Sdes 144261287Sdes;; Yr constraint is meant to be used in noavx contexts only, for VEX and EVEX 145261287Sdes;; the lower register numbers need the same instruction sizes as any other. 146261287Sdes;; In case Yr constraint is misused, try to limit the damage, by treating 147261287Sdes;; it as x constraint in avx mode, not v constraint. 148261287Sdes(define_register_constraint "Yr" 149261287Sdes "TARGET_SSE ? ((TARGET_AVOID_4BYTE_PREFIXES && !TARGET_AVX) ? NO_REX_SSE_REGS : SSE_REGS) : NO_REGS" 150261287Sdes "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.") 151261287Sdes 152261287Sdes;; We use the B prefix to denote any number of internal operands: 153261287Sdes;; s Sibcall memory operand, not valid for TARGET_X32 154261287Sdes;; w Call memory operand, not valid for TARGET_X32 155261287Sdes;; z Constant call address operand. 156261287Sdes;; C SSE constant operand. 157261287Sdes 158261287Sdes(define_constraint "Bs" 159261287Sdes "@internal Sibcall memory operand." 160261287Sdes (and (not (match_test "TARGET_X32")) 161261287Sdes (match_operand 0 "sibcall_memory_operand"))) 162261287Sdes 163261287Sdes(define_constraint "Bw" 164261287Sdes "@internal Call memory operand." 165261287Sdes (and (not (match_test "TARGET_X32")) 166261287Sdes (match_operand 0 "memory_operand"))) 167261287Sdes 168261287Sdes(define_constraint "Bz" 169261287Sdes "@internal Constant call address operand." 170261287Sdes (match_operand 0 "constant_call_address_operand")) 171261287Sdes 172261287Sdes(define_constraint "BC" 173261287Sdes "@internal SSE constant operand." 174261287Sdes (match_test "standard_sse_constant_p (op)")) 175261287Sdes 176261287Sdes;; Integer constant constraints. 177261287Sdes(define_constraint "I" 178261287Sdes "Integer constant in the range 0 @dots{} 31, for 32-bit shifts." 179261287Sdes (and (match_code "const_int") 180261287Sdes (match_test "IN_RANGE (ival, 0, 31)"))) 181261287Sdes 182261287Sdes(define_constraint "J" 183261287Sdes "Integer constant in the range 0 @dots{} 63, for 64-bit shifts." 184261287Sdes (and (match_code "const_int") 185261287Sdes (match_test "IN_RANGE (ival, 0, 63)"))) 186261287Sdes 187261287Sdes(define_constraint "K" 188261287Sdes "Signed 8-bit integer constant." 189261287Sdes (and (match_code "const_int") 190261287Sdes (match_test "IN_RANGE (ival, -128, 127)"))) 191261287Sdes 192261287Sdes(define_constraint "L" 193261287Sdes "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF} 194261287Sdes for AND as a zero-extending move." 195261287Sdes (and (match_code "const_int") 196261287Sdes (match_test "ival == 0xff || ival == 0xffff 197261287Sdes || ival == (HOST_WIDE_INT) 0xffffffff"))) 198261287Sdes 199261287Sdes(define_constraint "M" 200261287Sdes "0, 1, 2, or 3 (shifts for the @code{lea} instruction)." 201261287Sdes (and (match_code "const_int") 202261287Sdes (match_test "IN_RANGE (ival, 0, 3)"))) 203261287Sdes 204261287Sdes(define_constraint "N" 205261287Sdes "Unsigned 8-bit integer constant (for @code{in} and @code{out} 206261287Sdes instructions)." 207261287Sdes (and (match_code "const_int") 208261287Sdes (match_test "IN_RANGE (ival, 0, 255)"))) 209261287Sdes 210261287Sdes(define_constraint "O" 211261287Sdes "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts." 212261287Sdes (and (match_code "const_int") 213261287Sdes (match_test "IN_RANGE (ival, 0, 127)"))) 214261287Sdes 215261287Sdes;; Floating-point constant constraints. 216261287Sdes;; We allow constants even if TARGET_80387 isn't set, because the 217261287Sdes;; stack register converter may need to load 0.0 into the function 218261287Sdes;; value register (top of stack). 219261287Sdes(define_constraint "G" 220261287Sdes "Standard 80387 floating point constant." 221261287Sdes (and (match_code "const_double") 222261287Sdes (match_test "standard_80387_constant_p (op) > 0"))) 223261287Sdes 224261287Sdes;; This can theoretically be any mode's CONST0_RTX. 225261287Sdes(define_constraint "C" 226261287Sdes "SSE constant zero operand." 227261287Sdes (match_test "standard_sse_constant_p (op) == 1")) 228261287Sdes 229261287Sdes;; Constant-or-symbol-reference constraints. 230261287Sdes 231261287Sdes(define_constraint "e" 232261287Sdes "32-bit signed integer constant, or a symbolic reference known 233261287Sdes to fit that range (for immediate operands in sign-extending x86-64 234261287Sdes instructions)." 235261287Sdes (match_operand 0 "x86_64_immediate_operand")) 236261287Sdes 237261287Sdes;; We use W prefix to denote any number of 238261287Sdes;; constant-or-symbol-reference constraints 239261287Sdes 240261287Sdes(define_constraint "We" 241261287Sdes "32-bit signed integer constant, or a symbolic reference known 242261287Sdes to fit that range (for sign-extending conversion operations that 243261287Sdes require non-VOIDmode immediate operands)." 244261287Sdes (and (match_operand 0 "x86_64_immediate_operand") 245261287Sdes (match_test "GET_MODE (op) != VOIDmode"))) 246261287Sdes 247261287Sdes(define_constraint "Wz" 248261287Sdes "32-bit unsigned integer constant, or a symbolic reference known 249261287Sdes to fit that range (for zero-extending conversion operations that 250261287Sdes require non-VOIDmode immediate operands)." 251261287Sdes (and (match_operand 0 "x86_64_zext_immediate_operand") 252261287Sdes (match_test "GET_MODE (op) != VOIDmode"))) 253261287Sdes 254261287Sdes(define_constraint "Z" 255261287Sdes "32-bit unsigned integer constant, or a symbolic reference known 256261287Sdes to fit that range (for immediate operands in zero-extending x86-64 257261287Sdes instructions)." 258261287Sdes (match_operand 0 "x86_64_zext_immediate_operand")) 259261287Sdes 260261287Sdes;; T prefix is used for different address constraints 261261287Sdes;; v - VSIB address 262261287Sdes;; s - address with no segment register 263261287Sdes;; i - address with no index and no rip 264261287Sdes;; b - address with no base and no rip 265261287Sdes 266261287Sdes(define_address_constraint "Tv" 267261287Sdes "VSIB address operand" 268261287Sdes (match_operand 0 "vsib_address_operand")) 269261287Sdes 270261287Sdes(define_address_constraint "Ts" 271261287Sdes "Address operand without segment register" 272261287Sdes (match_operand 0 "address_no_seg_operand")) 273261287Sdes 274261287Sdes(define_address_constraint "Ti" 275261287Sdes "MPX address operand without index" 276261287Sdes (match_operand 0 "address_mpx_no_index_operand")) 277261287Sdes 278261287Sdes(define_address_constraint "Tb" 279261287Sdes "MPX address operand without base" 280261287Sdes (match_operand 0 "address_mpx_no_base_operand")) 281261287Sdes