1/* Definitions for GCC. Part of the machine description for CRIS. 2 Copyright (C) 1998-2015 Free Software Foundation, Inc. 3 Contributed by Axis Communications. Written by Hans-Peter Nilsson. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 3, or (at your option) 10any later version. 11 12GCC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING3. If not see 19<http://www.gnu.org/licenses/>. */ 20 21#include "config.h" 22#include "system.h" 23#include "coretypes.h" 24#include "tm.h" 25#include "rtl.h" 26#include "regs.h" 27#include "hard-reg-set.h" 28#include "insn-config.h" 29#include "conditions.h" 30#include "insn-attr.h" 31#include "flags.h" 32#include "hash-set.h" 33#include "machmode.h" 34#include "vec.h" 35#include "double-int.h" 36#include "input.h" 37#include "alias.h" 38#include "symtab.h" 39#include "wide-int.h" 40#include "inchash.h" 41#include "tree.h" 42#include "fold-const.h" 43#include "varasm.h" 44#include "stor-layout.h" 45#include "calls.h" 46#include "stmt.h" 47#include "hashtab.h" 48#include "function.h" 49#include "statistics.h" 50#include "real.h" 51#include "fixed-value.h" 52#include "expmed.h" 53#include "dojump.h" 54#include "explow.h" 55#include "emit-rtl.h" 56#include "expr.h" 57#include "except.h" 58#include "diagnostic-core.h" 59#include "recog.h" 60#include "reload.h" 61#include "tm_p.h" 62#include "debug.h" 63#include "output.h" 64#include "tm-constrs.h" 65#include "target.h" 66#include "target-def.h" 67#include "ggc.h" 68#include "insn-codes.h" 69#include "optabs.h" 70#include "dominance.h" 71#include "cfg.h" 72#include "cfgrtl.h" 73#include "cfganal.h" 74#include "lcm.h" 75#include "cfgbuild.h" 76#include "cfgcleanup.h" 77#include "predict.h" 78#include "basic-block.h" 79#include "df.h" 80#include "opts.h" 81#include "hash-map.h" 82#include "is-a.h" 83#include "plugin-api.h" 84#include "ipa-ref.h" 85#include "cgraph.h" 86#include "builtins.h" 87 88/* Usable when we have an amount to add or subtract, and want the 89 optimal size of the insn. */ 90#define ADDITIVE_SIZE_MODIFIER(size) \ 91 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d") 92 93#define LOSE_AND_RETURN(msgid, x) \ 94 do \ 95 { \ 96 cris_operand_lossage (msgid, x); \ 97 return; \ 98 } while (0) 99 100enum cris_retinsn_type 101 { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP }; 102 103/* Per-function machine data. */ 104struct GTY(()) machine_function 105 { 106 int needs_return_address_on_stack; 107 108 /* This is the number of registers we save in the prologue due to 109 stdarg. */ 110 int stdarg_regs; 111 112 enum cris_retinsn_type return_type; 113 }; 114 115/* This little fix suppresses the 'u' or 's' when '%e' in assembly 116 pattern. */ 117static char cris_output_insn_is_bound = 0; 118 119/* In code for output macros, this is how we know whether e.g. constant 120 goes in code or in a static initializer. */ 121static int in_code = 0; 122 123/* Fix for reg_overlap_mentioned_p. */ 124static int cris_reg_overlap_mentioned_p (rtx, rtx); 125 126static machine_mode cris_promote_function_mode (const_tree, machine_mode, 127 int *, const_tree, int); 128 129static unsigned int cris_atomic_align_for_mode (machine_mode); 130 131static void cris_print_base (rtx, FILE *); 132 133static void cris_print_index (rtx, FILE *); 134 135static void cris_output_addr_const (FILE *, rtx); 136 137static struct machine_function * cris_init_machine_status (void); 138 139static rtx cris_struct_value_rtx (tree, int); 140 141static void cris_setup_incoming_varargs (cumulative_args_t, machine_mode, 142 tree type, int *, int); 143 144static int cris_initial_frame_pointer_offset (void); 145 146static void cris_operand_lossage (const char *, rtx); 147 148static int cris_reg_saved_in_regsave_area (unsigned int, bool); 149 150static void cris_print_operand (FILE *, rtx, int); 151 152static void cris_print_operand_address (FILE *, rtx); 153 154static bool cris_print_operand_punct_valid_p (unsigned char code); 155 156static bool cris_output_addr_const_extra (FILE *, rtx); 157 158static void cris_conditional_register_usage (void); 159 160static void cris_asm_output_mi_thunk 161 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); 162 163static void cris_file_start (void); 164static void cris_init_libfuncs (void); 165 166static reg_class_t cris_preferred_reload_class (rtx, reg_class_t); 167 168static int cris_register_move_cost (machine_mode, reg_class_t, reg_class_t); 169static int cris_memory_move_cost (machine_mode, reg_class_t, bool); 170static bool cris_rtx_costs (rtx, int, int, int, int *, bool); 171static int cris_address_cost (rtx, machine_mode, addr_space_t, bool); 172static bool cris_pass_by_reference (cumulative_args_t, machine_mode, 173 const_tree, bool); 174static int cris_arg_partial_bytes (cumulative_args_t, machine_mode, 175 tree, bool); 176static rtx cris_function_arg (cumulative_args_t, machine_mode, 177 const_tree, bool); 178static rtx cris_function_incoming_arg (cumulative_args_t, 179 machine_mode, const_tree, bool); 180static void cris_function_arg_advance (cumulative_args_t, machine_mode, 181 const_tree, bool); 182static tree cris_md_asm_clobbers (tree, tree, tree); 183static bool cris_cannot_force_const_mem (machine_mode, rtx); 184 185static void cris_option_override (void); 186 187static bool cris_frame_pointer_required (void); 188 189static void cris_asm_trampoline_template (FILE *); 190static void cris_trampoline_init (rtx, tree, rtx); 191 192static rtx cris_function_value(const_tree, const_tree, bool); 193static rtx cris_libcall_value (machine_mode, const_rtx); 194static bool cris_function_value_regno_p (const unsigned int); 195static void cris_file_end (void); 196 197/* This is the parsed result of the "-max-stack-stackframe=" option. If 198 it (still) is zero, then there was no such option given. */ 199int cris_max_stackframe = 0; 200 201/* This is the parsed result of the "-march=" option, if given. */ 202int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION; 203 204#undef TARGET_ASM_ALIGNED_HI_OP 205#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" 206#undef TARGET_ASM_ALIGNED_SI_OP 207#define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t" 208#undef TARGET_ASM_ALIGNED_DI_OP 209#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" 210 211/* We need to define these, since the 2byte, 4byte, 8byte op:s are only 212 available in ELF. These "normal" pseudos do not have any alignment 213 constraints or side-effects. */ 214#undef TARGET_ASM_UNALIGNED_HI_OP 215#define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP 216 217#undef TARGET_ASM_UNALIGNED_SI_OP 218#define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP 219 220#undef TARGET_ASM_UNALIGNED_DI_OP 221#define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP 222 223#undef TARGET_PRINT_OPERAND 224#define TARGET_PRINT_OPERAND cris_print_operand 225#undef TARGET_PRINT_OPERAND_ADDRESS 226#define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address 227#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P 228#define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p 229#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA 230#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra 231 232#undef TARGET_CONDITIONAL_REGISTER_USAGE 233#define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage 234 235#undef TARGET_ASM_OUTPUT_MI_THUNK 236#define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk 237#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 238#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall 239 240#undef TARGET_ASM_FILE_START 241#define TARGET_ASM_FILE_START cris_file_start 242#undef TARGET_ASM_FILE_END 243#define TARGET_ASM_FILE_END cris_file_end 244 245#undef TARGET_INIT_LIBFUNCS 246#define TARGET_INIT_LIBFUNCS cris_init_libfuncs 247 248#undef TARGET_LEGITIMATE_ADDRESS_P 249#define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p 250 251#undef TARGET_LEGITIMATE_CONSTANT_P 252#define TARGET_LEGITIMATE_CONSTANT_P cris_legitimate_constant_p 253 254#undef TARGET_PREFERRED_RELOAD_CLASS 255#define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class 256 257#undef TARGET_REGISTER_MOVE_COST 258#define TARGET_REGISTER_MOVE_COST cris_register_move_cost 259#undef TARGET_MEMORY_MOVE_COST 260#define TARGET_MEMORY_MOVE_COST cris_memory_move_cost 261#undef TARGET_RTX_COSTS 262#define TARGET_RTX_COSTS cris_rtx_costs 263#undef TARGET_ADDRESS_COST 264#define TARGET_ADDRESS_COST cris_address_cost 265 266#undef TARGET_PROMOTE_FUNCTION_MODE 267#define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode 268 269#undef TARGET_ATOMIC_ALIGN_FOR_MODE 270#define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode 271 272#undef TARGET_STRUCT_VALUE_RTX 273#define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx 274#undef TARGET_SETUP_INCOMING_VARARGS 275#define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs 276#undef TARGET_PASS_BY_REFERENCE 277#define TARGET_PASS_BY_REFERENCE cris_pass_by_reference 278#undef TARGET_ARG_PARTIAL_BYTES 279#define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes 280#undef TARGET_FUNCTION_ARG 281#define TARGET_FUNCTION_ARG cris_function_arg 282#undef TARGET_FUNCTION_INCOMING_ARG 283#define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg 284#undef TARGET_FUNCTION_ARG_ADVANCE 285#define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance 286#undef TARGET_MD_ASM_CLOBBERS 287#define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers 288 289#undef TARGET_CANNOT_FORCE_CONST_MEM 290#define TARGET_CANNOT_FORCE_CONST_MEM cris_cannot_force_const_mem 291 292#undef TARGET_FRAME_POINTER_REQUIRED 293#define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required 294 295#undef TARGET_OPTION_OVERRIDE 296#define TARGET_OPTION_OVERRIDE cris_option_override 297 298#undef TARGET_ASM_TRAMPOLINE_TEMPLATE 299#define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template 300#undef TARGET_TRAMPOLINE_INIT 301#define TARGET_TRAMPOLINE_INIT cris_trampoline_init 302 303#undef TARGET_FUNCTION_VALUE 304#define TARGET_FUNCTION_VALUE cris_function_value 305#undef TARGET_LIBCALL_VALUE 306#define TARGET_LIBCALL_VALUE cris_libcall_value 307#undef TARGET_FUNCTION_VALUE_REGNO_P 308#define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p 309 310struct gcc_target targetm = TARGET_INITIALIZER; 311 312/* Helper for cris_load_multiple_op and cris_ret_movem_op. */ 313 314bool 315cris_movem_load_rest_p (rtx op, int offs) 316{ 317 unsigned int reg_count = XVECLEN (op, 0) - offs; 318 rtx src_addr; 319 int i; 320 rtx elt; 321 int setno; 322 int regno_dir = 1; 323 unsigned int regno = 0; 324 325 /* Perform a quick check so we don't blow up below. FIXME: Adjust for 326 other than (MEM reg). */ 327 if (reg_count <= 1 328 || GET_CODE (XVECEXP (op, 0, offs)) != SET 329 || !REG_P (SET_DEST (XVECEXP (op, 0, offs))) 330 || !MEM_P (SET_SRC (XVECEXP (op, 0, offs)))) 331 return false; 332 333 /* Check a possible post-inc indicator. */ 334 if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS) 335 { 336 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0); 337 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1); 338 339 reg_count--; 340 341 if (reg_count == 1 342 || !REG_P (reg) 343 || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1))) 344 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1))) 345 || !CONST_INT_P (inc) 346 || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4) 347 return false; 348 i = offs + 2; 349 } 350 else 351 i = offs + 1; 352 353 if (!TARGET_V32) 354 { 355 regno_dir = -1; 356 regno = reg_count - 1; 357 } 358 359 elt = XVECEXP (op, 0, offs); 360 src_addr = XEXP (SET_SRC (elt), 0); 361 362 if (GET_CODE (elt) != SET 363 || !REG_P (SET_DEST (elt)) 364 || GET_MODE (SET_DEST (elt)) != SImode 365 || REGNO (SET_DEST (elt)) != regno 366 || !MEM_P (SET_SRC (elt)) 367 || GET_MODE (SET_SRC (elt)) != SImode 368 || !memory_address_p (SImode, src_addr)) 369 return false; 370 371 for (setno = 1; i < XVECLEN (op, 0); setno++, i++) 372 { 373 rtx elt = XVECEXP (op, 0, i); 374 regno += regno_dir; 375 376 if (GET_CODE (elt) != SET 377 || !REG_P (SET_DEST (elt)) 378 || GET_MODE (SET_DEST (elt)) != SImode 379 || REGNO (SET_DEST (elt)) != regno 380 || !MEM_P (SET_SRC (elt)) 381 || GET_MODE (SET_SRC (elt)) != SImode 382 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS 383 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) 384 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1)) 385 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4) 386 return false; 387 } 388 389 return true; 390} 391 392/* Worker function for predicate for the parallel contents in a movem 393 to-memory. */ 394 395bool 396cris_store_multiple_op_p (rtx op) 397{ 398 int reg_count = XVECLEN (op, 0); 399 rtx dest; 400 rtx dest_addr; 401 rtx dest_base; 402 int i; 403 rtx elt; 404 int setno; 405 int regno_dir = 1; 406 int regno = 0; 407 int offset = 0; 408 409 /* Perform a quick check so we don't blow up below. FIXME: Adjust for 410 other than (MEM reg) and (MEM (PLUS reg const)). */ 411 if (reg_count <= 1) 412 return false; 413 414 elt = XVECEXP (op, 0, 0); 415 416 if (GET_CODE (elt) != SET) 417 return false; 418 419 dest = SET_DEST (elt); 420 421 if (!REG_P (SET_SRC (elt)) || !MEM_P (dest)) 422 return false; 423 424 dest_addr = XEXP (dest, 0); 425 426 /* Check a possible post-inc indicator. */ 427 if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS) 428 { 429 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0); 430 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1); 431 432 reg_count--; 433 434 if (reg_count == 1 435 || !REG_P (reg) 436 || !REG_P (SET_DEST (XVECEXP (op, 0, 1))) 437 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1))) 438 || !CONST_INT_P (inc) 439 /* Support increment by number of registers, and by the offset 440 of the destination, if it has the form (MEM (PLUS reg 441 offset)). */ 442 || !((REG_P (dest_addr) 443 && REGNO (dest_addr) == REGNO (reg) 444 && INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4) 445 || (GET_CODE (dest_addr) == PLUS 446 && REG_P (XEXP (dest_addr, 0)) 447 && REGNO (XEXP (dest_addr, 0)) == REGNO (reg) 448 && CONST_INT_P (XEXP (dest_addr, 1)) 449 && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc)))) 450 return false; 451 452 i = 2; 453 } 454 else 455 i = 1; 456 457 if (!TARGET_V32) 458 { 459 regno_dir = -1; 460 regno = reg_count - 1; 461 } 462 463 if (GET_CODE (elt) != SET 464 || !REG_P (SET_SRC (elt)) 465 || GET_MODE (SET_SRC (elt)) != SImode 466 || REGNO (SET_SRC (elt)) != (unsigned int) regno 467 || !MEM_P (SET_DEST (elt)) 468 || GET_MODE (SET_DEST (elt)) != SImode) 469 return false; 470 471 if (REG_P (dest_addr)) 472 { 473 dest_base = dest_addr; 474 offset = 0; 475 } 476 else if (GET_CODE (dest_addr) == PLUS 477 && REG_P (XEXP (dest_addr, 0)) 478 && CONST_INT_P (XEXP (dest_addr, 1))) 479 { 480 dest_base = XEXP (dest_addr, 0); 481 offset = INTVAL (XEXP (dest_addr, 1)); 482 } 483 else 484 return false; 485 486 for (setno = 1; i < XVECLEN (op, 0); setno++, i++) 487 { 488 rtx elt = XVECEXP (op, 0, i); 489 regno += regno_dir; 490 491 if (GET_CODE (elt) != SET 492 || !REG_P (SET_SRC (elt)) 493 || GET_MODE (SET_SRC (elt)) != SImode 494 || REGNO (SET_SRC (elt)) != (unsigned int) regno 495 || !MEM_P (SET_DEST (elt)) 496 || GET_MODE (SET_DEST (elt)) != SImode 497 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS 498 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base) 499 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1)) 500 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset) 501 return false; 502 } 503 504 return true; 505} 506 507/* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */ 508 509static void 510cris_conditional_register_usage (void) 511{ 512 /* FIXME: This isn't nice. We should be able to use that register for 513 something else if the PIC table isn't needed. */ 514 if (flag_pic) 515 fixed_regs[PIC_OFFSET_TABLE_REGNUM] 516 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; 517 518 /* Allow use of ACR (PC in pre-V32) and tweak order. */ 519 if (TARGET_V32) 520 { 521 static const int reg_alloc_order_v32[] = REG_ALLOC_ORDER_V32; 522 unsigned int i; 523 524 fixed_regs[CRIS_ACR_REGNUM] = 0; 525 526 for (i = 0; 527 i < sizeof (reg_alloc_order_v32)/sizeof (reg_alloc_order_v32[0]); 528 i++) 529 reg_alloc_order[i] = reg_alloc_order_v32[i]; 530 } 531 532 if (TARGET_HAS_MUL_INSNS) 533 fixed_regs[CRIS_MOF_REGNUM] = 0; 534 535 /* On early versions, we must use the 16-bit condition-code register, 536 which has another name. */ 537 if (cris_cpu_version < 8) 538 reg_names[CRIS_CC0_REGNUM] = "ccr"; 539} 540 541/* Return crtl->uses_pic_offset_table. For use in cris.md, 542 since some generated files do not include function.h. */ 543 544int 545cris_cfun_uses_pic_table (void) 546{ 547 return crtl->uses_pic_offset_table; 548} 549 550/* Worker function for TARGET_CANNOT_FORCE_CONST_MEM. 551 We can't put PIC addresses in the constant pool, not even the ones that 552 can be reached as pc-relative as we can't tell when or how to do that. */ 553 554static bool 555cris_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 556{ 557 enum cris_symbol_type t = cris_symbol_type_of (x); 558 559 return 560 t == cris_unspec 561 || t == cris_got_symbol 562 || t == cris_rel_symbol; 563} 564 565/* Given an rtx, return the text string corresponding to the CODE of X. 566 Intended for use in the assembly language output section of a 567 define_insn. */ 568 569const char * 570cris_op_str (rtx x) 571{ 572 cris_output_insn_is_bound = 0; 573 switch (GET_CODE (x)) 574 { 575 case PLUS: 576 return "add"; 577 break; 578 579 case MINUS: 580 return "sub"; 581 break; 582 583 case MULT: 584 /* This function is for retrieving a part of an instruction name for 585 an operator, for immediate output. If that ever happens for 586 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure 587 we notice. */ 588 internal_error ("MULT case in cris_op_str"); 589 break; 590 591 case DIV: 592 return "div"; 593 break; 594 595 case AND: 596 return "and"; 597 break; 598 599 case IOR: 600 return "or"; 601 break; 602 603 case XOR: 604 return "xor"; 605 break; 606 607 case NOT: 608 return "not"; 609 break; 610 611 case ASHIFT: 612 return "lsl"; 613 break; 614 615 case LSHIFTRT: 616 return "lsr"; 617 break; 618 619 case ASHIFTRT: 620 return "asr"; 621 break; 622 623 case UMIN: 624 /* Used to control the sign/zero-extend character for the 'E' modifier. 625 BOUND has none. */ 626 cris_output_insn_is_bound = 1; 627 return "bound"; 628 break; 629 630 default: 631 return "Unknown operator"; 632 break; 633 } 634} 635 636/* Emit an error message when we're in an asm, and a fatal error for 637 "normal" insns. Formatted output isn't easily implemented, since we 638 use output_operand_lossage to output the actual message and handle the 639 categorization of the error. */ 640 641static void 642cris_operand_lossage (const char *msgid, rtx op) 643{ 644 debug_rtx (op); 645 output_operand_lossage ("%s", msgid); 646} 647 648/* Print an index part of an address to file. */ 649 650static void 651cris_print_index (rtx index, FILE *file) 652{ 653 /* Make the index "additive" unless we'll output a negative number, in 654 which case the sign character is free (as in free beer). */ 655 if (!CONST_INT_P (index) || INTVAL (index) >= 0) 656 putc ('+', file); 657 658 if (REG_P (index)) 659 fprintf (file, "$%s.b", reg_names[REGNO (index)]); 660 else if (CRIS_CONSTANT_P (index)) 661 cris_output_addr_const (file, index); 662 else if (GET_CODE (index) == MULT) 663 { 664 fprintf (file, "$%s.", 665 reg_names[REGNO (XEXP (index, 0))]); 666 667 putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file); 668 } 669 else if (GET_CODE (index) == SIGN_EXTEND && MEM_P (XEXP (index, 0))) 670 { 671 rtx inner = XEXP (index, 0); 672 rtx inner_inner = XEXP (inner, 0); 673 674 if (GET_CODE (inner_inner) == POST_INC) 675 { 676 fprintf (file, "[$%s+].", 677 reg_names[REGNO (XEXP (inner_inner, 0))]); 678 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file); 679 } 680 else 681 { 682 fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]); 683 684 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file); 685 } 686 } 687 else if (MEM_P (index)) 688 { 689 rtx inner = XEXP (index, 0); 690 if (GET_CODE (inner) == POST_INC) 691 fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]); 692 else 693 fprintf (file, "[$%s].d", reg_names[REGNO (inner)]); 694 } 695 else 696 cris_operand_lossage ("unexpected index-type in cris_print_index", 697 index); 698} 699 700/* Print a base rtx of an address to file. */ 701 702static void 703cris_print_base (rtx base, FILE *file) 704{ 705 if (REG_P (base)) 706 fprintf (file, "$%s", reg_names[REGNO (base)]); 707 else if (GET_CODE (base) == POST_INC) 708 { 709 gcc_assert (REGNO (XEXP (base, 0)) != CRIS_ACR_REGNUM); 710 fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]); 711 } 712 else 713 cris_operand_lossage ("unexpected base-type in cris_print_base", 714 base); 715} 716 717/* Usable as a guard in expressions. */ 718 719int 720cris_fatal (char *arg) 721{ 722 internal_error (arg); 723 724 /* We'll never get here; this is just to appease compilers. */ 725 return 0; 726} 727 728/* Return nonzero if REGNO is an ordinary register that *needs* to be 729 saved together with other registers, possibly by a MOVEM instruction, 730 or is saved for target-independent reasons. There may be 731 target-dependent reasons to save the register anyway; this is just a 732 wrapper for a complicated conditional. */ 733 734static int 735cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used) 736{ 737 return 738 (((df_regs_ever_live_p (regno) 739 && !call_used_regs[regno]) 740 || (regno == PIC_OFFSET_TABLE_REGNUM 741 && (got_really_used 742 /* It is saved anyway, if there would be a gap. */ 743 || (flag_pic 744 && df_regs_ever_live_p (regno + 1) 745 && !call_used_regs[regno + 1])))) 746 && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed) 747 && regno != CRIS_SRP_REGNUM) 748 || (crtl->calls_eh_return 749 && (regno == EH_RETURN_DATA_REGNO (0) 750 || regno == EH_RETURN_DATA_REGNO (1) 751 || regno == EH_RETURN_DATA_REGNO (2) 752 || regno == EH_RETURN_DATA_REGNO (3))); 753} 754 755/* The PRINT_OPERAND worker. */ 756 757static void 758cris_print_operand (FILE *file, rtx x, int code) 759{ 760 rtx operand = x; 761 762 /* Size-strings corresponding to MULT expressions. */ 763 static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" }; 764 765 /* New code entries should just be added to the switch below. If 766 handling is finished, just return. If handling was just a 767 modification of the operand, the modified operand should be put in 768 "operand", and then do a break to let default handling 769 (zero-modifier) output the operand. */ 770 771 switch (code) 772 { 773 case 'b': 774 /* Print the unsigned supplied integer as if it were signed 775 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */ 776 if (!satisfies_constraint_O (x)) 777 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x); 778 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 779 INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535)); 780 return; 781 782 case 'x': 783 /* Print assembler code for operator. */ 784 fprintf (file, "%s", cris_op_str (operand)); 785 return; 786 787 case 'o': 788 { 789 /* A movem modifier working on a parallel; output the register 790 name. */ 791 int regno; 792 793 if (GET_CODE (x) != PARALLEL) 794 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x); 795 796 /* The second item can be (set reg (plus reg const)) to denote a 797 postincrement. */ 798 regno 799 = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS 800 ? XVECLEN (x, 0) - 2 801 : XVECLEN (x, 0) - 1); 802 803 fprintf (file, "$%s", reg_names [regno]); 804 } 805 return; 806 807 case 'O': 808 { 809 /* A similar movem modifier; output the memory operand. */ 810 rtx addr; 811 812 if (GET_CODE (x) != PARALLEL) 813 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x); 814 815 /* The lowest mem operand is in the first item, but perhaps it 816 needs to be output as postincremented. */ 817 addr = MEM_P (SET_SRC (XVECEXP (x, 0, 0))) 818 ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0) 819 : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0); 820 821 /* The second item can be a (set reg (plus reg const)) to denote 822 a modification. */ 823 if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS) 824 { 825 /* It's a post-increment, if the address is a naked (reg). */ 826 if (REG_P (addr)) 827 addr = gen_rtx_POST_INC (SImode, addr); 828 else 829 { 830 /* Otherwise, it's a side-effect; RN=RN+M. */ 831 fprintf (file, "[$%s=$%s%s%d]", 832 reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))], 833 reg_names [REGNO (XEXP (addr, 0))], 834 INTVAL (XEXP (addr, 1)) < 0 ? "" : "+", 835 (int) INTVAL (XEXP (addr, 1))); 836 return; 837 } 838 } 839 output_address (addr); 840 } 841 return; 842 843 case 'p': 844 /* Adjust a power of two to its log2. */ 845 if (!CONST_INT_P (x) || exact_log2 (INTVAL (x)) < 0 ) 846 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x); 847 fprintf (file, "%d", exact_log2 (INTVAL (x))); 848 return; 849 850 case 's': 851 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535 852 respectively. This modifier also terminates the inhibiting 853 effects of the 'x' modifier. */ 854 cris_output_insn_is_bound = 0; 855 if (GET_MODE (x) == VOIDmode && CONST_INT_P (x)) 856 { 857 if (INTVAL (x) >= 0) 858 { 859 if (INTVAL (x) <= 255) 860 putc ('b', file); 861 else if (INTVAL (x) <= 65535) 862 putc ('w', file); 863 else 864 putc ('d', file); 865 } 866 else 867 putc ('d', file); 868 return; 869 } 870 871 /* For a non-integer, print the size of the operand. */ 872 putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode) 873 ? 'd' : GET_MODE (x) == HImode ? 'w' 874 : GET_MODE (x) == QImode ? 'b' 875 /* If none of the above, emit an erroneous size letter. */ 876 : 'X', 877 file); 878 return; 879 880 case 'z': 881 /* Const_int: print b for -127 <= x <= 255, 882 w for -32768 <= x <= 65535, else die. */ 883 if (!CONST_INT_P (x) 884 || INTVAL (x) < -32768 || INTVAL (x) > 65535) 885 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x); 886 putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file); 887 return; 888 889 case 'Z': 890 /* If this is a GOT-symbol, print the size-letter corresponding to 891 -fpic/-fPIC. For everything else, print "d". */ 892 putc ((flag_pic == 1 893 && GET_CODE (x) == CONST 894 && GET_CODE (XEXP (x, 0)) == UNSPEC 895 && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREAD) 896 ? 'w' : 'd', file); 897 return; 898 899 case '#': 900 /* Output a 'nop' if there's nothing for the delay slot. 901 This method stolen from the sparc files. */ 902 if (dbr_sequence_length () == 0) 903 fputs ("\n\tnop", file); 904 return; 905 906 case '!': 907 /* Output directive for alignment padded with "nop" insns. 908 Optimizing for size, it's plain 4-byte alignment, otherwise we 909 align the section to a cache-line (32 bytes) and skip at max 2 910 bytes, i.e. we skip if it's the last insn on a cache-line. The 911 latter is faster by a small amount (for two test-programs 99.6% 912 and 99.9%) and larger by a small amount (ditto 100.1% and 913 100.2%). This is supposed to be the simplest yet performance- 914 wise least intrusive way to make sure the immediately following 915 (supposed) muls/mulu insn isn't located at the end of a 916 cache-line. */ 917 if (TARGET_MUL_BUG) 918 fputs (optimize_size 919 ? ".p2alignw 2,0x050f\n\t" 920 : ".p2alignw 5,0x050f,2\n\t", file); 921 return; 922 923 case ':': 924 /* The PIC register. */ 925 if (! flag_pic) 926 internal_error ("invalid use of ':' modifier"); 927 fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]); 928 return; 929 930 case 'H': 931 /* Print high (most significant) part of something. */ 932 switch (GET_CODE (operand)) 933 { 934 case CONST_INT: 935 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode) 936 value is kept here, and so may be other than 0 or -1. */ 937 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 938 INTVAL (operand_subword (operand, 1, 0, DImode))); 939 return; 940 941 case CONST_DOUBLE: 942 /* High part of a long long constant. */ 943 if (GET_MODE (operand) == VOIDmode) 944 { 945 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x)); 946 return; 947 } 948 else 949 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x); 950 951 case REG: 952 /* Print reg + 1. Check that there's not an attempt to print 953 high-parts of registers like stack-pointer or higher, except 954 for SRP (where the "high part" is MOF). */ 955 if (REGNO (operand) > STACK_POINTER_REGNUM - 2 956 && (REGNO (operand) != CRIS_SRP_REGNUM 957 || CRIS_SRP_REGNUM + 1 != CRIS_MOF_REGNUM 958 || fixed_regs[CRIS_MOF_REGNUM] != 0)) 959 LOSE_AND_RETURN ("bad register", operand); 960 fprintf (file, "$%s", reg_names[REGNO (operand) + 1]); 961 return; 962 963 case MEM: 964 /* Adjust memory address to high part. */ 965 { 966 rtx adj_mem = operand; 967 int size 968 = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT; 969 970 /* Adjust so we can use two SImode in DImode. 971 Calling adj_offsettable_operand will make sure it is an 972 offsettable address. Don't do this for a postincrement 973 though; it should remain as it was. */ 974 if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC) 975 adj_mem 976 = adjust_address (adj_mem, GET_MODE (adj_mem), size / 2); 977 978 output_address (XEXP (adj_mem, 0)); 979 return; 980 } 981 982 default: 983 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x); 984 } 985 986 case 'L': 987 /* Strip the MEM expression. */ 988 operand = XEXP (operand, 0); 989 break; 990 991 case 'e': 992 /* Like 'E', but ignore state set by 'x'. FIXME: Use code 993 iterators and attributes in cris.md to avoid the need for %x 994 and %E (and %e) and state passed between those modifiers. */ 995 cris_output_insn_is_bound = 0; 996 /* FALL THROUGH. */ 997 case 'E': 998 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless 999 cris_output_insn_is_bound is nonzero. */ 1000 if (GET_CODE (operand) != SIGN_EXTEND 1001 && GET_CODE (operand) != ZERO_EXTEND 1002 && !CONST_INT_P (operand)) 1003 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x); 1004 1005 if (cris_output_insn_is_bound) 1006 { 1007 cris_output_insn_is_bound = 0; 1008 return; 1009 } 1010 1011 putc (GET_CODE (operand) == SIGN_EXTEND 1012 || (CONST_INT_P (operand) && INTVAL (operand) < 0) 1013 ? 's' : 'u', file); 1014 return; 1015 1016 case 'm': 1017 /* Print the size letter of the inner element. We can do it by 1018 calling ourselves with the 's' modifier. */ 1019 if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND) 1020 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x); 1021 cris_print_operand (file, XEXP (operand, 0), 's'); 1022 return; 1023 1024 case 'M': 1025 /* Print the least significant part of operand. */ 1026 if (GET_CODE (operand) == CONST_DOUBLE) 1027 { 1028 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x)); 1029 return; 1030 } 1031 else if (HOST_BITS_PER_WIDE_INT > 32 && CONST_INT_P (operand)) 1032 { 1033 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 1034 INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1)); 1035 return; 1036 } 1037 /* Otherwise the least significant part equals the normal part, 1038 so handle it normally. */ 1039 break; 1040 1041 case 'A': 1042 /* When emitting an add for the high part of a DImode constant, we 1043 want to use addq for 0 and adds.w for -1. */ 1044 if (!CONST_INT_P (operand)) 1045 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x); 1046 fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq"); 1047 return; 1048 1049 case 'P': 1050 /* For const_int operands, print the additive mnemonic and the 1051 modified operand (byte-sized operands don't save anything): 1052 N=MIN_INT..-65536: add.d N 1053 -65535..-64: subu.w -N 1054 -63..-1: subq -N 1055 0..63: addq N 1056 64..65535: addu.w N 1057 65536..MAX_INT: add.d N. 1058 (Emitted mnemonics are capitalized to simplify testing.) 1059 For anything else (N.B: only register is valid), print "add.d". */ 1060 if (REG_P (operand)) 1061 { 1062 fprintf (file, "Add.d "); 1063 1064 /* Deal with printing the operand by dropping through to the 1065 normal path. */ 1066 break; 1067 } 1068 else 1069 { 1070 int val; 1071 gcc_assert (CONST_INT_P (operand)); 1072 1073 val = INTVAL (operand); 1074 if (!IN_RANGE (val, -65535, 65535)) 1075 fprintf (file, "Add.d %d", val); 1076 else if (val <= -64) 1077 fprintf (file, "Subu.w %d", -val); 1078 else if (val <= -1) 1079 fprintf (file, "Subq %d", -val); 1080 else if (val <= 63) 1081 fprintf (file, "Addq %d", val); 1082 else if (val <= 65535) 1083 fprintf (file, "Addu.w %d", val); 1084 return; 1085 } 1086 break; 1087 1088 case 'q': 1089 /* If the operand is an integer -31..31, print "q" else ".d". */ 1090 if (CONST_INT_P (operand) && IN_RANGE (INTVAL (operand), -31, 31)) 1091 fprintf (file, "q"); 1092 else 1093 fprintf (file, ".d"); 1094 return; 1095 1096 case 'd': 1097 /* If this is a GOT symbol, force it to be emitted as :GOT and 1098 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16). 1099 Avoid making this too much of a special case. */ 1100 if (flag_pic == 1 && CRIS_CONSTANT_P (operand)) 1101 { 1102 int flag_pic_save = flag_pic; 1103 1104 flag_pic = 2; 1105 cris_output_addr_const (file, operand); 1106 flag_pic = flag_pic_save; 1107 return; 1108 } 1109 break; 1110 1111 case 'D': 1112 /* When emitting an sub for the high part of a DImode constant, we 1113 want to use subq for 0 and subs.w for -1. */ 1114 if (!CONST_INT_P (operand)) 1115 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x); 1116 fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq"); 1117 return; 1118 1119 case 'S': 1120 /* Print the operand as the index-part of an address. 1121 Easiest way out is to use cris_print_index. */ 1122 cris_print_index (operand, file); 1123 return; 1124 1125 case 'T': 1126 /* Print the size letter for an operand to a MULT, which must be a 1127 const_int with a suitable value. */ 1128 if (!CONST_INT_P (operand) || INTVAL (operand) > 4) 1129 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x); 1130 fprintf (file, "%s", mults[INTVAL (operand)]); 1131 return; 1132 1133 case 'u': 1134 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */ 1135 if (flag_pic == 1 1136 && GET_CODE (operand) == CONST 1137 && GET_CODE (XEXP (operand, 0)) == UNSPEC 1138 && XINT (XEXP (operand, 0), 1) == CRIS_UNSPEC_GOTREAD) 1139 fprintf (file, "u.w"); 1140 else 1141 fprintf (file, ".d"); 1142 return; 1143 1144 case 0: 1145 /* No code, print as usual. */ 1146 break; 1147 1148 default: 1149 LOSE_AND_RETURN ("invalid operand modifier letter", x); 1150 } 1151 1152 /* Print an operand as without a modifier letter. */ 1153 switch (GET_CODE (operand)) 1154 { 1155 case REG: 1156 if (REGNO (operand) > 15 1157 && REGNO (operand) != CRIS_MOF_REGNUM 1158 && REGNO (operand) != CRIS_SRP_REGNUM 1159 && REGNO (operand) != CRIS_CC0_REGNUM) 1160 internal_error ("internal error: bad register: %d", REGNO (operand)); 1161 fprintf (file, "$%s", reg_names[REGNO (operand)]); 1162 return; 1163 1164 case MEM: 1165 output_address (XEXP (operand, 0)); 1166 return; 1167 1168 case CONST_DOUBLE: 1169 if (GET_MODE (operand) == VOIDmode) 1170 /* A long long constant. */ 1171 output_addr_const (file, operand); 1172 else 1173 { 1174 /* Only single precision is allowed as plain operands the 1175 moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't 1176 documented. */ 1177 REAL_VALUE_TYPE r; 1178 long l; 1179 1180 /* FIXME: Perhaps check overflow of the "single". */ 1181 REAL_VALUE_FROM_CONST_DOUBLE (r, operand); 1182 REAL_VALUE_TO_TARGET_SINGLE (r, l); 1183 1184 fprintf (file, "0x%lx", l); 1185 } 1186 return; 1187 1188 case UNSPEC: 1189 /* Fall through. */ 1190 case CONST: 1191 cris_output_addr_const (file, operand); 1192 return; 1193 1194 case MULT: 1195 case ASHIFT: 1196 { 1197 /* For a (MULT (reg X) const_int) we output "rX.S". */ 1198 int i = CONST_INT_P (XEXP (operand, 1)) 1199 ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0)); 1200 rtx reg = CONST_INT_P (XEXP (operand, 1)) 1201 ? XEXP (operand, 0) : XEXP (operand, 1); 1202 1203 if (!REG_P (reg) 1204 || (!CONST_INT_P (XEXP (operand, 0)) 1205 && !CONST_INT_P (XEXP (operand, 1)))) 1206 LOSE_AND_RETURN ("unexpected multiplicative operand", x); 1207 1208 cris_print_base (reg, file); 1209 fprintf (file, ".%c", 1210 i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b' 1211 : i == 4 ? 'd' 1212 : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w' 1213 : 'd'); 1214 return; 1215 } 1216 1217 default: 1218 /* No need to handle all strange variants, let output_addr_const 1219 do it for us. */ 1220 if (CRIS_CONSTANT_P (operand)) 1221 { 1222 cris_output_addr_const (file, operand); 1223 return; 1224 } 1225 1226 LOSE_AND_RETURN ("unexpected operand", x); 1227 } 1228} 1229 1230static bool 1231cris_print_operand_punct_valid_p (unsigned char code) 1232{ 1233 return (code == '#' || code == '!' || code == ':'); 1234} 1235 1236/* The PRINT_OPERAND_ADDRESS worker. */ 1237 1238static void 1239cris_print_operand_address (FILE *file, rtx x) 1240{ 1241 /* All these were inside MEM:s so output indirection characters. */ 1242 putc ('[', file); 1243 1244 if (CONSTANT_ADDRESS_P (x)) 1245 cris_output_addr_const (file, x); 1246 else if (cris_base_or_autoincr_p (x, true)) 1247 cris_print_base (x, file); 1248 else if (GET_CODE (x) == PLUS) 1249 { 1250 rtx x1, x2; 1251 1252 x1 = XEXP (x, 0); 1253 x2 = XEXP (x, 1); 1254 if (cris_base_p (x1, true)) 1255 { 1256 cris_print_base (x1, file); 1257 cris_print_index (x2, file); 1258 } 1259 else if (cris_base_p (x2, true)) 1260 { 1261 cris_print_base (x2, file); 1262 cris_print_index (x1, file); 1263 } 1264 else 1265 LOSE_AND_RETURN ("unrecognized address", x); 1266 } 1267 else if (MEM_P (x)) 1268 { 1269 /* A DIP. Output more indirection characters. */ 1270 putc ('[', file); 1271 cris_print_base (XEXP (x, 0), file); 1272 putc (']', file); 1273 } 1274 else 1275 LOSE_AND_RETURN ("unrecognized address", x); 1276 1277 putc (']', file); 1278} 1279 1280/* The RETURN_ADDR_RTX worker. 1281 We mark that the return address is used, either by EH or 1282 __builtin_return_address, for use by the function prologue and 1283 epilogue. FIXME: This isn't optimal; we just use the mark in the 1284 prologue and epilogue to say that the return address is to be stored 1285 in the stack frame. We could return SRP for leaf-functions and use the 1286 initial-value machinery. */ 1287 1288rtx 1289cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED) 1290{ 1291 cfun->machine->needs_return_address_on_stack = 1; 1292 1293 /* The return-address is stored just above the saved frame-pointer (if 1294 present). Apparently we can't eliminate from the frame-pointer in 1295 that direction, so use the incoming args (maybe pretended) pointer. */ 1296 return count == 0 1297 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, virtual_incoming_args_rtx, -4)) 1298 : NULL_RTX; 1299} 1300 1301/* Accessor used in cris.md:return because cfun->machine isn't available 1302 there. */ 1303 1304bool 1305cris_return_address_on_stack (void) 1306{ 1307 return df_regs_ever_live_p (CRIS_SRP_REGNUM) 1308 || cfun->machine->needs_return_address_on_stack; 1309} 1310 1311/* Accessor used in cris.md:return because cfun->machine isn't available 1312 there. */ 1313 1314bool 1315cris_return_address_on_stack_for_return (void) 1316{ 1317 return cfun->machine->return_type == CRIS_RETINSN_RET ? false 1318 : cris_return_address_on_stack (); 1319} 1320 1321/* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only 1322 handles FP -> SP elimination offset. */ 1323 1324static int 1325cris_initial_frame_pointer_offset (void) 1326{ 1327 int regno; 1328 1329 /* Initial offset is 0 if we don't have a frame pointer. */ 1330 int offs = 0; 1331 bool got_really_used = false; 1332 1333 if (crtl->uses_pic_offset_table) 1334 { 1335 push_topmost_sequence (); 1336 got_really_used 1337 = reg_used_between_p (pic_offset_table_rtx, get_insns (), 1338 NULL); 1339 pop_topmost_sequence (); 1340 } 1341 1342 /* And 4 for each register pushed. */ 1343 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 1344 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 1345 offs += 4; 1346 1347 /* And then, last, we add the locals allocated. */ 1348 offs += get_frame_size (); 1349 1350 /* And more; the accumulated args size. */ 1351 offs += crtl->outgoing_args_size; 1352 1353 /* Then round it off, in case we use aligned stack. */ 1354 if (TARGET_STACK_ALIGN) 1355 offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1; 1356 1357 return offs; 1358} 1359 1360/* The INITIAL_ELIMINATION_OFFSET worker. 1361 Calculate the difference between imaginary registers such as frame 1362 pointer and the stack pointer. Used to eliminate the frame pointer 1363 and imaginary arg pointer. */ 1364 1365int 1366cris_initial_elimination_offset (int fromreg, int toreg) 1367{ 1368 int fp_sp_offset 1369 = cris_initial_frame_pointer_offset (); 1370 1371 /* We should be able to use regs_ever_live and related prologue 1372 information here, or alpha should not as well. */ 1373 bool return_address_on_stack = cris_return_address_on_stack (); 1374 1375 /* Here we act as if the frame-pointer were needed. */ 1376 int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0); 1377 1378 if (fromreg == ARG_POINTER_REGNUM 1379 && toreg == FRAME_POINTER_REGNUM) 1380 return ap_fp_offset; 1381 1382 /* Between the frame pointer and the stack are only "normal" stack 1383 variables and saved registers. */ 1384 if (fromreg == FRAME_POINTER_REGNUM 1385 && toreg == STACK_POINTER_REGNUM) 1386 return fp_sp_offset; 1387 1388 /* We need to balance out the frame pointer here. */ 1389 if (fromreg == ARG_POINTER_REGNUM 1390 && toreg == STACK_POINTER_REGNUM) 1391 return ap_fp_offset + fp_sp_offset - 4; 1392 1393 gcc_unreachable (); 1394} 1395 1396/* Nonzero if X is a hard reg that can be used as an index. */ 1397static inline bool 1398reg_ok_for_base_p (const_rtx x, bool strict) 1399{ 1400 return ((! strict && ! HARD_REGISTER_P (x)) 1401 || REGNO_OK_FOR_BASE_P (REGNO (x))); 1402} 1403 1404/* Nonzero if X is a hard reg that can be used as an index. */ 1405static inline bool 1406reg_ok_for_index_p (const_rtx x, bool strict) 1407{ 1408 return reg_ok_for_base_p (x, strict); 1409} 1410 1411/* No symbol can be used as an index (or more correct, as a base) together 1412 with a register with PIC; the PIC register must be there. */ 1413 1414bool 1415cris_constant_index_p (const_rtx x) 1416{ 1417 return (CRIS_CONSTANT_P (x) && (!flag_pic || cris_valid_pic_const (x, true))); 1418} 1419 1420/* True if X is a valid base register. */ 1421 1422bool 1423cris_base_p (const_rtx x, bool strict) 1424{ 1425 return (REG_P (x) && reg_ok_for_base_p (x, strict)); 1426} 1427 1428/* True if X is a valid index register. */ 1429 1430static inline bool 1431cris_index_p (const_rtx x, bool strict) 1432{ 1433 return (REG_P (x) && reg_ok_for_index_p (x, strict)); 1434} 1435 1436/* True if X is a valid base register with or without autoincrement. */ 1437 1438bool 1439cris_base_or_autoincr_p (const_rtx x, bool strict) 1440{ 1441 return (cris_base_p (x, strict) 1442 || (GET_CODE (x) == POST_INC 1443 && cris_base_p (XEXP (x, 0), strict) 1444 && REGNO (XEXP (x, 0)) != CRIS_ACR_REGNUM)); 1445} 1446 1447/* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */ 1448 1449bool 1450cris_bdap_index_p (const_rtx x, bool strict) 1451{ 1452 return ((MEM_P (x) 1453 && GET_MODE (x) == SImode 1454 && cris_base_or_autoincr_p (XEXP (x, 0), strict)) 1455 || (GET_CODE (x) == SIGN_EXTEND 1456 && MEM_P (XEXP (x, 0)) 1457 && (GET_MODE (XEXP (x, 0)) == HImode 1458 || GET_MODE (XEXP (x, 0)) == QImode) 1459 && cris_base_or_autoincr_p (XEXP (XEXP (x, 0), 0), strict))); 1460} 1461 1462/* True if X is a valid (register) index for BIAP, i.e. Rd.m. */ 1463 1464bool 1465cris_biap_index_p (const_rtx x, bool strict) 1466{ 1467 return (cris_index_p (x, strict) 1468 || (GET_CODE (x) == MULT 1469 && cris_index_p (XEXP (x, 0), strict) 1470 && cris_scale_int_operand (XEXP (x, 1), VOIDmode))); 1471} 1472 1473/* Worker function for TARGET_LEGITIMATE_ADDRESS_P. 1474 1475 A PIC operand looks like a normal symbol here. At output we dress it 1476 in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local 1477 symbol) so we exclude all addressing modes where we can't replace a 1478 plain "symbol" with that. A global PIC symbol does not fit anywhere 1479 here (but is thankfully a general_operand in itself). A local PIC 1480 symbol is valid for the plain "symbol + offset" case. */ 1481 1482bool 1483cris_legitimate_address_p (machine_mode mode, rtx x, bool strict) 1484{ 1485 const_rtx x1, x2; 1486 1487 if (cris_base_or_autoincr_p (x, strict)) 1488 return true; 1489 else if (TARGET_V32) 1490 /* Nothing else is valid then. */ 1491 return false; 1492 else if (cris_constant_index_p (x)) 1493 return true; 1494 /* Indexed? */ 1495 else if (GET_CODE (x) == PLUS) 1496 { 1497 x1 = XEXP (x, 0); 1498 x2 = XEXP (x, 1); 1499 /* BDAP o, Rd. */ 1500 if ((cris_base_p (x1, strict) && cris_constant_index_p (x2)) 1501 || (cris_base_p (x2, strict) && cris_constant_index_p (x1)) 1502 /* BDAP Rs[+], Rd. */ 1503 || (GET_MODE_SIZE (mode) <= UNITS_PER_WORD 1504 && ((cris_base_p (x1, strict) 1505 && cris_bdap_index_p (x2, strict)) 1506 || (cris_base_p (x2, strict) 1507 && cris_bdap_index_p (x1, strict)) 1508 /* BIAP.m Rs, Rd */ 1509 || (cris_base_p (x1, strict) 1510 && cris_biap_index_p (x2, strict)) 1511 || (cris_base_p (x2, strict) 1512 && cris_biap_index_p (x1, strict))))) 1513 return true; 1514 } 1515 else if (MEM_P (x)) 1516 { 1517 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */ 1518 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD 1519 && cris_base_or_autoincr_p (XEXP (x, 0), strict)) 1520 return true; 1521 } 1522 1523 return false; 1524} 1525 1526/* Worker function for TARGET_LEGITIMATE_CONSTANT_P. We have to handle 1527 PIC constants that aren't legitimized. FIXME: there used to be a 1528 guarantee that the target LEGITIMATE_CONSTANT_P didn't have to handle 1529 PIC constants, but no more (4.7 era); testcase: glibc init-first.c. 1530 While that may be seen as a bug, that guarantee seems a wart by design, 1531 so don't bother; fix the documentation instead. */ 1532 1533bool 1534cris_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 1535{ 1536 enum cris_symbol_type t; 1537 1538 if (flag_pic) 1539 return LEGITIMATE_PIC_OPERAND_P (x); 1540 1541 t = cris_symbol_type_of (x); 1542 1543 return 1544 t == cris_no_symbol 1545 || t == cris_offsettable_symbol 1546 || t == cris_unspec; 1547} 1548 1549/* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */ 1550 1551bool 1552cris_reload_address_legitimized (rtx x, 1553 machine_mode mode ATTRIBUTE_UNUSED, 1554 int opnum ATTRIBUTE_UNUSED, 1555 int itype, 1556 int ind_levels ATTRIBUTE_UNUSED) 1557{ 1558 enum reload_type type = (enum reload_type) itype; 1559 rtx op0, op1; 1560 rtx *op1p; 1561 1562 if (GET_CODE (x) != PLUS) 1563 return false; 1564 1565 if (TARGET_V32) 1566 return false; 1567 1568 op0 = XEXP (x, 0); 1569 op1 = XEXP (x, 1); 1570 op1p = &XEXP (x, 1); 1571 1572 if (!REG_P (op1)) 1573 return false; 1574 1575 if (GET_CODE (op0) == SIGN_EXTEND && MEM_P (XEXP (op0, 0))) 1576 { 1577 rtx op00 = XEXP (op0, 0); 1578 rtx op000 = XEXP (op00, 0); 1579 rtx *op000p = &XEXP (op00, 0); 1580 1581 if ((GET_MODE (op00) == HImode || GET_MODE (op00) == QImode) 1582 && (REG_P (op000) 1583 || (GET_CODE (op000) == POST_INC && REG_P (XEXP (op000, 0))))) 1584 { 1585 bool something_reloaded = false; 1586 1587 if (GET_CODE (op000) == POST_INC 1588 && REG_P (XEXP (op000, 0)) 1589 && REGNO (XEXP (op000, 0)) > CRIS_LAST_GENERAL_REGISTER) 1590 /* No, this gets too complicated and is too rare to care 1591 about trying to improve on the general code Here. 1592 As the return-value is an all-or-nothing indicator, we 1593 punt on the other register too. */ 1594 return false; 1595 1596 if ((REG_P (op000) 1597 && REGNO (op000) > CRIS_LAST_GENERAL_REGISTER)) 1598 { 1599 /* The address of the inner mem is a pseudo or wrong 1600 reg: reload that. */ 1601 push_reload (op000, NULL_RTX, op000p, NULL, GENERAL_REGS, 1602 GET_MODE (x), VOIDmode, 0, 0, opnum, type); 1603 something_reloaded = true; 1604 } 1605 1606 if (REGNO (op1) > CRIS_LAST_GENERAL_REGISTER) 1607 { 1608 /* Base register is a pseudo or wrong reg: reload it. */ 1609 push_reload (op1, NULL_RTX, op1p, NULL, GENERAL_REGS, 1610 GET_MODE (x), VOIDmode, 0, 0, 1611 opnum, type); 1612 something_reloaded = true; 1613 } 1614 1615 gcc_assert (something_reloaded); 1616 1617 return true; 1618 } 1619 } 1620 1621 return false; 1622} 1623 1624 1625/* Worker function for TARGET_PREFERRED_RELOAD_CLASS. 1626 1627 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as 1628 the class for a constant (testcase: __Mul in arit.c). To avoid forcing 1629 out a constant into the constant pool, we will trap this case and 1630 return something a bit more sane. FIXME: Check if this is a bug. 1631 Beware that we must not "override" classes that can be specified as 1632 constraint letters, or else asm operands using them will fail when 1633 they need to be reloaded. FIXME: Investigate whether that constitutes 1634 a bug. */ 1635 1636static reg_class_t 1637cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) 1638{ 1639 if (rclass != ACR_REGS 1640 && rclass != MOF_REGS 1641 && rclass != MOF_SRP_REGS 1642 && rclass != SRP_REGS 1643 && rclass != CC0_REGS 1644 && rclass != SPECIAL_REGS) 1645 return GENERAL_REGS; 1646 1647 return rclass; 1648} 1649 1650/* Worker function for TARGET_REGISTER_MOVE_COST. */ 1651 1652static int 1653cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 1654 reg_class_t from, reg_class_t to) 1655{ 1656 /* Can't move to and from a SPECIAL_REGS register, so we have to say 1657 their move cost within that class is higher. How about 7? That's 3 1658 for a move to a GENERAL_REGS register, 3 for the move from the 1659 GENERAL_REGS register, and 1 for the increased register pressure. 1660 Also, it's higher than the memory move cost, as it should. 1661 We also do this for ALL_REGS, since we don't want that class to be 1662 preferred (even to memory) at all where GENERAL_REGS doesn't fit. 1663 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't 1664 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be 1665 used when a GENERAL_REGS should be used, even if there are call-saved 1666 GENERAL_REGS left to allocate. This is because the fall-back when 1667 the most preferred register class isn't available, isn't the next 1668 (or next good) wider register class, but the *most widest* register 1669 class. FIXME: pre-IRA comment, perhaps obsolete now. */ 1670 1671 if ((reg_classes_intersect_p (from, SPECIAL_REGS) 1672 && reg_classes_intersect_p (to, SPECIAL_REGS)) 1673 || from == ALL_REGS || to == ALL_REGS) 1674 return 7; 1675 1676 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we 1677 generally prefer GENERAL_REGS. */ 1678 if (reg_classes_intersect_p (from, SPECIAL_REGS) 1679 || reg_classes_intersect_p (to, SPECIAL_REGS)) 1680 return 3; 1681 1682 return 2; 1683} 1684 1685/* Worker function for TARGET_MEMORY_MOVE_COST. 1686 1687 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should 1688 suffice. */ 1689 1690static int 1691cris_memory_move_cost (machine_mode mode, 1692 reg_class_t rclass ATTRIBUTE_UNUSED, 1693 bool in ATTRIBUTE_UNUSED) 1694{ 1695 if (mode == QImode 1696 || mode == HImode) 1697 return 4; 1698 else 1699 return 6; 1700} 1701 1702/* Worker for cris_notice_update_cc; handles the "normal" cases. 1703 FIXME: this code is historical; its functionality should be 1704 refactored to look at insn attributes and moved to 1705 cris_notice_update_cc. Except, we better lose cc0 entirely. */ 1706 1707static void 1708cris_normal_notice_update_cc (rtx exp, rtx insn) 1709{ 1710 /* "Normal" means, for: 1711 (set (cc0) (...)): 1712 CC is (...). 1713 1714 (set (reg) (...)): 1715 CC is (reg) and (...) - unless (...) is 0 or reg is a special 1716 register or (v32 and (...) is -32..-1), then CC does not change. 1717 CC_NO_OVERFLOW unless (...) is reg or mem. 1718 1719 (set (mem) (...)): 1720 CC does not change. 1721 1722 (set (pc) (...)): 1723 CC does not change. 1724 1725 (parallel 1726 (set (reg1) (mem (bdap/biap))) 1727 (set (reg2) (bdap/biap))): 1728 CC is (reg1) and (mem (reg2)) 1729 1730 (parallel 1731 (set (mem (bdap/biap)) (reg1)) [or 0] 1732 (set (reg2) (bdap/biap))): 1733 CC does not change. 1734 1735 (where reg and mem includes strict_low_parts variants thereof) 1736 1737 For all others, assume CC is clobbered. 1738 Note that we do not have to care about setting CC_NO_OVERFLOW, 1739 since the overflow flag is set to 0 (i.e. right) for 1740 instructions where it does not have any sane sense, but where 1741 other flags have meanings. (This includes shifts; the carry is 1742 not set by them). 1743 1744 Note that there are other parallel constructs we could match, 1745 but we don't do that yet. */ 1746 1747 if (GET_CODE (exp) == SET) 1748 { 1749 /* FIXME: Check when this happens. It looks like we should 1750 actually do a CC_STATUS_INIT here to be safe. */ 1751 if (SET_DEST (exp) == pc_rtx) 1752 return; 1753 1754 /* Record CC0 changes, so we do not have to output multiple 1755 test insns. */ 1756 if (SET_DEST (exp) == cc0_rtx) 1757 { 1758 CC_STATUS_INIT; 1759 1760 if (GET_CODE (SET_SRC (exp)) == COMPARE 1761 && XEXP (SET_SRC (exp), 1) == const0_rtx) 1762 cc_status.value1 = XEXP (SET_SRC (exp), 0); 1763 else 1764 cc_status.value1 = SET_SRC (exp); 1765 1766 /* Handle flags for the special btstq on one bit. */ 1767 if (GET_CODE (cc_status.value1) == ZERO_EXTRACT 1768 && XEXP (cc_status.value1, 1) == const1_rtx) 1769 { 1770 if (CONST_INT_P (XEXP (cc_status.value1, 0))) 1771 /* Using cmpq. */ 1772 cc_status.flags = CC_INVERTED; 1773 else 1774 /* A one-bit btstq. */ 1775 cc_status.flags = CC_Z_IN_NOT_N; 1776 } 1777 1778 else if (GET_CODE (SET_SRC (exp)) == COMPARE) 1779 { 1780 if (!REG_P (XEXP (SET_SRC (exp), 0)) 1781 && XEXP (SET_SRC (exp), 1) != const0_rtx) 1782 /* For some reason gcc will not canonicalize compare 1783 operations, reversing the sign by itself if 1784 operands are in wrong order. */ 1785 /* (But NOT inverted; eq is still eq.) */ 1786 cc_status.flags = CC_REVERSED; 1787 1788 /* This seems to be overlooked by gcc. FIXME: Check again. 1789 FIXME: Is it really safe? */ 1790 cc_status.value2 1791 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)), 1792 XEXP (SET_SRC (exp), 0), 1793 XEXP (SET_SRC (exp), 1)); 1794 } 1795 return; 1796 } 1797 else if (REG_P (SET_DEST (exp)) 1798 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART 1799 && REG_P (XEXP (SET_DEST (exp), 0)))) 1800 { 1801 /* A register is set; normally CC is set to show that no 1802 test insn is needed. Catch the exceptions. */ 1803 1804 /* If not to cc0, then no "set"s in non-natural mode give 1805 ok cc0... */ 1806 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD 1807 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT) 1808 { 1809 /* ... except add:s and sub:s in DImode. */ 1810 if (GET_MODE (SET_DEST (exp)) == DImode 1811 && (GET_CODE (SET_SRC (exp)) == PLUS 1812 || GET_CODE (SET_SRC (exp)) == MINUS)) 1813 { 1814 CC_STATUS_INIT; 1815 cc_status.value1 = SET_DEST (exp); 1816 cc_status.value2 = SET_SRC (exp); 1817 1818 if (cris_reg_overlap_mentioned_p (cc_status.value1, 1819 cc_status.value2)) 1820 cc_status.value2 = 0; 1821 1822 /* Add and sub may set V, which gets us 1823 unoptimizable results in "gt" and "le" condition 1824 codes. */ 1825 cc_status.flags |= CC_NO_OVERFLOW; 1826 1827 return; 1828 } 1829 } 1830 else if (SET_SRC (exp) == const0_rtx 1831 || (REG_P (SET_SRC (exp)) 1832 && (REGNO (SET_SRC (exp)) 1833 > CRIS_LAST_GENERAL_REGISTER)) 1834 || (TARGET_V32 1835 && REG_P (SET_DEST (exp)) 1836 && satisfies_constraint_I (SET_SRC (exp)))) 1837 { 1838 /* There's no CC0 change for this case. Just check 1839 for overlap. */ 1840 if (cc_status.value1 1841 && modified_in_p (cc_status.value1, insn)) 1842 cc_status.value1 = 0; 1843 1844 if (cc_status.value2 1845 && modified_in_p (cc_status.value2, insn)) 1846 cc_status.value2 = 0; 1847 1848 return; 1849 } 1850 else 1851 { 1852 CC_STATUS_INIT; 1853 cc_status.value1 = SET_DEST (exp); 1854 cc_status.value2 = SET_SRC (exp); 1855 1856 if (cris_reg_overlap_mentioned_p (cc_status.value1, 1857 cc_status.value2)) 1858 cc_status.value2 = 0; 1859 1860 /* Some operations may set V, which gets us 1861 unoptimizable results in "gt" and "le" condition 1862 codes. */ 1863 if (GET_CODE (SET_SRC (exp)) == PLUS 1864 || GET_CODE (SET_SRC (exp)) == MINUS 1865 || GET_CODE (SET_SRC (exp)) == NEG) 1866 cc_status.flags |= CC_NO_OVERFLOW; 1867 1868 /* For V32, nothing with a register destination sets 1869 C and V usefully. */ 1870 if (TARGET_V32) 1871 cc_status.flags |= CC_NO_OVERFLOW; 1872 1873 return; 1874 } 1875 } 1876 else if (MEM_P (SET_DEST (exp)) 1877 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART 1878 && MEM_P (XEXP (SET_DEST (exp), 0)))) 1879 { 1880 /* When SET to MEM, then CC is not changed (except for 1881 overlap). */ 1882 if (cc_status.value1 1883 && modified_in_p (cc_status.value1, insn)) 1884 cc_status.value1 = 0; 1885 1886 if (cc_status.value2 1887 && modified_in_p (cc_status.value2, insn)) 1888 cc_status.value2 = 0; 1889 1890 return; 1891 } 1892 } 1893 else if (GET_CODE (exp) == PARALLEL) 1894 { 1895 if (GET_CODE (XVECEXP (exp, 0, 0)) == SET 1896 && GET_CODE (XVECEXP (exp, 0, 1)) == SET 1897 && REG_P (XEXP (XVECEXP (exp, 0, 1), 0))) 1898 { 1899 if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0)) 1900 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 1))) 1901 { 1902 CC_STATUS_INIT; 1903 1904 /* For "move.S [rx=ry+o],rz", say CC reflects 1905 value1=rz and value2=[rx] */ 1906 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0); 1907 cc_status.value2 1908 = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1), 1909 XEXP (XVECEXP (exp, 0, 1), 0)); 1910 1911 /* Huh? A side-effect cannot change the destination 1912 register. */ 1913 if (cris_reg_overlap_mentioned_p (cc_status.value1, 1914 cc_status.value2)) 1915 internal_error ("internal error: sideeffect-insn affecting main effect"); 1916 1917 /* For V32, moves to registers don't set C and V. */ 1918 if (TARGET_V32) 1919 cc_status.flags |= CC_NO_OVERFLOW; 1920 return; 1921 } 1922 else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1)) 1923 || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx) 1924 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 0))) 1925 { 1926 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]", 1927 say flags are not changed, except for overlap. */ 1928 if (cc_status.value1 1929 && modified_in_p (cc_status.value1, insn)) 1930 cc_status.value1 = 0; 1931 1932 if (cc_status.value2 1933 && modified_in_p (cc_status.value2, insn)) 1934 cc_status.value2 = 0; 1935 1936 return; 1937 } 1938 } 1939 } 1940 1941 /* If we got here, the case wasn't covered by the code above. */ 1942 CC_STATUS_INIT; 1943} 1944 1945/* This function looks into the pattern to see how this insn affects 1946 condition codes. 1947 1948 Used when to eliminate test insns before a condition-code user, 1949 such as a "scc" insn or a conditional branch. This includes 1950 checking if the entities that cc was updated by, are changed by the 1951 operation. 1952 1953 Currently a jumble of the old peek-inside-the-insn and the newer 1954 check-cc-attribute methods. */ 1955 1956void 1957cris_notice_update_cc (rtx exp, rtx_insn *insn) 1958{ 1959 enum attr_cc attrval = get_attr_cc (insn); 1960 1961 /* Check if user specified "-mcc-init" as a bug-workaround. Remember 1962 to still set CC_REVERSED as below, since that's required by some 1963 compare insn alternatives. (FIXME: GCC should do this virtual 1964 operand swap by itself.) A test-case that may otherwise fail is 1965 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */ 1966 if (TARGET_CCINIT) 1967 { 1968 CC_STATUS_INIT; 1969 1970 if (attrval == CC_REV) 1971 cc_status.flags = CC_REVERSED; 1972 return; 1973 } 1974 1975 /* Slowly, we're converting to using attributes to control the setting 1976 of condition-code status. */ 1977 switch (attrval) 1978 { 1979 case CC_NONE: 1980 /* Even if it is "none", a setting may clobber a previous 1981 cc-value, so check. */ 1982 if (GET_CODE (exp) == SET) 1983 { 1984 if (cc_status.value1 1985 && modified_in_p (cc_status.value1, insn)) 1986 cc_status.value1 = 0; 1987 1988 if (cc_status.value2 1989 && modified_in_p (cc_status.value2, insn)) 1990 cc_status.value2 = 0; 1991 } 1992 return; 1993 1994 case CC_CLOBBER: 1995 CC_STATUS_INIT; 1996 return; 1997 1998 case CC_REV: 1999 case CC_NOOV32: 2000 case CC_NORMAL: 2001 cris_normal_notice_update_cc (exp, insn); 2002 2003 /* The "test" insn doesn't clear (carry and) overflow on V32. We 2004 can change bge => bpl and blt => bmi by passing on to the cc0 2005 user that V should not be considered; bgt and ble are taken 2006 care of by other methods (see {tst,cmp}{si,hi,qi}). */ 2007 if (attrval == CC_NOOV32 && TARGET_V32) 2008 cc_status.flags |= CC_NO_OVERFLOW; 2009 return; 2010 2011 default: 2012 internal_error ("unknown cc_attr value"); 2013 } 2014 2015 CC_STATUS_INIT; 2016} 2017 2018/* Return != 0 if the return sequence for the current function is short, 2019 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if 2020 registers must be saved, so return 0 then. */ 2021 2022bool 2023cris_simple_epilogue (void) 2024{ 2025 unsigned int regno; 2026 unsigned int reglimit = STACK_POINTER_REGNUM; 2027 bool got_really_used = false; 2028 2029 if (! reload_completed 2030 || frame_pointer_needed 2031 || get_frame_size () != 0 2032 || crtl->args.pretend_args_size 2033 || crtl->args.size 2034 || crtl->outgoing_args_size 2035 || crtl->calls_eh_return 2036 2037 /* If we're not supposed to emit prologue and epilogue, we must 2038 not emit return-type instructions. */ 2039 || !TARGET_PROLOGUE_EPILOGUE) 2040 return false; 2041 2042 /* Can't return from stacked return address with v32. */ 2043 if (TARGET_V32 && cris_return_address_on_stack ()) 2044 return false; 2045 2046 if (crtl->uses_pic_offset_table) 2047 { 2048 push_topmost_sequence (); 2049 got_really_used 2050 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); 2051 pop_topmost_sequence (); 2052 } 2053 2054 /* No simple epilogue if there are saved registers. */ 2055 for (regno = 0; regno < reglimit; regno++) 2056 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 2057 return false; 2058 2059 return true; 2060} 2061 2062/* Emit checking that MEM is aligned for an access in MODE, failing 2063 that, executing a "break 8" (or call to abort, if "break 8" is 2064 disabled). */ 2065 2066void 2067cris_emit_trap_for_misalignment (rtx mem) 2068{ 2069 rtx addr, reg, ok_label, andop; 2070 rtx_insn *jmp; 2071 int natural_alignment; 2072 gcc_assert (MEM_P (mem)); 2073 2074 natural_alignment = GET_MODE_SIZE (GET_MODE (mem)); 2075 addr = XEXP (mem, 0); 2076 reg = force_reg (Pmode, addr); 2077 ok_label = gen_label_rtx (); 2078 2079 /* This will yield a btstq without a separate register used, usually - 2080 with the exception for PRE hoisting the "and" but not the branch 2081 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */ 2082 andop = gen_rtx_AND (Pmode, reg, GEN_INT (natural_alignment - 1)); 2083 emit_cmp_and_jump_insns (force_reg (SImode, andop), const0_rtx, EQ, 2084 NULL_RTX, Pmode, 1, ok_label); 2085 jmp = get_last_insn (); 2086 gcc_assert (JUMP_P (jmp)); 2087 2088 predict_insn_def (jmp, PRED_NORETURN, TAKEN); 2089 expand_builtin_trap (); 2090 emit_label (ok_label); 2091} 2092 2093/* Expand a return insn (just one insn) marked as using SRP or stack 2094 slot depending on parameter ON_STACK. */ 2095 2096void 2097cris_expand_return (bool on_stack) 2098{ 2099 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to 2100 tell "ret" from "jump [sp+]". Some, but not all, other parts of 2101 GCC expect just (return) to do the right thing when optimizing, so 2102 we do that until they're fixed. Currently, all return insns in a 2103 function must be the same (not really a limiting factor) so we need 2104 to check that it doesn't change half-way through. */ 2105 emit_jump_insn (ret_rtx); 2106 2107 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack); 2108 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack); 2109 2110 cfun->machine->return_type 2111 = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET; 2112} 2113 2114/* Compute a (partial) cost for rtx X. Return true if the complete 2115 cost has been computed, and false if subexpressions should be 2116 scanned. In either case, *TOTAL contains the cost result. */ 2117 2118static bool 2119cris_rtx_costs (rtx x, int code, int outer_code, int opno, int *total, 2120 bool speed) 2121{ 2122 switch (code) 2123 { 2124 case CONST_INT: 2125 { 2126 HOST_WIDE_INT val = INTVAL (x); 2127 if (val == 0) 2128 *total = 0; 2129 else if (val < 32 && val >= -32) 2130 *total = 1; 2131 /* Eight or 16 bits are a word and cycle more expensive. */ 2132 else if (val <= 32767 && val >= -32768) 2133 *total = 2; 2134 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs 2135 another word. FIXME: This isn't linear to 16 bits. */ 2136 else 2137 *total = 4; 2138 return true; 2139 } 2140 2141 case LABEL_REF: 2142 *total = 6; 2143 return true; 2144 2145 case CONST: 2146 case SYMBOL_REF: 2147 *total = 6; 2148 return true; 2149 2150 case CONST_DOUBLE: 2151 if (x != CONST0_RTX (GET_MODE (x) == VOIDmode ? DImode : GET_MODE (x))) 2152 *total = 12; 2153 else 2154 /* Make 0.0 cheap, else test-insns will not be used. */ 2155 *total = 0; 2156 return true; 2157 2158 case MULT: 2159 /* If we have one arm of an ADDI, make sure it gets the cost of 2160 one insn, i.e. zero cost for this operand, and just the cost 2161 of the PLUS, as the insn is created by combine from a PLUS 2162 and an ASHIFT, and the MULT cost below would make the 2163 combined value be larger than the separate insns. The insn 2164 validity is checked elsewhere by combine. 2165 2166 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole 2167 function should be rewritten. */ 2168 if (outer_code == PLUS && cris_biap_index_p (x, false)) 2169 { 2170 *total = 0; 2171 return true; 2172 } 2173 2174 /* Identify values that are no powers of two. Powers of 2 are 2175 taken care of already and those values should not be changed. */ 2176 if (!CONST_INT_P (XEXP (x, 1)) 2177 || exact_log2 (INTVAL (XEXP (x, 1)) < 0)) 2178 { 2179 /* If we have a multiply insn, then the cost is between 2180 1 and 2 "fast" instructions. */ 2181 if (TARGET_HAS_MUL_INSNS) 2182 { 2183 *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2; 2184 return true; 2185 } 2186 2187 /* Estimate as 4 + 4 * #ofbits. */ 2188 *total = COSTS_N_INSNS (132); 2189 return true; 2190 } 2191 return false; 2192 2193 case UDIV: 2194 case MOD: 2195 case UMOD: 2196 case DIV: 2197 if (!CONST_INT_P (XEXP (x, 1)) 2198 || exact_log2 (INTVAL (XEXP (x, 1)) < 0)) 2199 { 2200 /* Estimate this as 4 + 8 * #of bits. */ 2201 *total = COSTS_N_INSNS (260); 2202 return true; 2203 } 2204 return false; 2205 2206 case AND: 2207 if (CONST_INT_P (XEXP (x, 1)) 2208 /* Two constants may actually happen before optimization. */ 2209 && !CONST_INT_P (XEXP (x, 0)) 2210 && !satisfies_constraint_I (XEXP (x, 1))) 2211 { 2212 *total 2213 = (rtx_cost (XEXP (x, 0), (enum rtx_code) outer_code, 2214 opno, speed) + 2 2215 + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x, 0)))); 2216 return true; 2217 } 2218 return false; 2219 2220 case ZERO_EXTRACT: 2221 if (outer_code != COMPARE) 2222 return false; 2223 /* fall through */ 2224 2225 case ZERO_EXTEND: case SIGN_EXTEND: 2226 *total = rtx_cost (XEXP (x, 0), (enum rtx_code) outer_code, opno, speed); 2227 return true; 2228 2229 default: 2230 return false; 2231 } 2232} 2233 2234/* The ADDRESS_COST worker. */ 2235 2236static int 2237cris_address_cost (rtx x, machine_mode mode ATTRIBUTE_UNUSED, 2238 addr_space_t as ATTRIBUTE_UNUSED, 2239 bool speed ATTRIBUTE_UNUSED) 2240{ 2241 /* The metric to use for the cost-macros is unclear. 2242 The metric used here is (the number of cycles needed) / 2, 2243 where we consider equal a cycle for a word of code and a cycle to 2244 read memory. FIXME: Adding "+ 1" to all values would avoid 2245 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes" 2246 0 to 1, thereby giving equal costs to [rN + rM] and [rN]. 2247 Unfortunately(?) such a hack would expose other pessimizations, 2248 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the 2249 loop there, without apparent reason. */ 2250 2251 /* The cheapest addressing modes get 0, since nothing extra is needed. */ 2252 if (cris_base_or_autoincr_p (x, false)) 2253 return 0; 2254 2255 /* An indirect mem must be a DIP. This means two bytes extra for code, 2256 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */ 2257 if (MEM_P (x)) 2258 return (2 + 4) / 2; 2259 2260 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs 2261 an extra DIP prefix and 4 bytes of constant in most cases. */ 2262 if (CONSTANT_P (x)) 2263 return (2 + 4) / 2; 2264 2265 /* Handle BIAP and BDAP prefixes. */ 2266 if (GET_CODE (x) == PLUS) 2267 { 2268 rtx tem1 = XEXP (x, 0); 2269 rtx tem2 = XEXP (x, 1); 2270 2271 /* Local extended canonicalization rule: the first operand must 2272 be REG, unless it's an operation (MULT). */ 2273 if (!REG_P (tem1) && GET_CODE (tem1) != MULT) 2274 tem1 = tem2, tem2 = XEXP (x, 0); 2275 2276 /* We'll "assume" we have canonical RTX now. */ 2277 gcc_assert (REG_P (tem1) || GET_CODE (tem1) == MULT); 2278 2279 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We 2280 recognize the typical MULT which is always in tem1 because of 2281 insn canonicalization. */ 2282 if ((GET_CODE (tem1) == MULT && cris_biap_index_p (tem1, false)) 2283 || REG_P (tem2)) 2284 return 2 / 2; 2285 2286 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the 2287 PLUS is always found in tem2. */ 2288 if (CONST_INT_P (tem2) && INTVAL (tem2) < 128 && INTVAL (tem2) >= -128) 2289 return 2 / 2; 2290 2291 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra 2292 bytes. */ 2293 if (satisfies_constraint_L (tem2)) 2294 return (2 + 2) / 2; 2295 2296 /* A BDAP with some other constant is 2 bytes extra. */ 2297 if (CRIS_CONSTANT_P (tem2)) 2298 return (2 + 2 + 2) / 2; 2299 2300 /* BDAP with something indirect should have a higher cost than 2301 BIAP with register. FIXME: Should it cost like a MEM or more? */ 2302 return (2 + 2 + 2) / 2; 2303 } 2304 2305 /* What else? Return a high cost. It matters only for valid 2306 addressing modes. */ 2307 return 10; 2308} 2309 2310/* Check various objections to the side-effect. Used in the test-part 2311 of an anonymous insn describing an insn with a possible side-effect. 2312 Returns nonzero if the implied side-effect is ok. 2313 2314 code : PLUS or MULT 2315 ops : An array of rtx:es. lreg, rreg, rval, 2316 The variables multop and other_op are indexes into this, 2317 or -1 if they are not applicable. 2318 lreg : The register that gets assigned in the side-effect. 2319 rreg : One register in the side-effect expression 2320 rval : The other register, or an int. 2321 multop : An integer to multiply rval with. 2322 other_op : One of the entities of the main effect, 2323 whose mode we must consider. */ 2324 2325int 2326cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, 2327 int lreg, int rreg, int rval, 2328 int multop, int other_op) 2329{ 2330 /* Find what value to multiply with, for rx =ry + rz * n. */ 2331 int mult = multop < 0 ? 1 : INTVAL (ops[multop]); 2332 2333 rtx reg_rtx = ops[rreg]; 2334 rtx val_rtx = ops[rval]; 2335 2336 /* The operands may be swapped. Canonicalize them in reg_rtx and 2337 val_rtx, where reg_rtx always is a reg (for this constraint to 2338 match). */ 2339 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) 2340 reg_rtx = val_rtx, val_rtx = ops[rreg]; 2341 2342 /* Don't forget to check that reg_rtx really is a reg. If it isn't, 2343 we have no business. */ 2344 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) 2345 return 0; 2346 2347 /* Don't do this when -mno-split. */ 2348 if (!TARGET_SIDE_EFFECT_PREFIXES) 2349 return 0; 2350 2351 /* The mult expression may be hidden in lreg. FIXME: Add more 2352 commentary about that. */ 2353 if (GET_CODE (val_rtx) == MULT) 2354 { 2355 mult = INTVAL (XEXP (val_rtx, 1)); 2356 val_rtx = XEXP (val_rtx, 0); 2357 code = MULT; 2358 } 2359 2360 /* First check the "other operand". */ 2361 if (other_op >= 0) 2362 { 2363 if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD) 2364 return 0; 2365 2366 /* Check if the lvalue register is the same as the "other 2367 operand". If so, the result is undefined and we shouldn't do 2368 this. FIXME: Check again. */ 2369 if ((cris_base_p (ops[lreg], reload_in_progress || reload_completed) 2370 && cris_base_p (ops[other_op], 2371 reload_in_progress || reload_completed) 2372 && REGNO (ops[lreg]) == REGNO (ops[other_op])) 2373 || rtx_equal_p (ops[other_op], ops[lreg])) 2374 return 0; 2375 } 2376 2377 /* Do not accept frame_pointer_rtx as any operand. */ 2378 if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx 2379 || ops[rval] == frame_pointer_rtx 2380 || (other_op >= 0 && ops[other_op] == frame_pointer_rtx)) 2381 return 0; 2382 2383 if (code == PLUS 2384 && ! cris_base_p (val_rtx, reload_in_progress || reload_completed)) 2385 { 2386 2387 /* Do not allow rx = rx + n if a normal add or sub with same size 2388 would do. */ 2389 if (rtx_equal_p (ops[lreg], reg_rtx) 2390 && CONST_INT_P (val_rtx) 2391 && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63)) 2392 return 0; 2393 2394 /* Check allowed cases, like [r(+)?].[bwd] and const. */ 2395 if (CRIS_CONSTANT_P (val_rtx)) 2396 return 1; 2397 2398 if (MEM_P (val_rtx) 2399 && cris_base_or_autoincr_p (XEXP (val_rtx, 0), 2400 reload_in_progress || reload_completed)) 2401 return 1; 2402 2403 if (GET_CODE (val_rtx) == SIGN_EXTEND 2404 && MEM_P (XEXP (val_rtx, 0)) 2405 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx, 0), 0), 2406 reload_in_progress || reload_completed)) 2407 return 1; 2408 2409 /* If we got here, it's not a valid addressing mode. */ 2410 return 0; 2411 } 2412 else if (code == MULT 2413 || (code == PLUS 2414 && cris_base_p (val_rtx, 2415 reload_in_progress || reload_completed))) 2416 { 2417 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */ 2418 if (rtx_equal_p (ops[lreg], reg_rtx) 2419 || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx))) 2420 return 0; 2421 2422 /* Do not allow bad multiply-values. */ 2423 if (mult != 1 && mult != 2 && mult != 4) 2424 return 0; 2425 2426 /* Only allow r + ... */ 2427 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) 2428 return 0; 2429 2430 /* If we got here, all seems ok. 2431 (All checks need to be done above). */ 2432 return 1; 2433 } 2434 2435 /* If we get here, the caller got its initial tests wrong. */ 2436 internal_error ("internal error: cris_side_effect_mode_ok with bad operands"); 2437} 2438 2439/* Whether next_cc0_user of insn is LE or GT or requires a real compare 2440 insn for other reasons. */ 2441 2442bool 2443cris_cc0_user_requires_cmp (rtx insn) 2444{ 2445 rtx_insn *cc0_user = NULL; 2446 rtx body; 2447 rtx set; 2448 2449 gcc_assert (insn != NULL); 2450 2451 if (!TARGET_V32) 2452 return false; 2453 2454 cc0_user = next_cc0_user (insn); 2455 if (cc0_user == NULL) 2456 return false; 2457 2458 body = PATTERN (cc0_user); 2459 set = single_set (cc0_user); 2460 2461 /* Users can be sCC and bCC. */ 2462 if (JUMP_P (cc0_user) 2463 && GET_CODE (body) == SET 2464 && SET_DEST (body) == pc_rtx 2465 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE 2466 && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx) 2467 { 2468 return 2469 GET_CODE (XEXP (SET_SRC (body), 0)) == GT 2470 || GET_CODE (XEXP (SET_SRC (body), 0)) == LE; 2471 } 2472 else if (set) 2473 { 2474 return 2475 GET_CODE (SET_SRC (body)) == GT 2476 || GET_CODE (SET_SRC (body)) == LE; 2477 } 2478 2479 gcc_unreachable (); 2480} 2481 2482/* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16) 2483 does not handle the case where the IN operand is strict_low_part; it 2484 does handle it for X. Test-case in Axis-20010516. This function takes 2485 care of that for THIS port. FIXME: strict_low_part is going away 2486 anyway. */ 2487 2488static int 2489cris_reg_overlap_mentioned_p (rtx x, rtx in) 2490{ 2491 /* The function reg_overlap_mentioned now handles when X is 2492 strict_low_part, but not when IN is a STRICT_LOW_PART. */ 2493 if (GET_CODE (in) == STRICT_LOW_PART) 2494 in = XEXP (in, 0); 2495 2496 return reg_overlap_mentioned_p (x, in); 2497} 2498 2499/* Return TRUE iff X is a CONST valid for e.g. indexing. 2500 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1 2501 elsewhere. */ 2502 2503bool 2504cris_valid_pic_const (const_rtx x, bool any_operand) 2505{ 2506 gcc_assert (flag_pic); 2507 2508 switch (GET_CODE (x)) 2509 { 2510 case CONST_INT: 2511 case CONST_DOUBLE: 2512 return true; 2513 default: 2514 ; 2515 } 2516 2517 if (GET_CODE (x) != CONST) 2518 return false; 2519 2520 x = XEXP (x, 0); 2521 2522 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */ 2523 if (GET_CODE (x) == PLUS 2524 && GET_CODE (XEXP (x, 0)) == UNSPEC 2525 && (XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL 2526 || XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_PCREL) 2527 && CONST_INT_P (XEXP (x, 1))) 2528 x = XEXP (x, 0); 2529 2530 if (GET_CODE (x) == UNSPEC) 2531 switch (XINT (x, 1)) 2532 { 2533 /* A PCREL operand is only valid for call and movsi. */ 2534 case CRIS_UNSPEC_PLT_PCREL: 2535 case CRIS_UNSPEC_PCREL: 2536 return !any_operand; 2537 2538 case CRIS_UNSPEC_PLT_GOTREL: 2539 case CRIS_UNSPEC_PLTGOTREAD: 2540 case CRIS_UNSPEC_GOTREAD: 2541 case CRIS_UNSPEC_GOTREL: 2542 return true; 2543 default: 2544 gcc_unreachable (); 2545 } 2546 2547 return cris_symbol_type_of (x) == cris_no_symbol; 2548} 2549 2550/* Helper function to find the right symbol-type to generate, 2551 given the original (non-PIC) representation. */ 2552 2553enum cris_symbol_type 2554cris_symbol_type_of (const_rtx x) 2555{ 2556 switch (GET_CODE (x)) 2557 { 2558 case SYMBOL_REF: 2559 return flag_pic 2560 ? (SYMBOL_REF_LOCAL_P (x) 2561 ? cris_rel_symbol : cris_got_symbol) 2562 : cris_offsettable_symbol; 2563 2564 case LABEL_REF: 2565 return flag_pic ? cris_rel_symbol : cris_offsettable_symbol; 2566 2567 case CONST: 2568 return cris_symbol_type_of (XEXP (x, 0)); 2569 2570 case PLUS: 2571 case MINUS: 2572 { 2573 enum cris_symbol_type t1 = cris_symbol_type_of (XEXP (x, 0)); 2574 enum cris_symbol_type t2 = cris_symbol_type_of (XEXP (x, 1)); 2575 2576 gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol); 2577 2578 if (t1 == cris_got_symbol || t2 == cris_got_symbol) 2579 return cris_got_symbol_needing_fixup; 2580 2581 return t1 != cris_no_symbol ? t1 : t2; 2582 } 2583 2584 case CONST_INT: 2585 case CONST_DOUBLE: 2586 return cris_no_symbol; 2587 2588 case UNSPEC: 2589 return cris_unspec; 2590 2591 default: 2592 fatal_insn ("unrecognized supposed constant", x); 2593 } 2594 2595 gcc_unreachable (); 2596} 2597 2598/* The LEGITIMATE_PIC_OPERAND_P worker. */ 2599 2600int 2601cris_legitimate_pic_operand (rtx x) 2602{ 2603 /* Symbols are not valid PIC operands as-is; just constants. */ 2604 return cris_valid_pic_const (x, true); 2605} 2606 2607/* Queue an .ident string in the queue of top-level asm statements. 2608 If the front-end is done, we must be being called from toplev.c. 2609 In that case, do nothing. */ 2610void 2611cris_asm_output_ident (const char *string) 2612{ 2613 if (symtab->state != PARSING) 2614 return; 2615 2616 default_asm_output_ident_directive (string); 2617} 2618 2619/* The ASM_OUTPUT_CASE_END worker. */ 2620 2621void 2622cris_asm_output_case_end (FILE *stream, int num, rtx table) 2623{ 2624 /* Step back, over the label for the table, to the actual casejump and 2625 assert that we find only what's expected. */ 2626 rtx whole_jump_insn = prev_nonnote_nondebug_insn (table); 2627 gcc_assert (whole_jump_insn != NULL_RTX && LABEL_P (whole_jump_insn)); 2628 whole_jump_insn = prev_nonnote_nondebug_insn (whole_jump_insn); 2629 gcc_assert (whole_jump_insn != NULL_RTX 2630 && (JUMP_P (whole_jump_insn) 2631 || (TARGET_V32 && INSN_P (whole_jump_insn) 2632 && GET_CODE (PATTERN (whole_jump_insn)) == SEQUENCE))); 2633 /* Get the pattern of the casejump, so we can extract the default label. */ 2634 whole_jump_insn = PATTERN (whole_jump_insn); 2635 2636 if (TARGET_V32) 2637 { 2638 /* This can be a SEQUENCE, meaning the delay-slot of the jump is 2639 filled. We also output the offset word a little differently. */ 2640 rtx parallel_jump 2641 = (GET_CODE (whole_jump_insn) == SEQUENCE 2642 ? PATTERN (XVECEXP (whole_jump_insn, 0, 0)) : whole_jump_insn); 2643 2644 asm_fprintf (stream, 2645 "\t.word %LL%d-.%s\n", 2646 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP 2647 (parallel_jump, 0, 0), 2648 1), 2), 0)), 2649 (TARGET_PDEBUG ? "; default" : "")); 2650 return; 2651 } 2652 2653 asm_fprintf (stream, 2654 "\t.word %LL%d-%LL%d%s\n", 2655 CODE_LABEL_NUMBER (XEXP 2656 (XEXP 2657 (XEXP (XVECEXP (whole_jump_insn, 0, 0), 1), 2658 2), 0)), 2659 num, 2660 (TARGET_PDEBUG ? "; default" : "")); 2661} 2662 2663/* The TARGET_OPTION_OVERRIDE worker. 2664 As is the norm, this also parses -mfoo=bar type parameters. */ 2665 2666static void 2667cris_option_override (void) 2668{ 2669 if (cris_max_stackframe_str) 2670 { 2671 cris_max_stackframe = atoi (cris_max_stackframe_str); 2672 2673 /* Do some sanity checking. */ 2674 if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000) 2675 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d", 2676 cris_max_stackframe, 0x20000000); 2677 } 2678 2679 /* Let "-metrax4" and "-metrax100" change the cpu version. */ 2680 if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO) 2681 cris_cpu_version = CRIS_CPU_SVINTO; 2682 else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4) 2683 cris_cpu_version = CRIS_CPU_ETRAX4; 2684 2685 /* Parse -march=... and its synonym, the deprecated -mcpu=... */ 2686 if (cris_cpu_str) 2687 { 2688 cris_cpu_version 2689 = (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1); 2690 2691 if (strcmp ("etrax4", cris_cpu_str) == 0) 2692 cris_cpu_version = 3; 2693 2694 if (strcmp ("svinto", cris_cpu_str) == 0 2695 || strcmp ("etrax100", cris_cpu_str) == 0) 2696 cris_cpu_version = 8; 2697 2698 if (strcmp ("ng", cris_cpu_str) == 0 2699 || strcmp ("etrax100lx", cris_cpu_str) == 0) 2700 cris_cpu_version = 10; 2701 2702 if (cris_cpu_version < 0 || cris_cpu_version > 32) 2703 error ("unknown CRIS version specification in -march= or -mcpu= : %s", 2704 cris_cpu_str); 2705 2706 /* Set the target flags. */ 2707 if (cris_cpu_version >= CRIS_CPU_ETRAX4) 2708 target_flags |= MASK_ETRAX4_ADD; 2709 2710 /* If this is Svinto or higher, align for 32 bit accesses. */ 2711 if (cris_cpu_version >= CRIS_CPU_SVINTO) 2712 target_flags 2713 |= (MASK_SVINTO | MASK_ALIGN_BY_32 2714 | MASK_STACK_ALIGN | MASK_CONST_ALIGN 2715 | MASK_DATA_ALIGN); 2716 2717 /* Note that we do not add new flags when it can be completely 2718 described with a macro that uses -mcpu=X. So 2719 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */ 2720 } 2721 2722 if (cris_tune_str) 2723 { 2724 int cris_tune 2725 = (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1); 2726 2727 if (strcmp ("etrax4", cris_tune_str) == 0) 2728 cris_tune = 3; 2729 2730 if (strcmp ("svinto", cris_tune_str) == 0 2731 || strcmp ("etrax100", cris_tune_str) == 0) 2732 cris_tune = 8; 2733 2734 if (strcmp ("ng", cris_tune_str) == 0 2735 || strcmp ("etrax100lx", cris_tune_str) == 0) 2736 cris_tune = 10; 2737 2738 if (cris_tune < 0 || cris_tune > 32) 2739 error ("unknown CRIS cpu version specification in -mtune= : %s", 2740 cris_tune_str); 2741 2742 if (cris_tune >= CRIS_CPU_SVINTO) 2743 /* We have currently nothing more to tune than alignment for 2744 memory accesses. */ 2745 target_flags 2746 |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN 2747 | MASK_DATA_ALIGN | MASK_ALIGN_BY_32); 2748 } 2749 2750 if (cris_cpu_version >= CRIS_CPU_V32) 2751 target_flags &= ~(MASK_SIDE_EFFECT_PREFIXES|MASK_MUL_BUG); 2752 2753 if (flag_pic) 2754 { 2755 /* Use error rather than warning, so invalid use is easily 2756 detectable. Still change to the values we expect, to avoid 2757 further errors. */ 2758 if (! TARGET_LINUX) 2759 { 2760 error ("-fPIC and -fpic are not supported in this configuration"); 2761 flag_pic = 0; 2762 } 2763 2764 /* Turn off function CSE. We need to have the addresses reach the 2765 call expanders to get PLT-marked, as they could otherwise be 2766 compared against zero directly or indirectly. After visiting the 2767 call expanders they will then be cse:ed, as the call expanders 2768 force_reg the addresses, effectively forcing flag_no_function_cse 2769 to 0. */ 2770 flag_no_function_cse = 1; 2771 } 2772 2773 /* Set the per-function-data initializer. */ 2774 init_machine_status = cris_init_machine_status; 2775} 2776 2777/* The TARGET_ASM_OUTPUT_MI_THUNK worker. */ 2778 2779static void 2780cris_asm_output_mi_thunk (FILE *stream, 2781 tree thunkdecl ATTRIBUTE_UNUSED, 2782 HOST_WIDE_INT delta, 2783 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, 2784 tree funcdecl) 2785{ 2786 /* Make sure unwind info is emitted for the thunk if needed. */ 2787 final_start_function (emit_barrier (), stream, 1); 2788 2789 if (delta > 0) 2790 fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n", 2791 ADDITIVE_SIZE_MODIFIER (delta), delta, 2792 reg_names[CRIS_FIRST_ARG_REG]); 2793 else if (delta < 0) 2794 fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n", 2795 ADDITIVE_SIZE_MODIFIER (-delta), -delta, 2796 reg_names[CRIS_FIRST_ARG_REG]); 2797 2798 if (flag_pic) 2799 { 2800 const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0); 2801 2802 name = (* targetm.strip_name_encoding) (name); 2803 2804 if (TARGET_V32) 2805 { 2806 fprintf (stream, "\tba "); 2807 assemble_name (stream, name); 2808 fprintf (stream, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX); 2809 } 2810 else 2811 { 2812 fprintf (stream, "add.d "); 2813 assemble_name (stream, name); 2814 fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX); 2815 } 2816 } 2817 else 2818 { 2819 fprintf (stream, "jump "); 2820 assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0)); 2821 fprintf (stream, "\n"); 2822 2823 if (TARGET_V32) 2824 fprintf (stream, "\tnop\n"); 2825 } 2826 2827 final_end_function (); 2828} 2829 2830/* Boilerplate emitted at start of file. 2831 2832 NO_APP *only at file start* means faster assembly. It also means 2833 comments are not allowed. In some cases comments will be output 2834 for debugging purposes. Make sure they are allowed then. */ 2835static void 2836cris_file_start (void) 2837{ 2838 /* These expressions can vary at run time, so we cannot put 2839 them into TARGET_INITIALIZER. */ 2840 targetm.asm_file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name); 2841 2842 default_file_start (); 2843} 2844 2845/* Output that goes at the end of the file, similarly. */ 2846 2847static void 2848cris_file_end (void) 2849{ 2850 /* For CRIS, the default is to assume *no* executable stack, so output 2851 an executable-stack-note only when needed. */ 2852 if (TARGET_LINUX && trampolines_created) 2853 file_end_indicate_exec_stack (); 2854} 2855 2856/* Rename the function calls for integer multiply and divide. */ 2857static void 2858cris_init_libfuncs (void) 2859{ 2860 set_optab_libfunc (smul_optab, SImode, "__Mul"); 2861 set_optab_libfunc (sdiv_optab, SImode, "__Div"); 2862 set_optab_libfunc (udiv_optab, SImode, "__Udiv"); 2863 set_optab_libfunc (smod_optab, SImode, "__Mod"); 2864 set_optab_libfunc (umod_optab, SImode, "__Umod"); 2865 2866 /* Atomic data being unaligned is unfortunately a reality. 2867 Deal with it. */ 2868 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS) 2869 { 2870 set_optab_libfunc (sync_compare_and_swap_optab, SImode, 2871 "__cris_atcmpxchgr32"); 2872 set_optab_libfunc (sync_compare_and_swap_optab, HImode, 2873 "__cris_atcmpxchgr16"); 2874 } 2875} 2876 2877/* The INIT_EXPANDERS worker sets the per-function-data initializer and 2878 mark functions. */ 2879 2880void 2881cris_init_expanders (void) 2882{ 2883 /* Nothing here at the moment. */ 2884} 2885 2886/* Zero initialization is OK for all current fields. */ 2887 2888static struct machine_function * 2889cris_init_machine_status (void) 2890{ 2891 return ggc_cleared_alloc<machine_function> (); 2892} 2893 2894/* Split a 2 word move (DI or presumably DF) into component parts. 2895 Originally a copy of gen_split_move_double in m32r.c. */ 2896 2897rtx 2898cris_split_movdx (rtx *operands) 2899{ 2900 machine_mode mode = GET_MODE (operands[0]); 2901 rtx dest = operands[0]; 2902 rtx src = operands[1]; 2903 rtx val; 2904 2905 /* We used to have to handle (SUBREG (MEM)) here, but that should no 2906 longer happen; after reload there are no SUBREGs any more, and we're 2907 only called after reload. */ 2908 CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG); 2909 2910 start_sequence (); 2911 if (REG_P (dest)) 2912 { 2913 int dregno = REGNO (dest); 2914 2915 /* Reg-to-reg copy. */ 2916 if (REG_P (src)) 2917 { 2918 int sregno = REGNO (src); 2919 2920 int reverse = (dregno == sregno + 1); 2921 2922 /* We normally copy the low-numbered register first. However, if 2923 the first register operand 0 is the same as the second register of 2924 operand 1, we must copy in the opposite order. */ 2925 emit_insn (gen_rtx_SET (VOIDmode, 2926 operand_subword (dest, reverse, TRUE, mode), 2927 operand_subword (src, reverse, TRUE, mode))); 2928 2929 emit_insn (gen_rtx_SET (VOIDmode, 2930 operand_subword (dest, !reverse, TRUE, mode), 2931 operand_subword (src, !reverse, TRUE, mode))); 2932 } 2933 /* Constant-to-reg copy. */ 2934 else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE) 2935 { 2936 rtx words[2]; 2937 split_double (src, &words[0], &words[1]); 2938 emit_insn (gen_rtx_SET (VOIDmode, 2939 operand_subword (dest, 0, TRUE, mode), 2940 words[0])); 2941 2942 emit_insn (gen_rtx_SET (VOIDmode, 2943 operand_subword (dest, 1, TRUE, mode), 2944 words[1])); 2945 } 2946 /* Mem-to-reg copy. */ 2947 else if (MEM_P (src)) 2948 { 2949 /* If the high-address word is used in the address, we must load it 2950 last. Otherwise, load it first. */ 2951 rtx addr = XEXP (src, 0); 2952 int reverse = (refers_to_regno_p (dregno, addr) != 0); 2953 2954 /* The original code implies that we can't do 2955 move.x [rN+],rM move.x [rN],rM+1 2956 when rN is dead, because of REG_NOTES damage. That is 2957 consistent with what I've seen, so don't try it. 2958 2959 We have two different cases here; if the addr is POST_INC, 2960 just pass it through, otherwise add constants. */ 2961 2962 if (GET_CODE (addr) == POST_INC) 2963 { 2964 rtx mem; 2965 rtx insn; 2966 2967 /* Whenever we emit insns with post-incremented 2968 addresses ourselves, we must add a post-inc note 2969 manually. */ 2970 mem = change_address (src, SImode, addr); 2971 insn 2972 = gen_rtx_SET (VOIDmode, 2973 operand_subword (dest, 0, TRUE, mode), mem); 2974 insn = emit_insn (insn); 2975 if (GET_CODE (XEXP (mem, 0)) == POST_INC) 2976 REG_NOTES (insn) 2977 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), 2978 REG_NOTES (insn)); 2979 2980 mem = copy_rtx (mem); 2981 insn 2982 = gen_rtx_SET (VOIDmode, 2983 operand_subword (dest, 1, TRUE, mode), mem); 2984 insn = emit_insn (insn); 2985 if (GET_CODE (XEXP (mem, 0)) == POST_INC) 2986 REG_NOTES (insn) 2987 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), 2988 REG_NOTES (insn)); 2989 } 2990 else 2991 { 2992 /* Make sure we don't get any other addresses with 2993 embedded postincrements. They should be stopped in 2994 GO_IF_LEGITIMATE_ADDRESS, but we're here for your 2995 safety. */ 2996 if (side_effects_p (addr)) 2997 fatal_insn ("unexpected side-effects in address", addr); 2998 2999 emit_insn (gen_rtx_SET 3000 (VOIDmode, 3001 operand_subword (dest, reverse, TRUE, mode), 3002 change_address 3003 (src, SImode, 3004 plus_constant (Pmode, addr, 3005 reverse * UNITS_PER_WORD)))); 3006 emit_insn (gen_rtx_SET 3007 (VOIDmode, 3008 operand_subword (dest, ! reverse, TRUE, mode), 3009 change_address 3010 (src, SImode, 3011 plus_constant (Pmode, addr, 3012 (! reverse) * 3013 UNITS_PER_WORD)))); 3014 } 3015 } 3016 else 3017 internal_error ("unknown src"); 3018 } 3019 /* Reg-to-mem copy or clear mem. */ 3020 else if (MEM_P (dest) 3021 && (REG_P (src) 3022 || src == const0_rtx 3023 || src == CONST0_RTX (DFmode))) 3024 { 3025 rtx addr = XEXP (dest, 0); 3026 3027 if (GET_CODE (addr) == POST_INC) 3028 { 3029 rtx mem; 3030 rtx insn; 3031 3032 /* Whenever we emit insns with post-incremented addresses 3033 ourselves, we must add a post-inc note manually. */ 3034 mem = change_address (dest, SImode, addr); 3035 insn 3036 = gen_rtx_SET (VOIDmode, 3037 mem, operand_subword (src, 0, TRUE, mode)); 3038 insn = emit_insn (insn); 3039 if (GET_CODE (XEXP (mem, 0)) == POST_INC) 3040 REG_NOTES (insn) 3041 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), 3042 REG_NOTES (insn)); 3043 3044 mem = copy_rtx (mem); 3045 insn 3046 = gen_rtx_SET (VOIDmode, 3047 mem, 3048 operand_subword (src, 1, TRUE, mode)); 3049 insn = emit_insn (insn); 3050 if (GET_CODE (XEXP (mem, 0)) == POST_INC) 3051 REG_NOTES (insn) 3052 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), 3053 REG_NOTES (insn)); 3054 } 3055 else 3056 { 3057 /* Make sure we don't get any other addresses with embedded 3058 postincrements. They should be stopped in 3059 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */ 3060 if (side_effects_p (addr)) 3061 fatal_insn ("unexpected side-effects in address", addr); 3062 3063 emit_insn (gen_rtx_SET 3064 (VOIDmode, 3065 change_address (dest, SImode, addr), 3066 operand_subword (src, 0, TRUE, mode))); 3067 3068 emit_insn (gen_rtx_SET 3069 (VOIDmode, 3070 change_address (dest, SImode, 3071 plus_constant (Pmode, addr, 3072 UNITS_PER_WORD)), 3073 operand_subword (src, 1, TRUE, mode))); 3074 } 3075 } 3076 3077 else 3078 internal_error ("unknown dest"); 3079 3080 val = get_insns (); 3081 end_sequence (); 3082 return val; 3083} 3084 3085/* The expander for the prologue pattern name. */ 3086 3087void 3088cris_expand_prologue (void) 3089{ 3090 int regno; 3091 int size = get_frame_size (); 3092 /* Shorten the used name for readability. */ 3093 int cfoa_size = crtl->outgoing_args_size; 3094 int last_movem_reg = -1; 3095 int framesize = 0; 3096 rtx mem, insn; 3097 int return_address_on_stack = cris_return_address_on_stack (); 3098 int got_really_used = false; 3099 int n_movem_regs = 0; 3100 int pretend = crtl->args.pretend_args_size; 3101 3102 /* Don't do anything if no prologues or epilogues are wanted. */ 3103 if (!TARGET_PROLOGUE_EPILOGUE) 3104 return; 3105 3106 CRIS_ASSERT (size >= 0); 3107 3108 if (crtl->uses_pic_offset_table) 3109 { 3110 /* A reference may have been optimized out (like the abort () in 3111 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that 3112 it's still used. */ 3113 push_topmost_sequence (); 3114 got_really_used 3115 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); 3116 pop_topmost_sequence (); 3117 } 3118 3119 /* Align the size to what's best for the CPU model. */ 3120 if (TARGET_STACK_ALIGN) 3121 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1; 3122 3123 if (pretend) 3124 { 3125 /* See also cris_setup_incoming_varargs where 3126 cfun->machine->stdarg_regs is set. There are other setters of 3127 crtl->args.pretend_args_size than stdarg handling, like 3128 for an argument passed with parts in R13 and stack. We must 3129 not store R13 into the pretend-area for that case, as GCC does 3130 that itself. "Our" store would be marked as redundant and GCC 3131 will attempt to remove it, which will then be flagged as an 3132 internal error; trying to remove a frame-related insn. */ 3133 int stdarg_regs = cfun->machine->stdarg_regs; 3134 3135 framesize += pretend; 3136 3137 for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1; 3138 stdarg_regs > 0; 3139 regno--, pretend -= 4, stdarg_regs--) 3140 { 3141 insn = emit_insn (gen_rtx_SET (VOIDmode, 3142 stack_pointer_rtx, 3143 plus_constant (Pmode, 3144 stack_pointer_rtx, 3145 -4))); 3146 /* FIXME: When dwarf2 frame output and unless asynchronous 3147 exceptions, make dwarf2 bundle together all stack 3148 adjustments like it does for registers between stack 3149 adjustments. */ 3150 RTX_FRAME_RELATED_P (insn) = 1; 3151 3152 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3153 set_mem_alias_set (mem, get_varargs_alias_set ()); 3154 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno)); 3155 3156 /* Note the absence of RTX_FRAME_RELATED_P on the above insn: 3157 the value isn't restored, so we don't want to tell dwarf2 3158 that it's been stored to stack, else EH handling info would 3159 get confused. */ 3160 } 3161 3162 /* For other setters of crtl->args.pretend_args_size, we 3163 just adjust the stack by leaving the remaining size in 3164 "pretend", handled below. */ 3165 } 3166 3167 /* Save SRP if not a leaf function. */ 3168 if (return_address_on_stack) 3169 { 3170 insn = emit_insn (gen_rtx_SET (VOIDmode, 3171 stack_pointer_rtx, 3172 plus_constant (Pmode, stack_pointer_rtx, 3173 -4 - pretend))); 3174 pretend = 0; 3175 RTX_FRAME_RELATED_P (insn) = 1; 3176 3177 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3178 set_mem_alias_set (mem, get_frame_alias_set ()); 3179 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM)); 3180 RTX_FRAME_RELATED_P (insn) = 1; 3181 framesize += 4; 3182 } 3183 3184 /* Set up the frame pointer, if needed. */ 3185 if (frame_pointer_needed) 3186 { 3187 insn = emit_insn (gen_rtx_SET (VOIDmode, 3188 stack_pointer_rtx, 3189 plus_constant (Pmode, stack_pointer_rtx, 3190 -4 - pretend))); 3191 pretend = 0; 3192 RTX_FRAME_RELATED_P (insn) = 1; 3193 3194 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3195 set_mem_alias_set (mem, get_frame_alias_set ()); 3196 insn = emit_move_insn (mem, frame_pointer_rtx); 3197 RTX_FRAME_RELATED_P (insn) = 1; 3198 3199 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); 3200 RTX_FRAME_RELATED_P (insn) = 1; 3201 3202 framesize += 4; 3203 } 3204 3205 /* Between frame-pointer and saved registers lie the area for local 3206 variables. If we get here with "pretended" size remaining, count 3207 it into the general stack size. */ 3208 size += pretend; 3209 3210 /* Get a contiguous sequence of registers, starting with R0, that need 3211 to be saved. */ 3212 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 3213 { 3214 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 3215 { 3216 n_movem_regs++; 3217 3218 /* Check if movem may be used for registers so far. */ 3219 if (regno == last_movem_reg + 1) 3220 /* Yes, update next expected register. */ 3221 last_movem_reg = regno; 3222 else 3223 { 3224 /* We cannot use movem for all registers. We have to flush 3225 any movem:ed registers we got so far. */ 3226 if (last_movem_reg != -1) 3227 { 3228 int n_saved 3229 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1; 3230 3231 /* It is a win to use a side-effect assignment for 3232 64 <= size <= 128. But side-effect on movem was 3233 not usable for CRIS v0..3. Also only do it if 3234 side-effects insns are allowed. */ 3235 if ((last_movem_reg + 1) * 4 + size >= 64 3236 && (last_movem_reg + 1) * 4 + size <= 128 3237 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1) 3238 && TARGET_SIDE_EFFECT_PREFIXES) 3239 { 3240 mem 3241 = gen_rtx_MEM (SImode, 3242 plus_constant (Pmode, stack_pointer_rtx, 3243 -(n_saved * 4 + size))); 3244 set_mem_alias_set (mem, get_frame_alias_set ()); 3245 insn 3246 = cris_emit_movem_store (mem, GEN_INT (n_saved), 3247 -(n_saved * 4 + size), 3248 true); 3249 } 3250 else 3251 { 3252 insn 3253 = gen_rtx_SET (VOIDmode, 3254 stack_pointer_rtx, 3255 plus_constant (Pmode, stack_pointer_rtx, 3256 -(n_saved * 4 + size))); 3257 insn = emit_insn (insn); 3258 RTX_FRAME_RELATED_P (insn) = 1; 3259 3260 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3261 set_mem_alias_set (mem, get_frame_alias_set ()); 3262 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 3263 0, true); 3264 } 3265 3266 framesize += n_saved * 4 + size; 3267 last_movem_reg = -1; 3268 size = 0; 3269 } 3270 3271 insn = emit_insn (gen_rtx_SET (VOIDmode, 3272 stack_pointer_rtx, 3273 plus_constant (Pmode, 3274 stack_pointer_rtx, 3275 -4 - size))); 3276 RTX_FRAME_RELATED_P (insn) = 1; 3277 3278 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3279 set_mem_alias_set (mem, get_frame_alias_set ()); 3280 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno)); 3281 RTX_FRAME_RELATED_P (insn) = 1; 3282 3283 framesize += 4 + size; 3284 size = 0; 3285 } 3286 } 3287 } 3288 3289 /* Check after, if we could movem all registers. This is the normal case. */ 3290 if (last_movem_reg != -1) 3291 { 3292 int n_saved 3293 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1; 3294 3295 /* Side-effect on movem was not usable for CRIS v0..3. Also only 3296 do it if side-effects insns are allowed. */ 3297 if ((last_movem_reg + 1) * 4 + size >= 64 3298 && (last_movem_reg + 1) * 4 + size <= 128 3299 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1) 3300 && TARGET_SIDE_EFFECT_PREFIXES) 3301 { 3302 mem 3303 = gen_rtx_MEM (SImode, 3304 plus_constant (Pmode, stack_pointer_rtx, 3305 -(n_saved * 4 + size))); 3306 set_mem_alias_set (mem, get_frame_alias_set ()); 3307 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 3308 -(n_saved * 4 + size), true); 3309 } 3310 else 3311 { 3312 insn 3313 = gen_rtx_SET (VOIDmode, 3314 stack_pointer_rtx, 3315 plus_constant (Pmode, stack_pointer_rtx, 3316 -(n_saved * 4 + size))); 3317 insn = emit_insn (insn); 3318 RTX_FRAME_RELATED_P (insn) = 1; 3319 3320 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3321 set_mem_alias_set (mem, get_frame_alias_set ()); 3322 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true); 3323 } 3324 3325 framesize += n_saved * 4 + size; 3326 /* We have to put outgoing argument space after regs. */ 3327 if (cfoa_size) 3328 { 3329 insn = emit_insn (gen_rtx_SET (VOIDmode, 3330 stack_pointer_rtx, 3331 plus_constant (Pmode, 3332 stack_pointer_rtx, 3333 -cfoa_size))); 3334 RTX_FRAME_RELATED_P (insn) = 1; 3335 framesize += cfoa_size; 3336 } 3337 } 3338 else if ((size + cfoa_size) > 0) 3339 { 3340 insn = emit_insn (gen_rtx_SET (VOIDmode, 3341 stack_pointer_rtx, 3342 plus_constant (Pmode, 3343 stack_pointer_rtx, 3344 -(cfoa_size + size)))); 3345 RTX_FRAME_RELATED_P (insn) = 1; 3346 framesize += size + cfoa_size; 3347 } 3348 3349 /* Set up the PIC register, if it is used. */ 3350 if (got_really_used) 3351 { 3352 rtx got 3353 = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT); 3354 emit_move_insn (pic_offset_table_rtx, got); 3355 3356 /* FIXME: This is a cover-up for flow2 messing up; it doesn't 3357 follow exceptional paths and tries to delete the GOT load as 3358 unused, if it isn't used on the non-exceptional paths. Other 3359 ports have similar or other cover-ups, or plain bugs marking 3360 the GOT register load as maybe-dead. To see this, remove the 3361 line below and try libsupc++/vec.cc or a trivial 3362 "static void y (); void x () {try {y ();} catch (...) {}}". */ 3363 emit_use (pic_offset_table_rtx); 3364 } 3365 3366 if (cris_max_stackframe && framesize > cris_max_stackframe) 3367 warning (0, "stackframe too big: %d bytes", framesize); 3368} 3369 3370/* The expander for the epilogue pattern. */ 3371 3372void 3373cris_expand_epilogue (void) 3374{ 3375 int regno; 3376 int size = get_frame_size (); 3377 int last_movem_reg = -1; 3378 int argspace_offset = crtl->outgoing_args_size; 3379 int pretend = crtl->args.pretend_args_size; 3380 rtx mem; 3381 bool return_address_on_stack = cris_return_address_on_stack (); 3382 /* A reference may have been optimized out 3383 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1) 3384 so check that it's still used. */ 3385 int got_really_used = false; 3386 int n_movem_regs = 0; 3387 3388 if (!TARGET_PROLOGUE_EPILOGUE) 3389 return; 3390 3391 if (crtl->uses_pic_offset_table) 3392 { 3393 /* A reference may have been optimized out (like the abort () in 3394 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that 3395 it's still used. */ 3396 push_topmost_sequence (); 3397 got_really_used 3398 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); 3399 pop_topmost_sequence (); 3400 } 3401 3402 /* Align byte count of stack frame. */ 3403 if (TARGET_STACK_ALIGN) 3404 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1; 3405 3406 /* Check how many saved regs we can movem. They start at r0 and must 3407 be contiguous. */ 3408 for (regno = 0; 3409 regno < FIRST_PSEUDO_REGISTER; 3410 regno++) 3411 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 3412 { 3413 n_movem_regs++; 3414 3415 if (regno == last_movem_reg + 1) 3416 last_movem_reg = regno; 3417 else 3418 break; 3419 } 3420 3421 /* If there was only one register that really needed to be saved 3422 through movem, don't use movem. */ 3423 if (n_movem_regs == 1) 3424 last_movem_reg = -1; 3425 3426 /* Now emit "normal" move insns for all regs higher than the movem 3427 regs. */ 3428 for (regno = FIRST_PSEUDO_REGISTER - 1; 3429 regno > last_movem_reg; 3430 regno--) 3431 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 3432 { 3433 rtx insn; 3434 3435 if (argspace_offset) 3436 { 3437 /* There is an area for outgoing parameters located before 3438 the saved registers. We have to adjust for that. */ 3439 emit_insn (gen_rtx_SET (VOIDmode, 3440 stack_pointer_rtx, 3441 plus_constant (Pmode, stack_pointer_rtx, 3442 argspace_offset))); 3443 /* Make sure we only do this once. */ 3444 argspace_offset = 0; 3445 } 3446 3447 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, 3448 stack_pointer_rtx)); 3449 set_mem_alias_set (mem, get_frame_alias_set ()); 3450 insn = emit_move_insn (gen_rtx_raw_REG (SImode, regno), mem); 3451 3452 /* Whenever we emit insns with post-incremented addresses 3453 ourselves, we must add a post-inc note manually. */ 3454 REG_NOTES (insn) 3455 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3456 } 3457 3458 /* If we have any movem-restore, do it now. */ 3459 if (last_movem_reg != -1) 3460 { 3461 rtx insn; 3462 3463 if (argspace_offset) 3464 { 3465 emit_insn (gen_rtx_SET (VOIDmode, 3466 stack_pointer_rtx, 3467 plus_constant (Pmode, stack_pointer_rtx, 3468 argspace_offset))); 3469 argspace_offset = 0; 3470 } 3471 3472 mem = gen_rtx_MEM (SImode, 3473 gen_rtx_POST_INC (SImode, stack_pointer_rtx)); 3474 set_mem_alias_set (mem, get_frame_alias_set ()); 3475 insn 3476 = emit_insn (cris_gen_movem_load (mem, 3477 GEN_INT (last_movem_reg + 1), 0)); 3478 /* Whenever we emit insns with post-incremented addresses 3479 ourselves, we must add a post-inc note manually. */ 3480 if (side_effects_p (PATTERN (insn))) 3481 REG_NOTES (insn) 3482 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3483 } 3484 3485 /* If we don't clobber all of the allocated stack area (we've already 3486 deallocated saved registers), GCC might want to schedule loads from 3487 the stack to *after* the stack-pointer restore, which introduces an 3488 interrupt race condition. This happened for the initial-value 3489 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of 3490 other failure for that test). It also happened for the stack slot 3491 for the return value in (one version of) 3492 linux/fs/dcache.c:__d_lookup, at least with "-O2 3493 -fno-omit-frame-pointer". */ 3494 3495 /* Restore frame pointer if necessary. */ 3496 if (frame_pointer_needed) 3497 { 3498 rtx insn; 3499 3500 emit_insn (gen_cris_frame_deallocated_barrier ()); 3501 3502 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); 3503 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, 3504 stack_pointer_rtx)); 3505 set_mem_alias_set (mem, get_frame_alias_set ()); 3506 insn = emit_move_insn (frame_pointer_rtx, mem); 3507 3508 /* Whenever we emit insns with post-incremented addresses 3509 ourselves, we must add a post-inc note manually. */ 3510 REG_NOTES (insn) 3511 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3512 } 3513 else if ((size + argspace_offset) != 0) 3514 { 3515 emit_insn (gen_cris_frame_deallocated_barrier ()); 3516 3517 /* If there was no frame-pointer to restore sp from, we must 3518 explicitly deallocate local variables. */ 3519 3520 /* Handle space for outgoing parameters that hasn't been handled 3521 yet. */ 3522 size += argspace_offset; 3523 3524 emit_insn (gen_rtx_SET (VOIDmode, 3525 stack_pointer_rtx, 3526 plus_constant (Pmode, stack_pointer_rtx, size))); 3527 } 3528 3529 /* If this function has no pushed register parameters 3530 (stdargs/varargs), and if it is not a leaf function, then we have 3531 the return address on the stack. */ 3532 if (return_address_on_stack && pretend == 0) 3533 { 3534 if (TARGET_V32 || crtl->calls_eh_return) 3535 { 3536 rtx mem; 3537 rtx insn; 3538 rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM); 3539 mem = gen_rtx_MEM (SImode, 3540 gen_rtx_POST_INC (SImode, 3541 stack_pointer_rtx)); 3542 set_mem_alias_set (mem, get_frame_alias_set ()); 3543 insn = emit_move_insn (srpreg, mem); 3544 3545 /* Whenever we emit insns with post-incremented addresses 3546 ourselves, we must add a post-inc note manually. */ 3547 REG_NOTES (insn) 3548 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3549 3550 if (crtl->calls_eh_return) 3551 emit_insn (gen_addsi3 (stack_pointer_rtx, 3552 stack_pointer_rtx, 3553 gen_rtx_raw_REG (SImode, 3554 CRIS_STACKADJ_REG))); 3555 cris_expand_return (false); 3556 } 3557 else 3558 cris_expand_return (true); 3559 3560 return; 3561 } 3562 3563 /* If we pushed some register parameters, then adjust the stack for 3564 them. */ 3565 if (pretend != 0) 3566 { 3567 /* If SRP is stored on the way, we need to restore it first. */ 3568 if (return_address_on_stack) 3569 { 3570 rtx mem; 3571 rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM); 3572 rtx insn; 3573 3574 mem = gen_rtx_MEM (SImode, 3575 gen_rtx_POST_INC (SImode, 3576 stack_pointer_rtx)); 3577 set_mem_alias_set (mem, get_frame_alias_set ()); 3578 insn = emit_move_insn (srpreg, mem); 3579 3580 /* Whenever we emit insns with post-incremented addresses 3581 ourselves, we must add a post-inc note manually. */ 3582 REG_NOTES (insn) 3583 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3584 } 3585 3586 emit_insn (gen_rtx_SET (VOIDmode, 3587 stack_pointer_rtx, 3588 plus_constant (Pmode, stack_pointer_rtx, 3589 pretend))); 3590 } 3591 3592 /* Perform the "physical" unwinding that the EH machinery calculated. */ 3593 if (crtl->calls_eh_return) 3594 emit_insn (gen_addsi3 (stack_pointer_rtx, 3595 stack_pointer_rtx, 3596 gen_rtx_raw_REG (SImode, 3597 CRIS_STACKADJ_REG))); 3598 cris_expand_return (false); 3599} 3600 3601/* Worker function for generating movem from mem for load_multiple. */ 3602 3603rtx 3604cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix) 3605{ 3606 int nregs = INTVAL (nregs_rtx); 3607 rtvec vec; 3608 int eltno = 1; 3609 int i; 3610 rtx srcreg = XEXP (src, 0); 3611 unsigned int regno = nregs - 1; 3612 int regno_inc = -1; 3613 3614 if (TARGET_V32) 3615 { 3616 regno = 0; 3617 regno_inc = 1; 3618 } 3619 3620 if (GET_CODE (srcreg) == POST_INC) 3621 srcreg = XEXP (srcreg, 0); 3622 3623 CRIS_ASSERT (REG_P (srcreg)); 3624 3625 /* Don't use movem for just one insn. The insns are equivalent except 3626 for the pipeline hazard (on v32); movem does not forward the loaded 3627 registers so there's a three cycles penalty for their use. */ 3628 if (nregs == 1) 3629 return gen_movsi (gen_rtx_REG (SImode, 0), src); 3630 3631 vec = rtvec_alloc (nprefix + nregs 3632 + (GET_CODE (XEXP (src, 0)) == POST_INC)); 3633 3634 if (GET_CODE (XEXP (src, 0)) == POST_INC) 3635 { 3636 RTVEC_ELT (vec, nprefix + 1) 3637 = gen_rtx_SET (VOIDmode, srcreg, 3638 plus_constant (Pmode, srcreg, nregs * 4)); 3639 eltno++; 3640 } 3641 3642 src = replace_equiv_address (src, srcreg); 3643 RTVEC_ELT (vec, nprefix) 3644 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), src); 3645 regno += regno_inc; 3646 3647 for (i = 1; i < nregs; i++, eltno++) 3648 { 3649 RTVEC_ELT (vec, nprefix + eltno) 3650 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), 3651 adjust_address_nv (src, SImode, i * 4)); 3652 regno += regno_inc; 3653 } 3654 3655 return gen_rtx_PARALLEL (VOIDmode, vec); 3656} 3657 3658/* Worker function for generating movem to mem. If FRAME_RELATED, notes 3659 are added that the dwarf2 machinery understands. */ 3660 3661rtx 3662cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment, 3663 bool frame_related) 3664{ 3665 int nregs = INTVAL (nregs_rtx); 3666 rtvec vec; 3667 int eltno = 1; 3668 int i; 3669 rtx insn; 3670 rtx destreg = XEXP (dest, 0); 3671 unsigned int regno = nregs - 1; 3672 int regno_inc = -1; 3673 3674 if (TARGET_V32) 3675 { 3676 regno = 0; 3677 regno_inc = 1; 3678 } 3679 3680 if (GET_CODE (destreg) == POST_INC) 3681 increment += nregs * 4; 3682 3683 if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS) 3684 destreg = XEXP (destreg, 0); 3685 3686 CRIS_ASSERT (REG_P (destreg)); 3687 3688 /* Don't use movem for just one insn. The insns are equivalent except 3689 for the pipeline hazard (on v32); movem does not forward the loaded 3690 registers so there's a three cycles penalty for use. */ 3691 if (nregs == 1) 3692 { 3693 rtx mov = gen_rtx_SET (VOIDmode, dest, gen_rtx_REG (SImode, 0)); 3694 3695 if (increment == 0) 3696 { 3697 insn = emit_insn (mov); 3698 if (frame_related) 3699 RTX_FRAME_RELATED_P (insn) = 1; 3700 return insn; 3701 } 3702 3703 /* If there was a request for a side-effect, create the ordinary 3704 parallel. */ 3705 vec = rtvec_alloc (2); 3706 3707 RTVEC_ELT (vec, 0) = mov; 3708 RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, destreg, 3709 plus_constant (Pmode, destreg, 3710 increment)); 3711 if (frame_related) 3712 { 3713 RTX_FRAME_RELATED_P (mov) = 1; 3714 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1; 3715 } 3716 } 3717 else 3718 { 3719 vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0)); 3720 RTVEC_ELT (vec, 0) 3721 = gen_rtx_SET (VOIDmode, 3722 replace_equiv_address (dest, 3723 plus_constant (Pmode, destreg, 3724 increment)), 3725 gen_rtx_REG (SImode, regno)); 3726 regno += regno_inc; 3727 3728 /* The dwarf2 info wants this mark on each component in a parallel 3729 that's part of the prologue (though it's optional on the first 3730 component). */ 3731 if (frame_related) 3732 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1; 3733 3734 if (increment != 0) 3735 { 3736 RTVEC_ELT (vec, 1) 3737 = gen_rtx_SET (VOIDmode, destreg, 3738 plus_constant (Pmode, destreg, 3739 increment != 0 3740 ? increment : nregs * 4)); 3741 eltno++; 3742 3743 if (frame_related) 3744 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1; 3745 3746 /* Don't call adjust_address_nv on a post-incremented address if 3747 we can help it. */ 3748 if (GET_CODE (XEXP (dest, 0)) == POST_INC) 3749 dest = replace_equiv_address (dest, destreg); 3750 } 3751 3752 for (i = 1; i < nregs; i++, eltno++) 3753 { 3754 RTVEC_ELT (vec, eltno) 3755 = gen_rtx_SET (VOIDmode, adjust_address_nv (dest, SImode, i * 4), 3756 gen_rtx_REG (SImode, regno)); 3757 if (frame_related) 3758 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1; 3759 regno += regno_inc; 3760 } 3761 } 3762 3763 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec)); 3764 3765 /* Because dwarf2out.c handles the insns in a parallel as a sequence, 3766 we need to keep the stack adjustment separate, after the 3767 MEM-setters. Else the stack-adjustment in the second component of 3768 the parallel would be mishandled; the offsets for the SETs that 3769 follow it would be wrong. We prepare for this by adding a 3770 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE 3771 followed by the increment. Note that we have FRAME_RELATED_P on 3772 all the SETs, including the original stack adjustment SET in the 3773 parallel. */ 3774 if (frame_related) 3775 { 3776 if (increment != 0) 3777 { 3778 rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1)); 3779 XVECEXP (seq, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn), 0, 0)); 3780 for (i = 1; i < nregs; i++) 3781 XVECEXP (seq, 0, i) 3782 = copy_rtx (XVECEXP (PATTERN (insn), 0, i + 1)); 3783 XVECEXP (seq, 0, nregs) = copy_rtx (XVECEXP (PATTERN (insn), 0, 1)); 3784 add_reg_note (insn, REG_FRAME_RELATED_EXPR, seq); 3785 } 3786 3787 RTX_FRAME_RELATED_P (insn) = 1; 3788 } 3789 3790 return insn; 3791} 3792 3793/* Worker function for expanding the address for PIC function calls. */ 3794 3795void 3796cris_expand_pic_call_address (rtx *opp, rtx *markerp) 3797{ 3798 rtx op = *opp; 3799 3800 gcc_assert (flag_pic && MEM_P (op)); 3801 op = XEXP (op, 0); 3802 3803 /* It might be that code can be generated that jumps to 0 (or to a 3804 specific address). Don't die on that. (There is a 3805 testcase.) */ 3806 if (CONSTANT_P (op) && !CONST_INT_P (op)) 3807 { 3808 enum cris_symbol_type t = cris_symbol_type_of (op); 3809 3810 CRIS_ASSERT (can_create_pseudo_p ()); 3811 3812 /* For local symbols (non-PLT), just get the plain symbol 3813 reference into a register. For symbols that can be PLT, make 3814 them PLT. */ 3815 if (t == cris_rel_symbol) 3816 { 3817 /* For v32, we're fine as-is; just PICify the symbol. Forcing 3818 into a register caused performance regression for 3.2.1, 3819 observable in __floatdidf and elsewhere in libgcc. */ 3820 if (TARGET_V32) 3821 { 3822 rtx sym = GET_CODE (op) != CONST ? op : get_related_value (op); 3823 HOST_WIDE_INT offs = get_integer_term (op); 3824 3825 /* We can't get calls to sym+N, N integer, can we? */ 3826 gcc_assert (offs == 0); 3827 3828 op = gen_rtx_CONST (Pmode, 3829 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 3830 CRIS_UNSPEC_PCREL)); 3831 } 3832 else 3833 op = force_reg (Pmode, op); 3834 3835 /* A local call. */ 3836 *markerp = const0_rtx; 3837 } 3838 else if (t == cris_got_symbol) 3839 { 3840 if (TARGET_AVOID_GOTPLT) 3841 { 3842 /* Change a "jsr sym" into (allocate register rM, rO) 3843 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT_GOTREL)),rM" 3844 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and 3845 "jsr (const (unspec [sym] CRIS_UNSPEC_PLT_PCREL))" 3846 for v32. */ 3847 rtx tem, rm, ro; 3848 3849 crtl->uses_pic_offset_table = 1; 3850 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), 3851 TARGET_V32 3852 ? CRIS_UNSPEC_PLT_PCREL 3853 : CRIS_UNSPEC_PLT_GOTREL); 3854 tem = gen_rtx_CONST (Pmode, tem); 3855 if (TARGET_V32) 3856 op = tem; 3857 else 3858 { 3859 rm = gen_reg_rtx (Pmode); 3860 emit_move_insn (rm, tem); 3861 ro = gen_reg_rtx (Pmode); 3862 if (expand_binop (Pmode, add_optab, rm, 3863 pic_offset_table_rtx, 3864 ro, 0, OPTAB_LIB_WIDEN) != ro) 3865 internal_error ("expand_binop failed in movsi got"); 3866 op = ro; 3867 } 3868 } 3869 else 3870 { 3871 /* Change a "jsr sym" into (allocate register rM, rO) 3872 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM" 3873 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access 3874 marked as not trapping and not aliasing. No "move.d 3875 [rO],rP" as that would invite to re-use of a value 3876 that should not be reused. FIXME: Need a peephole2 3877 for cases when this is cse:d from the call, to change 3878 back to just get the PLT entry address, so we don't 3879 resolve the same symbol over and over (the memory 3880 access of the PLTGOT isn't constant). */ 3881 rtx tem, mem, rm, ro; 3882 3883 gcc_assert (can_create_pseudo_p ()); 3884 crtl->uses_pic_offset_table = 1; 3885 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), 3886 CRIS_UNSPEC_PLTGOTREAD); 3887 rm = gen_reg_rtx (Pmode); 3888 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem)); 3889 ro = gen_reg_rtx (Pmode); 3890 if (expand_binop (Pmode, add_optab, rm, 3891 pic_offset_table_rtx, 3892 ro, 0, OPTAB_LIB_WIDEN) != ro) 3893 internal_error ("expand_binop failed in movsi got"); 3894 mem = gen_rtx_MEM (Pmode, ro); 3895 3896 /* This MEM doesn't alias anything. Whether it aliases 3897 other same symbols is unimportant. */ 3898 set_mem_alias_set (mem, new_alias_set ()); 3899 MEM_NOTRAP_P (mem) = 1; 3900 op = mem; 3901 } 3902 3903 /* We need to prepare this call to go through the PLT; we 3904 need to make GOT available. */ 3905 *markerp = pic_offset_table_rtx; 3906 } 3907 else 3908 /* Can't possibly get anything else for a function-call, right? */ 3909 fatal_insn ("unidentifiable call op", op); 3910 3911 /* If the validizing variant is called, it will try to validize 3912 the address as a valid any-operand constant, but as it's only 3913 valid for calls and moves, it will fail and always be forced 3914 into a register. */ 3915 *opp = replace_equiv_address_nv (*opp, op); 3916 } 3917 else 3918 /* Can't tell what locality a call to a non-constant address has; 3919 better make the GOT register alive at it. 3920 FIXME: Can we see whether the register has known constant 3921 contents? */ 3922 *markerp = pic_offset_table_rtx; 3923} 3924 3925/* Make sure operands are in the right order for an addsi3 insn as 3926 generated by a define_split. Nothing but REG_P as the first 3927 operand is recognized by addsi3 after reload. OPERANDS contains 3928 the operands, with the first at OPERANDS[N] and the second at 3929 OPERANDS[N+1]. */ 3930 3931void 3932cris_order_for_addsi3 (rtx *operands, int n) 3933{ 3934 if (!REG_P (operands[n])) 3935 { 3936 rtx tem = operands[n]; 3937 operands[n] = operands[n + 1]; 3938 operands[n + 1] = tem; 3939 } 3940} 3941 3942/* Use from within code, from e.g. PRINT_OPERAND and 3943 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit 3944 different things depending on whether code operand or constant is 3945 emitted. */ 3946 3947static void 3948cris_output_addr_const (FILE *file, rtx x) 3949{ 3950 in_code++; 3951 output_addr_const (file, x); 3952 in_code--; 3953} 3954 3955/* Worker function for ASM_OUTPUT_SYMBOL_REF. */ 3956 3957void 3958cris_asm_output_symbol_ref (FILE *file, rtx x) 3959{ 3960 gcc_assert (GET_CODE (x) == SYMBOL_REF); 3961 3962 if (flag_pic && in_code > 0) 3963 { 3964 const char *origstr = XSTR (x, 0); 3965 const char *str; 3966 str = (* targetm.strip_name_encoding) (origstr); 3967 assemble_name (file, str); 3968 3969 /* Sanity check. */ 3970 if (!TARGET_V32 && !crtl->uses_pic_offset_table) 3971 output_operand_lossage ("PIC register isn't set up"); 3972 } 3973 else 3974 assemble_name (file, XSTR (x, 0)); 3975} 3976 3977/* Worker function for ASM_OUTPUT_LABEL_REF. */ 3978 3979void 3980cris_asm_output_label_ref (FILE *file, char *buf) 3981{ 3982 if (flag_pic && in_code > 0) 3983 { 3984 assemble_name (file, buf); 3985 3986 /* Sanity check. */ 3987 if (!TARGET_V32 && !crtl->uses_pic_offset_table) 3988 internal_error ("emitting PIC operand, but PIC register " 3989 "isn%'t set up"); 3990 } 3991 else 3992 assemble_name (file, buf); 3993} 3994 3995/* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */ 3996 3997static bool 3998cris_output_addr_const_extra (FILE *file, rtx xconst) 3999{ 4000 switch (GET_CODE (xconst)) 4001 { 4002 rtx x; 4003 4004 case UNSPEC: 4005 x = XVECEXP (xconst, 0, 0); 4006 CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF 4007 || GET_CODE (x) == LABEL_REF 4008 || GET_CODE (x) == CONST); 4009 output_addr_const (file, x); 4010 switch (XINT (xconst, 1)) 4011 { 4012 case CRIS_UNSPEC_PCREL: 4013 /* We only get this with -fpic/PIC to tell it apart from an 4014 invalid symbol. We can't tell here, but it should only 4015 be the operand of a call or movsi. */ 4016 gcc_assert (TARGET_V32 && flag_pic); 4017 break; 4018 4019 case CRIS_UNSPEC_PLT_PCREL: 4020 gcc_assert (TARGET_V32); 4021 fprintf (file, ":PLT"); 4022 break; 4023 4024 case CRIS_UNSPEC_PLT_GOTREL: 4025 gcc_assert (!TARGET_V32); 4026 fprintf (file, ":PLTG"); 4027 break; 4028 4029 case CRIS_UNSPEC_GOTREL: 4030 gcc_assert (!TARGET_V32); 4031 fprintf (file, ":GOTOFF"); 4032 break; 4033 4034 case CRIS_UNSPEC_GOTREAD: 4035 if (flag_pic == 1) 4036 fprintf (file, ":GOT16"); 4037 else 4038 fprintf (file, ":GOT"); 4039 break; 4040 4041 case CRIS_UNSPEC_PLTGOTREAD: 4042 if (flag_pic == 1) 4043 fprintf (file, CRIS_GOTPLT_SUFFIX "16"); 4044 else 4045 fprintf (file, CRIS_GOTPLT_SUFFIX); 4046 break; 4047 4048 default: 4049 gcc_unreachable (); 4050 } 4051 return true; 4052 4053 default: 4054 return false; 4055 } 4056} 4057 4058/* Worker function for TARGET_STRUCT_VALUE_RTX. */ 4059 4060static rtx 4061cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, 4062 int incoming ATTRIBUTE_UNUSED) 4063{ 4064 return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM); 4065} 4066 4067/* Worker function for TARGET_SETUP_INCOMING_VARARGS. */ 4068 4069static void 4070cris_setup_incoming_varargs (cumulative_args_t ca_v, 4071 machine_mode mode ATTRIBUTE_UNUSED, 4072 tree type ATTRIBUTE_UNUSED, 4073 int *pretend_arg_size, 4074 int second_time) 4075{ 4076 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); 4077 4078 if (ca->regs < CRIS_MAX_ARGS_IN_REGS) 4079 { 4080 int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs; 4081 cfun->machine->stdarg_regs = stdarg_regs; 4082 *pretend_arg_size = stdarg_regs * 4; 4083 } 4084 4085 if (TARGET_PDEBUG) 4086 fprintf (asm_out_file, 4087 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n", 4088 ca->regs, *pretend_arg_size, second_time); 4089} 4090 4091/* Return true if TYPE must be passed by invisible reference. 4092 For cris, we pass <= 8 bytes by value, others by reference. */ 4093 4094static bool 4095cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED, 4096 machine_mode mode, const_tree type, 4097 bool named ATTRIBUTE_UNUSED) 4098{ 4099 return (targetm.calls.must_pass_in_stack (mode, type) 4100 || CRIS_FUNCTION_ARG_SIZE (mode, type) > 8); 4101} 4102 4103/* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments 4104 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the 4105 best code size and speed for gcc, ipps and products in gcc-2.7.2. */ 4106 4107machine_mode 4108cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, 4109 machine_mode mode, 4110 int *punsignedp ATTRIBUTE_UNUSED, 4111 const_tree fntype ATTRIBUTE_UNUSED, 4112 int for_return) 4113{ 4114 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even 4115 when modifying TARGET_FUNCTION_VALUE to return the promoted mode). 4116 Maybe pointless as of now, but let's keep the old behavior. */ 4117 if (for_return == 1) 4118 return mode; 4119 return CRIS_PROMOTED_MODE (mode, *punsignedp, type); 4120} 4121 4122/* Atomic types require alignment to be at least their "natural" size. */ 4123 4124static unsigned int 4125cris_atomic_align_for_mode (machine_mode mode) 4126{ 4127 return GET_MODE_BITSIZE (mode); 4128} 4129 4130/* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the 4131 time being. */ 4132 4133static rtx 4134cris_function_value(const_tree type, 4135 const_tree func ATTRIBUTE_UNUSED, 4136 bool outgoing ATTRIBUTE_UNUSED) 4137{ 4138 return gen_rtx_REG (TYPE_MODE (type), CRIS_FIRST_ARG_REG); 4139} 4140 4141/* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the 4142 time being. */ 4143 4144static rtx 4145cris_libcall_value (machine_mode mode, 4146 const_rtx fun ATTRIBUTE_UNUSED) 4147{ 4148 return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG); 4149} 4150 4151/* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the 4152 time being. */ 4153 4154static bool 4155cris_function_value_regno_p (const unsigned int regno) 4156{ 4157 return (regno == CRIS_FIRST_ARG_REG); 4158} 4159 4160static int 4161cris_arg_partial_bytes (cumulative_args_t ca, machine_mode mode, 4162 tree type, bool named ATTRIBUTE_UNUSED) 4163{ 4164 if (get_cumulative_args (ca)->regs == CRIS_MAX_ARGS_IN_REGS - 1 4165 && !targetm.calls.must_pass_in_stack (mode, type) 4166 && CRIS_FUNCTION_ARG_SIZE (mode, type) > 4 4167 && CRIS_FUNCTION_ARG_SIZE (mode, type) <= 8) 4168 return UNITS_PER_WORD; 4169 else 4170 return 0; 4171} 4172 4173static rtx 4174cris_function_arg_1 (cumulative_args_t ca_v, 4175 machine_mode mode ATTRIBUTE_UNUSED, 4176 const_tree type ATTRIBUTE_UNUSED, 4177 bool named, bool incoming) 4178{ 4179 const CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); 4180 4181 if ((!incoming || named) && ca->regs < CRIS_MAX_ARGS_IN_REGS) 4182 return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG + ca->regs); 4183 else 4184 return NULL_RTX; 4185} 4186 4187/* Worker function for TARGET_FUNCTION_ARG. 4188 The void_type_node is sent as a "closing" call. */ 4189 4190static rtx 4191cris_function_arg (cumulative_args_t ca, machine_mode mode, 4192 const_tree type, bool named) 4193{ 4194 return cris_function_arg_1 (ca, mode, type, named, false); 4195} 4196 4197/* Worker function for TARGET_FUNCTION_INCOMING_ARG. 4198 4199 The differences between this and the previous, is that this one checks 4200 that an argument is named, since incoming stdarg/varargs arguments are 4201 pushed onto the stack, and we don't have to check against the "closing" 4202 void_type_node TYPE parameter. */ 4203 4204static rtx 4205cris_function_incoming_arg (cumulative_args_t ca, machine_mode mode, 4206 const_tree type, bool named) 4207{ 4208 return cris_function_arg_1 (ca, mode, type, named, true); 4209} 4210 4211/* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */ 4212 4213static void 4214cris_function_arg_advance (cumulative_args_t ca_v, machine_mode mode, 4215 const_tree type, bool named ATTRIBUTE_UNUSED) 4216{ 4217 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); 4218 4219 ca->regs += (3 + CRIS_FUNCTION_ARG_SIZE (mode, type)) / 4; 4220} 4221 4222/* Worker function for TARGET_MD_ASM_CLOBBERS. */ 4223 4224static tree 4225cris_md_asm_clobbers (tree outputs, tree inputs, tree in_clobbers) 4226{ 4227 HARD_REG_SET mof_set; 4228 tree clobbers; 4229 tree t; 4230 4231 CLEAR_HARD_REG_SET (mof_set); 4232 SET_HARD_REG_BIT (mof_set, CRIS_MOF_REGNUM); 4233 4234 /* For the time being, all asms clobber condition codes. Revisit when 4235 there's a reasonable use for inputs/outputs that mention condition 4236 codes. */ 4237 clobbers 4238 = tree_cons (NULL_TREE, 4239 build_string (strlen (reg_names[CRIS_CC0_REGNUM]), 4240 reg_names[CRIS_CC0_REGNUM]), 4241 in_clobbers); 4242 4243 for (t = outputs; t != NULL; t = TREE_CHAIN (t)) 4244 { 4245 tree val = TREE_VALUE (t); 4246 4247 /* The constraint letter for the singleton register class of MOF 4248 is 'h'. If it's mentioned in the constraints, the asm is 4249 MOF-aware and adding it to the clobbers would cause it to have 4250 impossible constraints. */ 4251 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))), 4252 'h') != NULL 4253 || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE) 4254 return clobbers; 4255 } 4256 4257 for (t = inputs; t != NULL; t = TREE_CHAIN (t)) 4258 { 4259 tree val = TREE_VALUE (t); 4260 4261 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))), 4262 'h') != NULL 4263 || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE) 4264 return clobbers; 4265 } 4266 4267 return tree_cons (NULL_TREE, 4268 build_string (strlen (reg_names[CRIS_MOF_REGNUM]), 4269 reg_names[CRIS_MOF_REGNUM]), 4270 clobbers); 4271} 4272 4273/* Implement TARGET_FRAME_POINTER_REQUIRED. 4274 4275 Really only needed if the stack frame has variable length (alloca 4276 or variable sized local arguments (GNU C extension). See PR39499 and 4277 PR38609 for the reason this isn't just 0. */ 4278 4279bool 4280cris_frame_pointer_required (void) 4281{ 4282 return !crtl->sp_is_unchanging; 4283} 4284 4285/* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE. 4286 4287 This looks too complicated, and it is. I assigned r7 to be the 4288 static chain register, but it is call-saved, so we have to save it, 4289 and come back to restore it after the call, so we have to save srp... 4290 Anyway, trampolines are rare enough that we can cope with this 4291 somewhat lack of elegance. 4292 (Do not be tempted to "straighten up" whitespace in the asms; the 4293 assembler #NO_APP state mandates strict spacing). */ 4294/* ??? See the i386 regparm=3 implementation that pushes the static 4295 chain value to the stack in the trampoline, and uses a call-saved 4296 register when called directly. */ 4297 4298static void 4299cris_asm_trampoline_template (FILE *f) 4300{ 4301 if (TARGET_V32) 4302 { 4303 /* This normally-unused nop insn acts as an instruction to 4304 the simulator to flush its instruction cache. None of 4305 the other instructions in the trampoline template suits 4306 as a trigger for V32. The pc-relative addressing mode 4307 works nicely as a trigger for V10. 4308 FIXME: Have specific V32 template (possibly avoiding the 4309 use of a special instruction). */ 4310 fprintf (f, "\tclearf x\n"); 4311 /* We have to use a register as an intermediate, choosing 4312 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM), 4313 so we can use it for address indirection and jsr target. */ 4314 fprintf (f, "\tmove $r1,$mof\n"); 4315 /* +4 */ 4316 fprintf (f, "\tmove.d 0,$r1\n"); 4317 fprintf (f, "\tmove.d $%s,[$r1]\n", reg_names[STATIC_CHAIN_REGNUM]); 4318 fprintf (f, "\taddq 6,$r1\n"); 4319 fprintf (f, "\tmove $mof,[$r1]\n"); 4320 fprintf (f, "\taddq 6,$r1\n"); 4321 fprintf (f, "\tmove $srp,[$r1]\n"); 4322 /* +20 */ 4323 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); 4324 /* +26 */ 4325 fprintf (f, "\tmove.d 0,$r1\n"); 4326 fprintf (f, "\tjsr $r1\n"); 4327 fprintf (f, "\tsetf\n"); 4328 /* +36 */ 4329 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); 4330 /* +42 */ 4331 fprintf (f, "\tmove.d 0,$r1\n"); 4332 /* +48 */ 4333 fprintf (f, "\tmove.d 0,$r9\n"); 4334 fprintf (f, "\tjump $r9\n"); 4335 fprintf (f, "\tsetf\n"); 4336 } 4337 else 4338 { 4339 fprintf (f, "\tmove.d $%s,[$pc+20]\n", reg_names[STATIC_CHAIN_REGNUM]); 4340 fprintf (f, "\tmove $srp,[$pc+22]\n"); 4341 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); 4342 fprintf (f, "\tjsr 0\n"); 4343 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); 4344 fprintf (f, "\tjump 0\n"); 4345 } 4346} 4347 4348/* Implement TARGET_TRAMPOLINE_INIT. */ 4349 4350static void 4351cris_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 4352{ 4353 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); 4354 rtx tramp = XEXP (m_tramp, 0); 4355 rtx mem; 4356 4357 emit_block_move (m_tramp, assemble_trampoline_template (), 4358 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); 4359 4360 if (TARGET_V32) 4361 { 4362 mem = adjust_address (m_tramp, SImode, 6); 4363 emit_move_insn (mem, plus_constant (Pmode, tramp, 38)); 4364 mem = adjust_address (m_tramp, SImode, 22); 4365 emit_move_insn (mem, chain_value); 4366 mem = adjust_address (m_tramp, SImode, 28); 4367 emit_move_insn (mem, fnaddr); 4368 } 4369 else 4370 { 4371 mem = adjust_address (m_tramp, SImode, 10); 4372 emit_move_insn (mem, chain_value); 4373 mem = adjust_address (m_tramp, SImode, 16); 4374 emit_move_insn (mem, fnaddr); 4375 } 4376 4377 /* Note that there is no need to do anything with the cache for 4378 sake of a trampoline. */ 4379} 4380 4381 4382#if 0 4383/* Various small functions to replace macros. Only called from a 4384 debugger. They might collide with gcc functions or system functions, 4385 so only emit them when '#if 1' above. */ 4386 4387enum rtx_code Get_code (rtx); 4388 4389enum rtx_code 4390Get_code (rtx x) 4391{ 4392 return GET_CODE (x); 4393} 4394 4395const char *Get_mode (rtx); 4396 4397const char * 4398Get_mode (rtx x) 4399{ 4400 return GET_MODE_NAME (GET_MODE (x)); 4401} 4402 4403rtx Xexp (rtx, int); 4404 4405rtx 4406Xexp (rtx x, int n) 4407{ 4408 return XEXP (x, n); 4409} 4410 4411rtx Xvecexp (rtx, int, int); 4412 4413rtx 4414Xvecexp (rtx x, int n, int m) 4415{ 4416 return XVECEXP (x, n, m); 4417} 4418 4419int Get_rtx_len (rtx); 4420 4421int 4422Get_rtx_len (rtx x) 4423{ 4424 return GET_RTX_LENGTH (GET_CODE (x)); 4425} 4426 4427/* Use upper-case to distinguish from local variables that are sometimes 4428 called next_insn and prev_insn. */ 4429 4430rtx Next_insn (rtx); 4431 4432rtx 4433Next_insn (rtx insn) 4434{ 4435 return NEXT_INSN (insn); 4436} 4437 4438rtx Prev_insn (rtx); 4439 4440rtx 4441Prev_insn (rtx insn) 4442{ 4443 return PREV_INSN (insn); 4444} 4445#endif 4446 4447#include "gt-cris.h" 4448 4449/* 4450 * Local variables: 4451 * eval: (c-set-style "gnu") 4452 * indent-tabs-mode: t 4453 * End: 4454 */ 4455