1/* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2015 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha@arm.com) 6 Minor hacks by Nick Clifton (nickc@cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29#ifndef GCC_ARM_H 30#define GCC_ARM_H 31 32/* We can't use machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35#ifdef GENERATOR_FILE 36#define MACHMODE int 37#else 38#include "insn-modes.h" 39#define MACHMODE machine_mode 40#endif 41 42#include "config/vxworks-dummy.h" 43 44/* The architecture define. */ 45extern char arm_arch_name[]; 46 47/* Target CPU builtins. */ 48#define TARGET_CPU_CPP_BUILTINS() \ 49 do \ 50 { \ 51 if (TARGET_DSP_MULTIPLY) \ 52 builtin_define ("__ARM_FEATURE_DSP"); \ 53 if (TARGET_ARM_QBIT) \ 54 builtin_define ("__ARM_FEATURE_QBIT"); \ 55 if (TARGET_ARM_SAT) \ 56 builtin_define ("__ARM_FEATURE_SAT"); \ 57 if (TARGET_CRYPTO) \ 58 builtin_define ("__ARM_FEATURE_CRYPTO"); \ 59 if (unaligned_access) \ 60 builtin_define ("__ARM_FEATURE_UNALIGNED"); \ 61 if (TARGET_CRC32) \ 62 builtin_define ("__ARM_FEATURE_CRC32"); \ 63 if (TARGET_32BIT) \ 64 builtin_define ("__ARM_32BIT_STATE"); \ 65 if (TARGET_ARM_FEATURE_LDREX) \ 66 builtin_define_with_int_value ( \ 67 "__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); \ 68 if ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) \ 69 || TARGET_ARM_ARCH_ISA_THUMB >=2) \ 70 builtin_define ("__ARM_FEATURE_CLZ"); \ 71 if (TARGET_INT_SIMD) \ 72 builtin_define ("__ARM_FEATURE_SIMD32"); \ 73 \ 74 builtin_define_with_int_value ( \ 75 "__ARM_SIZEOF_MINIMAL_ENUM", \ 76 flag_short_enums ? 1 : 4); \ 77 builtin_define_type_sizeof ("__ARM_SIZEOF_WCHAR_T", \ 78 wchar_type_node); \ 79 if (TARGET_ARM_ARCH_PROFILE) \ 80 builtin_define_with_int_value ( \ 81 "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \ 82 \ 83 /* Define __arm__ even when in thumb mode, for \ 84 consistency with armcc. */ \ 85 builtin_define ("__arm__"); \ 86 if (TARGET_ARM_ARCH) \ 87 builtin_define_with_int_value ( \ 88 "__ARM_ARCH", TARGET_ARM_ARCH); \ 89 if (arm_arch_notm) \ 90 builtin_define ("__ARM_ARCH_ISA_ARM"); \ 91 builtin_define ("__APCS_32__"); \ 92 if (TARGET_THUMB) \ 93 builtin_define ("__thumb__"); \ 94 if (TARGET_THUMB2) \ 95 builtin_define ("__thumb2__"); \ 96 if (TARGET_ARM_ARCH_ISA_THUMB) \ 97 builtin_define_with_int_value ( \ 98 "__ARM_ARCH_ISA_THUMB", \ 99 TARGET_ARM_ARCH_ISA_THUMB); \ 100 \ 101 if (TARGET_BIG_END) \ 102 { \ 103 builtin_define ("__ARMEB__"); \ 104 builtin_define ("__ARM_BIG_ENDIAN"); \ 105 if (TARGET_THUMB) \ 106 builtin_define ("__THUMBEB__"); \ 107 } \ 108 else \ 109 { \ 110 builtin_define ("__ARMEL__"); \ 111 if (TARGET_THUMB) \ 112 builtin_define ("__THUMBEL__"); \ 113 } \ 114 \ 115 if (TARGET_SOFT_FLOAT) \ 116 builtin_define ("__SOFTFP__"); \ 117 \ 118 if (TARGET_VFP) \ 119 builtin_define ("__VFP_FP__"); \ 120 \ 121 if (TARGET_ARM_FP) \ 122 builtin_define_with_int_value ( \ 123 "__ARM_FP", TARGET_ARM_FP); \ 124 if (arm_fp16_format == ARM_FP16_FORMAT_IEEE) \ 125 builtin_define ("__ARM_FP16_FORMAT_IEEE"); \ 126 if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) \ 127 builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE"); \ 128 if (TARGET_FMA) \ 129 builtin_define ("__ARM_FEATURE_FMA"); \ 130 \ 131 if (TARGET_NEON) \ 132 { \ 133 builtin_define ("__ARM_NEON__"); \ 134 builtin_define ("__ARM_NEON"); \ 135 } \ 136 if (TARGET_NEON_FP) \ 137 builtin_define_with_int_value ( \ 138 "__ARM_NEON_FP", TARGET_NEON_FP); \ 139 \ 140 /* Add a define for interworking. \ 141 Needed when building libgcc.a. */ \ 142 if (arm_cpp_interwork) \ 143 builtin_define ("__THUMB_INTERWORK__"); \ 144 \ 145 builtin_assert ("cpu=arm"); \ 146 builtin_assert ("machine=arm"); \ 147 \ 148 builtin_define (arm_arch_name); \ 149 if (arm_arch_xscale) \ 150 builtin_define ("__XSCALE__"); \ 151 if (arm_arch_iwmmxt) \ 152 { \ 153 builtin_define ("__IWMMXT__"); \ 154 builtin_define ("__ARM_WMMX"); \ 155 } \ 156 if (arm_arch_iwmmxt2) \ 157 builtin_define ("__IWMMXT2__"); \ 158 if (TARGET_AAPCS_BASED) \ 159 { \ 160 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ 161 builtin_define ("__ARM_PCS_VFP"); \ 162 else if (arm_pcs_default == ARM_PCS_AAPCS) \ 163 builtin_define ("__ARM_PCS"); \ 164 builtin_define ("__ARM_EABI__"); \ 165 } \ 166 if (TARGET_IDIV) \ 167 { \ 168 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \ 169 builtin_define ("__ARM_FEATURE_IDIV"); \ 170 } \ 171 if (inline_asm_unified) \ 172 builtin_define ("__ARM_ASM_SYNTAX_UNIFIED__");\ 173 } while (0) 174 175#include "config/arm/arm-opts.h" 176 177enum target_cpus 178{ 179#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \ 180 TARGET_CPU_##INTERNAL_IDENT, 181#include "arm-cores.def" 182#undef ARM_CORE 183 TARGET_CPU_generic 184}; 185 186/* The processor for which instructions should be scheduled. */ 187extern enum processor_type arm_tune; 188 189typedef enum arm_cond_code 190{ 191 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 192 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 193} 194arm_cc; 195 196extern arm_cc arm_current_cc; 197 198#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 199 200/* The maximum number of instructions that is beneficial to 201 conditionally execute. */ 202#undef MAX_CONDITIONAL_EXECUTE 203#define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 204 205extern int arm_target_label; 206extern int arm_ccfsm_state; 207extern GTY(()) rtx arm_target_insn; 208/* The label of the current constant pool. */ 209extern rtx pool_vector_label; 210/* Set to 1 when a return insn is output, this means that the epilogue 211 is not needed. */ 212extern int return_used_this_function; 213/* Callback to output language specific object attributes. */ 214extern void (*arm_lang_output_object_attributes_hook)(void); 215 216/* Just in case configure has failed to define anything. */ 217#ifndef TARGET_CPU_DEFAULT 218#define TARGET_CPU_DEFAULT TARGET_CPU_generic 219#endif 220 221 222#undef CPP_SPEC 223#define CPP_SPEC "%(subtarget_cpp_spec) \ 224%{mfloat-abi=soft:%{mfloat-abi=hard: \ 225 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ 226%{mbig-endian:%{mlittle-endian: \ 227 %e-mbig-endian and -mlittle-endian may not be used together}}" 228 229#ifndef CC1_SPEC 230#define CC1_SPEC "" 231#endif 232 233/* This macro defines names of additional specifications to put in the specs 234 that can be used in various specifications like CC1_SPEC. Its definition 235 is an initializer with a subgrouping for each command option. 236 237 Each subgrouping contains a string constant, that defines the 238 specification name, and a string constant that used by the GCC driver 239 program. 240 241 Do not define this macro if it does not need to do anything. */ 242#define EXTRA_SPECS \ 243 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 244 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 245 SUBTARGET_EXTRA_SPECS 246 247#ifndef SUBTARGET_EXTRA_SPECS 248#define SUBTARGET_EXTRA_SPECS 249#endif 250 251#ifndef SUBTARGET_CPP_SPEC 252#define SUBTARGET_CPP_SPEC "" 253#endif 254 255/* Run-time Target Specification. */ 256#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) 257/* Use hardware floating point instructions. */ 258#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 259/* Use hardware floating point calling convention. */ 260#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 261#define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) 262#define TARGET_IWMMXT (arm_arch_iwmmxt) 263#define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 264#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) 265#define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT) 266#define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 267#define TARGET_ARM (! TARGET_THUMB) 268#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 269#define TARGET_BACKTRACE (leaf_function_p () \ 270 ? TARGET_TPCS_LEAF_FRAME \ 271 : TARGET_TPCS_FRAME) 272#define TARGET_AAPCS_BASED \ 273 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 274 275#define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 276#define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 277#define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 278 279/* Only 16-bit thumb code. */ 280#define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 281/* Arm or Thumb-2 32-bit code. */ 282#define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 283/* 32-bit Thumb-2 code. */ 284#define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 285/* Thumb-1 only. */ 286#define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 287 288#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ 289 && !TARGET_THUMB1) 290 291#define TARGET_CRC32 (arm_arch_crc) 292 293/* The following two macros concern the ability to execute coprocessor 294 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 295 only ever tested when we know we are generating for VFP hardware; we need 296 to be more careful with TARGET_NEON as noted below. */ 297 298/* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 299#define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32) 300 301/* FPU supports VFPv3 instructions. */ 302#define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) 303 304/* FPU supports FPv5 instructions. */ 305#define TARGET_VFP5 (TARGET_VFP && arm_fpu_desc->rev >= 5) 306 307/* FPU only supports VFP single-precision instructions. */ 308#define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) 309 310/* FPU supports VFP double-precision instructions. */ 311#define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE) 312 313/* FPU supports half-precision floating-point with NEON element load/store. */ 314#define TARGET_NEON_FP16 \ 315 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16) 316 317/* FPU supports VFP half-precision floating-point. */ 318#define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) 319 320/* FPU supports fused-multiply-add operations. */ 321#define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4) 322 323/* FPU is ARMv8 compatible. */ 324#define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >= 8) 325 326/* FPU supports Crypto extensions. */ 327#define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto) 328 329/* FPU supports Neon instructions. The setting of this macro gets 330 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 331 and TARGET_HARD_FLOAT to ensure that NEON instructions are 332 available. */ 333#define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ 334 && TARGET_VFP && arm_fpu_desc->neon) 335 336/* Q-bit is present. */ 337#define TARGET_ARM_QBIT \ 338 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7)) 339/* Saturation operation, e.g. SSAT. */ 340#define TARGET_ARM_SAT \ 341 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 342/* "DSP" multiply instructions, eg. SMULxy. */ 343#define TARGET_DSP_MULTIPLY \ 344 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) 345/* Integer SIMD instructions, and extend-accumulate instructions. */ 346#define TARGET_INT_SIMD \ 347 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 348 349/* Should MOVW/MOVT be used in preference to a constant pool. */ 350#define TARGET_USE_MOVT \ 351 (arm_arch_thumb2 \ 352 && (arm_disable_literal_pool \ 353 || (!optimize_size && !current_tune->prefer_constant_pool))) 354 355/* We could use unified syntax for arm mode, but for now we just use it 356 for thumb mode. */ 357#define TARGET_UNIFIED_ASM (TARGET_THUMB) 358 359/* Nonzero if this chip provides the DMB instruction. */ 360#define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 361 362/* Nonzero if this chip implements a memory barrier via CP15. */ 363#define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 364 && ! TARGET_THUMB1) 365 366/* Nonzero if this chip implements a memory barrier instruction. */ 367#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 368 369/* Nonzero if this chip supports ldrex and strex */ 370#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) 371 372/* Nonzero if this chip supports LPAE. */ 373#define TARGET_HAVE_LPAE \ 374 (arm_arch7 && ((insn_flags & FL_FOR_ARCH7VE) == FL_FOR_ARCH7VE)) 375 376/* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 377#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) 378 379/* Nonzero if this chip supports ldrexd and strexd. */ 380#define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \ 381 && arm_arch_notm) 382 383/* Nonzero if this chip supports load-acquire and store-release. */ 384#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 385 386/* Nonzero if integer division instructions supported. */ 387#define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 388 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) 389 390/* Nonzero if disallow volatile memory access in IT block. */ 391#define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) 392 393/* Should NEON be used for 64-bits bitops. */ 394#define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) 395 396/* True iff the full BPABI is being used. If TARGET_BPABI is true, 397 then TARGET_AAPCS_BASED must be true -- but the converse does not 398 hold. TARGET_BPABI implies the use of the BPABI runtime library, 399 etc., in addition to just the AAPCS calling conventions. */ 400#ifndef TARGET_BPABI 401#define TARGET_BPABI false 402#endif 403 404/* Support for a compile-time default CPU, et cetera. The rules are: 405 --with-arch is ignored if -march or -mcpu are specified. 406 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 407 by --with-arch. 408 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 409 by -march). 410 --with-float is ignored if -mfloat-abi is specified. 411 --with-fpu is ignored if -mfpu is specified. 412 --with-abi is ignored if -mabi is specified. 413 --with-tls is ignored if -mtls-dialect is specified. */ 414#define OPTION_DEFAULT_SPECS \ 415 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 416 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 417 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 418 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 419 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 420 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 421 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ 422 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 423 424/* Which floating point model to use. */ 425enum arm_fp_model 426{ 427 ARM_FP_MODEL_UNKNOWN, 428 /* VFP floating point model. */ 429 ARM_FP_MODEL_VFP 430}; 431 432enum vfp_reg_type 433{ 434 VFP_NONE = 0, 435 VFP_REG_D16, 436 VFP_REG_D32, 437 VFP_REG_SINGLE 438}; 439 440extern const struct arm_fpu_desc 441{ 442 const char *name; 443 enum arm_fp_model model; 444 int rev; 445 enum vfp_reg_type regs; 446 int neon; 447 int fp16; 448 int crypto; 449} *arm_fpu_desc; 450 451/* Which floating point hardware to schedule for. */ 452extern int arm_fpu_attr; 453 454#ifndef TARGET_DEFAULT_FLOAT_ABI 455#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 456#endif 457 458#ifndef ARM_DEFAULT_ABI 459#define ARM_DEFAULT_ABI ARM_ABI_APCS 460#endif 461 462/* Map each of the micro-architecture variants to their corresponding 463 major architecture revision. */ 464 465enum base_architecture 466{ 467 BASE_ARCH_0 = 0, 468 BASE_ARCH_2 = 2, 469 BASE_ARCH_3 = 3, 470 BASE_ARCH_3M = 3, 471 BASE_ARCH_4 = 4, 472 BASE_ARCH_4T = 4, 473 BASE_ARCH_5 = 5, 474 BASE_ARCH_5E = 5, 475 BASE_ARCH_5T = 5, 476 BASE_ARCH_5TE = 5, 477 BASE_ARCH_5TEJ = 5, 478 BASE_ARCH_6 = 6, 479 BASE_ARCH_6J = 6, 480 BASE_ARCH_6ZK = 6, 481 BASE_ARCH_6K = 6, 482 BASE_ARCH_6T2 = 6, 483 BASE_ARCH_6M = 6, 484 BASE_ARCH_6Z = 6, 485 BASE_ARCH_7 = 7, 486 BASE_ARCH_7A = 7, 487 BASE_ARCH_7R = 7, 488 BASE_ARCH_7M = 7, 489 BASE_ARCH_7EM = 7, 490 BASE_ARCH_8A = 8 491}; 492 493/* The major revision number of the ARM Architecture implemented by the target. */ 494extern enum base_architecture arm_base_arch; 495 496/* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 497extern int arm_arch3m; 498 499/* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 500extern int arm_arch4; 501 502/* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 503extern int arm_arch4t; 504 505/* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 506extern int arm_arch5; 507 508/* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 509extern int arm_arch5e; 510 511/* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 512extern int arm_arch6; 513 514/* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 515extern int arm_arch6k; 516 517/* Nonzero if instructions present in ARMv6-M can be used. */ 518extern int arm_arch6m; 519 520/* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 521extern int arm_arch7; 522 523/* Nonzero if instructions not present in the 'M' profile can be used. */ 524extern int arm_arch_notm; 525 526/* Nonzero if instructions present in ARMv7E-M can be used. */ 527extern int arm_arch7em; 528 529/* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 530extern int arm_arch8; 531 532/* Nonzero if this chip can benefit from load scheduling. */ 533extern int arm_ld_sched; 534 535/* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */ 536extern int thumb_code; 537 538/* Nonzero if generating Thumb-1 code. */ 539extern int thumb1_code; 540 541/* Nonzero if this chip is a StrongARM. */ 542extern int arm_tune_strongarm; 543 544/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 545extern int arm_arch_iwmmxt; 546 547/* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 548extern int arm_arch_iwmmxt2; 549 550/* Nonzero if this chip is an XScale. */ 551extern int arm_arch_xscale; 552 553/* Nonzero if tuning for XScale. */ 554extern int arm_tune_xscale; 555 556/* Nonzero if tuning for stores via the write buffer. */ 557extern int arm_tune_wbuf; 558 559/* Nonzero if tuning for Cortex-A9. */ 560extern int arm_tune_cortex_a9; 561 562/* Nonzero if we should define __THUMB_INTERWORK__ in the 563 preprocessor. 564 XXX This is a bit of a hack, it's intended to help work around 565 problems in GLD which doesn't understand that armv5t code is 566 interworking clean. */ 567extern int arm_cpp_interwork; 568 569/* Nonzero if chip supports Thumb 2. */ 570extern int arm_arch_thumb2; 571 572/* Nonzero if chip supports integer division instruction in ARM mode. */ 573extern int arm_arch_arm_hwdiv; 574 575/* Nonzero if chip supports integer division instruction in Thumb mode. */ 576extern int arm_arch_thumb_hwdiv; 577 578/* Nonzero if chip disallows volatile memory access in IT block. */ 579extern int arm_arch_no_volatile_ce; 580 581/* Nonzero if we should use Neon to handle 64-bits operations rather 582 than core registers. */ 583extern int prefer_neon_for_64bits; 584 585/* Nonzero if we shouldn't use literal pools. */ 586#ifndef USED_FOR_TARGET 587extern bool arm_disable_literal_pool; 588#endif 589 590/* Nonzero if chip supports the ARMv8 CRC instructions. */ 591extern int arm_arch_crc; 592 593#ifndef TARGET_DEFAULT 594#define TARGET_DEFAULT (MASK_APCS_FRAME) 595#endif 596 597/* Nonzero if PIC code requires explicit qualifiers to generate 598 PLT and GOT relocs rather than the assembler doing so implicitly. 599 Subtargets can override these if required. */ 600#ifndef NEED_GOT_RELOC 601#define NEED_GOT_RELOC 0 602#endif 603#ifndef NEED_PLT_RELOC 604#define NEED_PLT_RELOC 0 605#endif 606 607#ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 608#define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 609#endif 610 611/* Nonzero if we need to refer to the GOT with a PC-relative 612 offset. In other words, generate 613 614 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 615 616 rather than 617 618 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 619 620 The default is true, which matches NetBSD. Subtargets can 621 override this if required. */ 622#ifndef GOT_PCREL 623#define GOT_PCREL 1 624#endif 625 626/* Target machine storage Layout. */ 627 628 629/* Define this macro if it is advisable to hold scalars in registers 630 in a wider mode than that declared by the program. In such cases, 631 the value is constrained to be within the bounds of the declared 632 type, but kept valid in the wider mode. The signedness of the 633 extension may differ from that of the type. */ 634 635#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 636 if (GET_MODE_CLASS (MODE) == MODE_INT \ 637 && GET_MODE_SIZE (MODE) < 4) \ 638 { \ 639 (MODE) = SImode; \ 640 } 641 642/* Define this if most significant bit is lowest numbered 643 in instructions that operate on numbered bit-fields. */ 644#define BITS_BIG_ENDIAN 0 645 646/* Define this if most significant byte of a word is the lowest numbered. 647 Most ARM processors are run in little endian mode, so that is the default. 648 If you want to have it run-time selectable, change the definition in a 649 cover file to be TARGET_BIG_ENDIAN. */ 650#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 651 652/* Define this if most significant word of a multiword number is the lowest 653 numbered. */ 654#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 655 656#define UNITS_PER_WORD 4 657 658/* True if natural alignment is used for doubleword types. */ 659#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 660 661#define DOUBLEWORD_ALIGNMENT 64 662 663#define PARM_BOUNDARY 32 664 665#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 666 667#define PREFERRED_STACK_BOUNDARY \ 668 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 669 670#define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32) 671 672/* The lowest bit is used to indicate Thumb-mode functions, so the 673 vbit must go into the delta field of pointers to member 674 functions. */ 675#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 676 677#define EMPTY_FIELD_BOUNDARY 32 678 679#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 680 681#define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 682 683/* XXX Blah -- this macro is used directly by libobjc. Since it 684 supports no vector modes, cut out the complexity and fall back 685 on BIGGEST_FIELD_ALIGNMENT. */ 686#ifdef IN_TARGET_LIBS 687#define BIGGEST_FIELD_ALIGNMENT 64 688#endif 689 690/* Make strings word-aligned so strcpy from constants will be faster. */ 691#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 692 693#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 694 ((TREE_CODE (EXP) == STRING_CST \ 695 && !optimize_size \ 696 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 697 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 698 699/* Align definitions of arrays, unions and structures so that 700 initializations and copies can be made more efficient. This is not 701 ABI-changing, so it only affects places where we can see the 702 definition. Increasing the alignment tends to introduce padding, 703 so don't do this when optimizing for size/conserving stack space. */ 704#define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 705 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 706 && (TREE_CODE (EXP) == ARRAY_TYPE \ 707 || TREE_CODE (EXP) == UNION_TYPE \ 708 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 709 710/* Align global data. */ 711#define DATA_ALIGNMENT(EXP, ALIGN) \ 712 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 713 714/* Similarly, make sure that objects on the stack are sensibly aligned. */ 715#define LOCAL_ALIGNMENT(EXP, ALIGN) \ 716 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 717 718/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 719 value set in previous versions of this toolchain was 8, which produces more 720 compact structures. The command line option -mstructure_size_boundary=<n> 721 can be used to change this value. For compatibility with the ARM SDK 722 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 723 0020D) page 2-20 says "Structures are aligned on word boundaries". 724 The AAPCS specifies a value of 8. */ 725#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 726 727/* This is the value used to initialize arm_structure_size_boundary. If a 728 particular arm target wants to change the default value it should change 729 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 730 for an example of this. */ 731#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 732#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 733#endif 734 735/* Nonzero if move instructions will actually fail to work 736 when given unaligned data. */ 737#define STRICT_ALIGNMENT 1 738 739/* wchar_t is unsigned under the AAPCS. */ 740#ifndef WCHAR_TYPE 741#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 742 743#define WCHAR_TYPE_SIZE BITS_PER_WORD 744#endif 745 746/* Sized for fixed-point types. */ 747 748#define SHORT_FRACT_TYPE_SIZE 8 749#define FRACT_TYPE_SIZE 16 750#define LONG_FRACT_TYPE_SIZE 32 751#define LONG_LONG_FRACT_TYPE_SIZE 64 752 753#define SHORT_ACCUM_TYPE_SIZE 16 754#define ACCUM_TYPE_SIZE 32 755#define LONG_ACCUM_TYPE_SIZE 64 756#define LONG_LONG_ACCUM_TYPE_SIZE 64 757 758#define MAX_FIXED_MODE_SIZE 64 759 760#ifndef SIZE_TYPE 761#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 762#endif 763 764#ifndef PTRDIFF_TYPE 765#define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 766#endif 767 768/* AAPCS requires that structure alignment is affected by bitfields. */ 769#ifndef PCC_BITFIELD_TYPE_MATTERS 770#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 771#endif 772 773/* The maximum size of the sync library functions supported. */ 774#ifndef MAX_SYNC_LIBFUNC_SIZE 775#define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) 776#endif 777 778 779/* Standard register usage. */ 780 781/* Register allocation in ARM Procedure Call Standard 782 (S - saved over call). 783 784 r0 * argument word/integer result 785 r1-r3 argument word 786 787 r4-r8 S register variable 788 r9 S (rfp) register variable (real frame pointer) 789 790 r10 F S (sl) stack limit (used by -mapcs-stack-check) 791 r11 F S (fp) argument pointer 792 r12 (ip) temp workspace 793 r13 F S (sp) lower end of current stack frame 794 r14 (lr) link address/workspace 795 r15 F (pc) program counter 796 797 cc This is NOT a real register, but is used internally 798 to represent things that use or set the condition 799 codes. 800 sfp This isn't either. It is used during rtl generation 801 since the offset between the frame pointer and the 802 auto's isn't known until after register allocation. 803 afp Nor this, we only need this because of non-local 804 goto. Without it fp appears to be used and the 805 elimination code won't get rid of sfp. It tracks 806 fp exactly at all times. 807 808 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 809 810/* s0-s15 VFP scratch (aka d0-d7). 811 s16-s31 S VFP variable (aka d8-d15). 812 vfpcc Not a real register. Represents the VFP condition 813 code flags. */ 814 815/* The stack backtrace structure is as follows: 816 fp points to here: | save code pointer | [fp] 817 | return link value | [fp, #-4] 818 | return sp value | [fp, #-8] 819 | return fp value | [fp, #-12] 820 [| saved r10 value |] 821 [| saved r9 value |] 822 [| saved r8 value |] 823 [| saved r7 value |] 824 [| saved r6 value |] 825 [| saved r5 value |] 826 [| saved r4 value |] 827 [| saved r3 value |] 828 [| saved r2 value |] 829 [| saved r1 value |] 830 [| saved r0 value |] 831 r0-r3 are not normally saved in a C function. */ 832 833/* 1 for registers that have pervasive standard uses 834 and are not available for the register allocator. */ 835#define FIXED_REGISTERS \ 836{ \ 837 /* Core regs. */ \ 838 0,0,0,0,0,0,0,0, \ 839 0,0,0,0,0,1,0,1, \ 840 /* VFP regs. */ \ 841 1,1,1,1,1,1,1,1, \ 842 1,1,1,1,1,1,1,1, \ 843 1,1,1,1,1,1,1,1, \ 844 1,1,1,1,1,1,1,1, \ 845 1,1,1,1,1,1,1,1, \ 846 1,1,1,1,1,1,1,1, \ 847 1,1,1,1,1,1,1,1, \ 848 1,1,1,1,1,1,1,1, \ 849 /* IWMMXT regs. */ \ 850 1,1,1,1,1,1,1,1, \ 851 1,1,1,1,1,1,1,1, \ 852 1,1,1,1, \ 853 /* Specials. */ \ 854 1,1,1,1 \ 855} 856 857/* 1 for registers not available across function calls. 858 These must include the FIXED_REGISTERS and also any 859 registers that can be used without being saved. 860 The latter must include the registers where values are returned 861 and the register where structure-value addresses are passed. 862 Aside from that, you can include as many other registers as you like. 863 The CC is not preserved over function calls on the ARM 6, so it is 864 easier to assume this for all. SFP is preserved, since FP is. */ 865#define CALL_USED_REGISTERS \ 866{ \ 867 /* Core regs. */ \ 868 1,1,1,1,0,0,0,0, \ 869 0,0,0,0,1,1,1,1, \ 870 /* VFP Regs. */ \ 871 1,1,1,1,1,1,1,1, \ 872 1,1,1,1,1,1,1,1, \ 873 1,1,1,1,1,1,1,1, \ 874 1,1,1,1,1,1,1,1, \ 875 1,1,1,1,1,1,1,1, \ 876 1,1,1,1,1,1,1,1, \ 877 1,1,1,1,1,1,1,1, \ 878 1,1,1,1,1,1,1,1, \ 879 /* IWMMXT regs. */ \ 880 1,1,1,1,1,1,1,1, \ 881 1,1,1,1,1,1,1,1, \ 882 1,1,1,1, \ 883 /* Specials. */ \ 884 1,1,1,1 \ 885} 886 887#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 888#define SUBTARGET_CONDITIONAL_REGISTER_USAGE 889#endif 890 891/* These are a couple of extensions to the formats accepted 892 by asm_fprintf: 893 %@ prints out ASM_COMMENT_START 894 %r prints out REGISTER_PREFIX reg_names[arg] */ 895#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 896 case '@': \ 897 fputs (ASM_COMMENT_START, FILE); \ 898 break; \ 899 \ 900 case 'r': \ 901 fputs (REGISTER_PREFIX, FILE); \ 902 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 903 break; 904 905/* Round X up to the nearest word. */ 906#define ROUND_UP_WORD(X) (((X) + 3) & ~3) 907 908/* Convert fron bytes to ints. */ 909#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 910 911/* The number of (integer) registers required to hold a quantity of type MODE. 912 Also used for VFP registers. */ 913#define ARM_NUM_REGS(MODE) \ 914 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 915 916/* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 917#define ARM_NUM_REGS2(MODE, TYPE) \ 918 ARM_NUM_INTS ((MODE) == BLKmode ? \ 919 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 920 921/* The number of (integer) argument register available. */ 922#define NUM_ARG_REGS 4 923 924/* And similarly for the VFP. */ 925#define NUM_VFP_ARG_REGS 16 926 927/* Return the register number of the N'th (integer) argument. */ 928#define ARG_REGISTER(N) (N - 1) 929 930/* Specify the registers used for certain standard purposes. 931 The values of these macros are register numbers. */ 932 933/* The number of the last argument register. */ 934#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 935 936/* The numbers of the Thumb register ranges. */ 937#define FIRST_LO_REGNUM 0 938#define LAST_LO_REGNUM 7 939#define FIRST_HI_REGNUM 8 940#define LAST_HI_REGNUM 11 941 942/* Overridden by config/arm/bpabi.h. */ 943#ifndef ARM_UNWIND_INFO 944#define ARM_UNWIND_INFO 0 945#endif 946 947/* Use r0 and r1 to pass exception handling information. */ 948#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 949 950/* The register that holds the return address in exception handlers. */ 951#define ARM_EH_STACKADJ_REGNUM 2 952#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 953 954#ifndef ARM_TARGET2_DWARF_FORMAT 955#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 956#endif 957 958/* ttype entries (the only interesting data references used) 959 use TARGET2 relocations. */ 960#define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 961 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 962 : DW_EH_PE_absptr) 963 964/* The native (Norcroft) Pascal compiler for the ARM passes the static chain 965 as an invisible last argument (possible since varargs don't exist in 966 Pascal), so the following is not true. */ 967#define STATIC_CHAIN_REGNUM 12 968 969/* Define this to be where the real frame pointer is if it is not possible to 970 work out the offset between the frame pointer and the automatic variables 971 until after register allocation has taken place. FRAME_POINTER_REGNUM 972 should point to a special register that we will make sure is eliminated. 973 974 For the Thumb we have another problem. The TPCS defines the frame pointer 975 as r11, and GCC believes that it is always possible to use the frame pointer 976 as base register for addressing purposes. (See comments in 977 find_reloads_address()). But - the Thumb does not allow high registers, 978 including r11, to be used as base address registers. Hence our problem. 979 980 The solution used here, and in the old thumb port is to use r7 instead of 981 r11 as the hard frame pointer and to have special code to generate 982 backtrace structures on the stack (if required to do so via a command line 983 option) using r11. This is the only 'user visible' use of r11 as a frame 984 pointer. */ 985#define ARM_HARD_FRAME_POINTER_REGNUM 11 986#define THUMB_HARD_FRAME_POINTER_REGNUM 7 987 988#define HARD_FRAME_POINTER_REGNUM \ 989 (TARGET_ARM \ 990 ? ARM_HARD_FRAME_POINTER_REGNUM \ 991 : THUMB_HARD_FRAME_POINTER_REGNUM) 992 993#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 994#define HARD_FRAME_POINTER_IS_ARG_POINTER 0 995 996#define FP_REGNUM HARD_FRAME_POINTER_REGNUM 997 998/* Register to use for pushing function arguments. */ 999#define STACK_POINTER_REGNUM SP_REGNUM 1000 1001#define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 1002#define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 1003 1004/* Need to sync with WCGR in iwmmxt.md. */ 1005#define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 1006#define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 1007 1008#define IS_IWMMXT_REGNUM(REGNUM) \ 1009 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 1010#define IS_IWMMXT_GR_REGNUM(REGNUM) \ 1011 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 1012 1013/* Base register for access to local variables of the function. */ 1014#define FRAME_POINTER_REGNUM 102 1015 1016/* Base register for access to arguments of the function. */ 1017#define ARG_POINTER_REGNUM 103 1018 1019#define FIRST_VFP_REGNUM 16 1020#define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 1021#define LAST_VFP_REGNUM \ 1022 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 1023 1024#define IS_VFP_REGNUM(REGNUM) \ 1025 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 1026 1027/* VFP registers are split into two types: those defined by VFP versions < 3 1028 have D registers overlaid on consecutive pairs of S registers. VFP version 3 1029 defines 16 new D registers (d16-d31) which, for simplicity and correctness 1030 in various parts of the backend, we implement as "fake" single-precision 1031 registers (which would be S32-S63, but cannot be used in that way). The 1032 following macros define these ranges of registers. */ 1033#define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 1034#define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 1035#define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 1036 1037#define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 1038 ((REGNUM) <= LAST_LO_VFP_REGNUM) 1039 1040/* DFmode values are only valid in even register pairs. */ 1041#define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1042 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1043 1044/* Neon Quad values must start at a multiple of four registers. */ 1045#define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1046 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1047 1048/* Neon structures of vectors must be in even register pairs and there 1049 must be enough registers available. Because of various patterns 1050 requiring quad registers, we require them to start at a multiple of 1051 four. */ 1052#define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1053 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1054 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1055 1056/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */ 1057/* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1058/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 1059#define FIRST_PSEUDO_REGISTER 104 1060 1061#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1062 1063/* Value should be nonzero if functions must have frame pointers. 1064 Zero means the frame pointer need not be set up (and parms may be accessed 1065 via the stack pointer) in functions that seem suitable. 1066 If we have to have a frame pointer we might as well make use of it. 1067 APCS says that the frame pointer does not need to be pushed in leaf 1068 functions, or simple tail call functions. */ 1069 1070#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1071#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1072#endif 1073 1074/* Return number of consecutive hard regs needed starting at reg REGNO 1075 to hold something of mode MODE. 1076 This is ordinarily the length in words of a value of mode MODE 1077 but can be less for certain modes in special long registers. 1078 1079 On the ARM core regs are UNITS_PER_WORD bits wide. */ 1080#define HARD_REGNO_NREGS(REGNO, MODE) \ 1081 ((TARGET_32BIT \ 1082 && REGNO > PC_REGNUM \ 1083 && REGNO != FRAME_POINTER_REGNUM \ 1084 && REGNO != ARG_POINTER_REGNUM) \ 1085 && !IS_VFP_REGNUM (REGNO) \ 1086 ? 1 : ARM_NUM_REGS (MODE)) 1087 1088/* Return true if REGNO is suitable for holding a quantity of type MODE. */ 1089#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1090 arm_hard_regno_mode_ok ((REGNO), (MODE)) 1091 1092#define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2) 1093 1094#define VALID_IWMMXT_REG_MODE(MODE) \ 1095 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1096 1097/* Modes valid for Neon D registers. */ 1098#define VALID_NEON_DREG_MODE(MODE) \ 1099 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1100 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode) 1101 1102/* Modes valid for Neon Q registers. */ 1103#define VALID_NEON_QREG_MODE(MODE) \ 1104 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1105 || (MODE) == V4SFmode || (MODE) == V2DImode) 1106 1107/* Structure modes valid for Neon registers. */ 1108#define VALID_NEON_STRUCT_MODE(MODE) \ 1109 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1110 || (MODE) == CImode || (MODE) == XImode) 1111 1112/* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1113extern int arm_regs_in_sequence[]; 1114 1115/* The order in which register should be allocated. It is good to use ip 1116 since no saving is required (though calls clobber it) and it never contains 1117 function parameters. It is quite good to use lr since other calls may 1118 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1119 least likely to contain a function parameter; in addition results are 1120 returned in r0. 1121 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1122 then D8-D15. The reason for doing this is to attempt to reduce register 1123 pressure when both single- and double-precision registers are used in a 1124 function. */ 1125 1126#define VREG(X) (FIRST_VFP_REGNUM + (X)) 1127#define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1128#define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1129 1130#define REG_ALLOC_ORDER \ 1131{ \ 1132 /* General registers. */ \ 1133 3, 2, 1, 0, 12, 14, 4, 5, \ 1134 6, 7, 8, 9, 10, 11, \ 1135 /* High VFP registers. */ \ 1136 VREG(32), VREG(33), VREG(34), VREG(35), \ 1137 VREG(36), VREG(37), VREG(38), VREG(39), \ 1138 VREG(40), VREG(41), VREG(42), VREG(43), \ 1139 VREG(44), VREG(45), VREG(46), VREG(47), \ 1140 VREG(48), VREG(49), VREG(50), VREG(51), \ 1141 VREG(52), VREG(53), VREG(54), VREG(55), \ 1142 VREG(56), VREG(57), VREG(58), VREG(59), \ 1143 VREG(60), VREG(61), VREG(62), VREG(63), \ 1144 /* VFP argument registers. */ \ 1145 VREG(15), VREG(14), VREG(13), VREG(12), \ 1146 VREG(11), VREG(10), VREG(9), VREG(8), \ 1147 VREG(7), VREG(6), VREG(5), VREG(4), \ 1148 VREG(3), VREG(2), VREG(1), VREG(0), \ 1149 /* VFP call-saved registers. */ \ 1150 VREG(16), VREG(17), VREG(18), VREG(19), \ 1151 VREG(20), VREG(21), VREG(22), VREG(23), \ 1152 VREG(24), VREG(25), VREG(26), VREG(27), \ 1153 VREG(28), VREG(29), VREG(30), VREG(31), \ 1154 /* IWMMX registers. */ \ 1155 WREG(0), WREG(1), WREG(2), WREG(3), \ 1156 WREG(4), WREG(5), WREG(6), WREG(7), \ 1157 WREG(8), WREG(9), WREG(10), WREG(11), \ 1158 WREG(12), WREG(13), WREG(14), WREG(15), \ 1159 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1160 /* Registers not for general use. */ \ 1161 CC_REGNUM, VFPCC_REGNUM, \ 1162 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1163 SP_REGNUM, PC_REGNUM \ 1164} 1165 1166/* Use different register alloc ordering for Thumb. */ 1167#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1168 1169/* Tell IRA to use the order we define rather than messing it up with its 1170 own cost calculations. */ 1171#define HONOR_REG_ALLOC_ORDER 1 1172 1173/* Interrupt functions can only use registers that have already been 1174 saved by the prologue, even if they would normally be 1175 call-clobbered. */ 1176#define HARD_REGNO_RENAME_OK(SRC, DST) \ 1177 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1178 df_regs_ever_live_p (DST)) 1179 1180/* Register and constant classes. */ 1181 1182/* Register classes. */ 1183enum reg_class 1184{ 1185 NO_REGS, 1186 LO_REGS, 1187 STACK_REG, 1188 BASE_REGS, 1189 HI_REGS, 1190 CALLER_SAVE_REGS, 1191 GENERAL_REGS, 1192 CORE_REGS, 1193 VFP_D0_D7_REGS, 1194 VFP_LO_REGS, 1195 VFP_HI_REGS, 1196 VFP_REGS, 1197 IWMMXT_REGS, 1198 IWMMXT_GR_REGS, 1199 CC_REG, 1200 VFPCC_REG, 1201 SFP_REG, 1202 AFP_REG, 1203 ALL_REGS, 1204 LIM_REG_CLASSES 1205}; 1206 1207#define N_REG_CLASSES (int) LIM_REG_CLASSES 1208 1209/* Give names of register classes as strings for dump file. */ 1210#define REG_CLASS_NAMES \ 1211{ \ 1212 "NO_REGS", \ 1213 "LO_REGS", \ 1214 "STACK_REG", \ 1215 "BASE_REGS", \ 1216 "HI_REGS", \ 1217 "CALLER_SAVE_REGS", \ 1218 "GENERAL_REGS", \ 1219 "CORE_REGS", \ 1220 "VFP_D0_D7_REGS", \ 1221 "VFP_LO_REGS", \ 1222 "VFP_HI_REGS", \ 1223 "VFP_REGS", \ 1224 "IWMMXT_REGS", \ 1225 "IWMMXT_GR_REGS", \ 1226 "CC_REG", \ 1227 "VFPCC_REG", \ 1228 "SFP_REG", \ 1229 "AFP_REG", \ 1230 "ALL_REGS" \ 1231} 1232 1233/* Define which registers fit in which classes. 1234 This is an initializer for a vector of HARD_REG_SET 1235 of length N_REG_CLASSES. */ 1236#define REG_CLASS_CONTENTS \ 1237{ \ 1238 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1239 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1240 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1241 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1242 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1243 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1244 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1245 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1246 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1247 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1248 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1249 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1250 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1251 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1252 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1253 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1254 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1255 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1256 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \ 1257} 1258 1259/* Any of the VFP register classes. */ 1260#define IS_VFP_CLASS(X) \ 1261 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1262 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1263 1264/* The same information, inverted: 1265 Return the class number of the smallest class containing 1266 reg number REGNO. This could be a conditional expression 1267 or could index an array. */ 1268#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1269 1270/* In VFPv1, VFP registers could only be accessed in the mode they 1271 were set, so subregs would be invalid there. However, we don't 1272 support VFPv1 at the moment, and the restriction was lifted in 1273 VFPv2. 1274 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in 1275 VFP registers in little-endian order. We can't describe that accurately to 1276 GCC, so avoid taking subregs of such values. 1277 The only exception is going from a 128-bit to a 64-bit type. In that case 1278 the data layout happens to be consistent for big-endian, so we explicitly allow 1279 that case. */ 1280#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1281 (TARGET_VFP && TARGET_BIG_END \ 1282 && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \ 1283 && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ 1284 || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ 1285 && reg_classes_intersect_p (VFP_REGS, (CLASS))) 1286 1287/* The class value for index registers, and the one for base regs. */ 1288#define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1289#define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1290 1291/* For the Thumb the high registers cannot be used as base registers 1292 when addressing quantities in QI or HI mode; if we don't know the 1293 mode, then we must be conservative. */ 1294#define MODE_BASE_REG_CLASS(MODE) \ 1295 (TARGET_32BIT ? CORE_REGS \ 1296 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1297 : LO_REGS) 1298 1299/* For Thumb we can not support SP+reg addressing, so we return LO_REGS 1300 instead of BASE_REGS. */ 1301#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1302 1303/* When this hook returns true for MODE, the compiler allows 1304 registers explicitly used in the rtl to be used as spill registers 1305 but prevents the compiler from extending the lifetime of these 1306 registers. */ 1307#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1308 arm_small_register_classes_for_mode_p 1309 1310/* Must leave BASE_REGS reloads alone */ 1311#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1312 (lra_in_progress ? NO_REGS \ 1313 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1314 ? ((true_regnum (X) == -1 ? LO_REGS \ 1315 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1316 : NO_REGS)) \ 1317 : NO_REGS)) 1318 1319#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1320 (lra_in_progress ? NO_REGS \ 1321 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1322 ? ((true_regnum (X) == -1 ? LO_REGS \ 1323 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1324 : NO_REGS)) \ 1325 : NO_REGS) 1326 1327/* Return the register class of a scratch register needed to copy IN into 1328 or out of a register in CLASS in MODE. If it can be done directly, 1329 NO_REGS is returned. */ 1330#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1331 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1332 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1333 && IS_VFP_CLASS (CLASS)) \ 1334 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1335 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1336 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1337 : TARGET_32BIT \ 1338 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1339 ? GENERAL_REGS : NO_REGS) \ 1340 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1341 1342/* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1343#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1344 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1345 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1346 && IS_VFP_CLASS (CLASS)) \ 1347 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1348 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1349 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1350 (TARGET_32BIT ? \ 1351 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1352 && CONSTANT_P (X)) \ 1353 ? GENERAL_REGS : \ 1354 (((MODE) == HImode && ! arm_arch4 \ 1355 && (MEM_P (X) \ 1356 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1357 && true_regnum (X) == -1))) \ 1358 ? GENERAL_REGS : NO_REGS) \ 1359 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1360 1361/* Try a machine-dependent way of reloading an illegitimate address 1362 operand. If we find one, push the reload and jump to WIN. This 1363 macro is used in only one place: `find_reloads_address' in reload.c. 1364 1365 For the ARM, we wish to handle large displacements off a base 1366 register by splitting the addend across a MOV and the mem insn. 1367 This can cut the number of reloads needed. */ 1368#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ 1369 do \ 1370 { \ 1371 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \ 1372 goto WIN; \ 1373 } \ 1374 while (0) 1375 1376/* XXX If an HImode FP+large_offset address is converted to an HImode 1377 SP+large_offset address, then reload won't know how to fix it. It sees 1378 only that SP isn't valid for HImode, and so reloads the SP into an index 1379 register, but the resulting address is still invalid because the offset 1380 is too big. We fix it here instead by reloading the entire address. */ 1381/* We could probably achieve better results by defining PROMOTE_MODE to help 1382 cope with the variances between the Thumb's signed and unsigned byte and 1383 halfword load instructions. */ 1384/* ??? This should be safe for thumb2, but we may be able to do better. */ 1385#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ 1386do { \ 1387 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ 1388 if (new_x) \ 1389 { \ 1390 X = new_x; \ 1391 goto WIN; \ 1392 } \ 1393} while (0) 1394 1395#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1396 if (TARGET_ARM) \ 1397 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ 1398 else \ 1399 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) 1400 1401/* Return the maximum number of consecutive registers 1402 needed to represent mode MODE in a register of class CLASS. 1403 ARM regs are UNITS_PER_WORD bits. 1404 FIXME: Is this true for iWMMX? */ 1405#define CLASS_MAX_NREGS(CLASS, MODE) \ 1406 (ARM_NUM_REGS (MODE)) 1407 1408/* If defined, gives a class of registers that cannot be used as the 1409 operand of a SUBREG that changes the mode of the object illegally. */ 1410 1411/* Stack layout; function entry, exit and calling. */ 1412 1413/* Define this if pushing a word on the stack 1414 makes the stack pointer a smaller address. */ 1415#define STACK_GROWS_DOWNWARD 1 1416 1417/* Define this to nonzero if the nominal address of the stack frame 1418 is at the high-address end of the local variables; 1419 that is, each additional local variable allocated 1420 goes at a more negative offset in the frame. */ 1421#define FRAME_GROWS_DOWNWARD 1 1422 1423/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1424 When present, it is one word in size, and sits at the top of the frame, 1425 between the soft frame pointer and either r7 or r11. 1426 1427 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1428 and only then if some outgoing arguments are passed on the stack. It would 1429 be tempting to also check whether the stack arguments are passed by indirect 1430 calls, but there seems to be no reason in principle why a post-reload pass 1431 couldn't convert a direct call into an indirect one. */ 1432#define CALLER_INTERWORKING_SLOT_SIZE \ 1433 (TARGET_CALLER_INTERWORKING \ 1434 && crtl->outgoing_args_size != 0 \ 1435 ? UNITS_PER_WORD : 0) 1436 1437/* Offset within stack frame to start allocating local variables at. 1438 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1439 first local allocated. Otherwise, it is the offset to the BEGINNING 1440 of the first local allocated. */ 1441#define STARTING_FRAME_OFFSET 0 1442 1443/* If we generate an insn to push BYTES bytes, 1444 this says how many the stack pointer really advances by. */ 1445/* The push insns do not do this rounding implicitly. 1446 So don't define this. */ 1447/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1448 1449/* Define this if the maximum size of all the outgoing args is to be 1450 accumulated and pushed during the prologue. The amount can be 1451 found in the variable crtl->outgoing_args_size. */ 1452#define ACCUMULATE_OUTGOING_ARGS 1 1453 1454/* Offset of first parameter from the argument pointer register value. */ 1455#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1456 1457/* Amount of memory needed for an untyped call to save all possible return 1458 registers. */ 1459#define APPLY_RESULT_SIZE arm_apply_result_size() 1460 1461/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1462 values must be in memory. On the ARM, they need only do so if larger 1463 than a word, or if they contain elements offset from zero in the struct. */ 1464#define DEFAULT_PCC_STRUCT_RETURN 0 1465 1466/* These bits describe the different types of function supported 1467 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1468 normal function and an interworked function, for example. Knowing the 1469 type of a function is important for determining its prologue and 1470 epilogue sequences. 1471 Note value 7 is currently unassigned. Also note that the interrupt 1472 function types all have bit 2 set, so that they can be tested for easily. 1473 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1474 machine_function structure is initialized (to zero) func_type will 1475 default to unknown. This will force the first use of arm_current_func_type 1476 to call arm_compute_func_type. */ 1477#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1478#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1479#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1480#define ARM_FT_ISR 4 /* An interrupt service routine. */ 1481#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1482#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1483 1484#define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1485 1486/* In addition functions can have several type modifiers, 1487 outlined by these bit masks: */ 1488#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1489#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1490#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1491#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1492#define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1493 1494/* Some macros to test these flags. */ 1495#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1496#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1497#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1498#define IS_NAKED(t) (t & ARM_FT_NAKED) 1499#define IS_NESTED(t) (t & ARM_FT_NESTED) 1500#define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1501 1502 1503/* Structure used to hold the function stack frame layout. Offsets are 1504 relative to the stack pointer on function entry. Positive offsets are 1505 in the direction of stack growth. 1506 Only soft_frame is used in thumb mode. */ 1507 1508typedef struct GTY(()) arm_stack_offsets 1509{ 1510 int saved_args; /* ARG_POINTER_REGNUM. */ 1511 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1512 int saved_regs; 1513 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1514 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1515 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1516 unsigned int saved_regs_mask; 1517} 1518arm_stack_offsets; 1519 1520#if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) 1521/* A C structure for machine-specific, per-function data. 1522 This is added to the cfun structure. */ 1523typedef struct GTY(()) machine_function 1524{ 1525 /* Additional stack adjustment in __builtin_eh_throw. */ 1526 rtx eh_epilogue_sp_ofs; 1527 /* Records if LR has to be saved for far jumps. */ 1528 int far_jump_used; 1529 /* Records if ARG_POINTER was ever live. */ 1530 int arg_pointer_live; 1531 /* Records if the save of LR has been eliminated. */ 1532 int lr_save_eliminated; 1533 /* The size of the stack frame. Only valid after reload. */ 1534 arm_stack_offsets stack_offsets; 1535 /* Records the type of the current function. */ 1536 unsigned long func_type; 1537 /* Record if the function has a variable argument list. */ 1538 int uses_anonymous_args; 1539 /* Records if sibcalls are blocked because an argument 1540 register is needed to preserve stack alignment. */ 1541 int sibcall_blocked; 1542 /* The PIC register for this function. This might be a pseudo. */ 1543 rtx pic_reg; 1544 /* Labels for per-function Thumb call-via stubs. One per potential calling 1545 register. We can never call via LR or PC. We can call via SP if a 1546 trampoline happens to be on the top of the stack. */ 1547 rtx call_via[14]; 1548 /* Set to 1 when a return insn is output, this means that the epilogue 1549 is not needed. */ 1550 int return_used_this_function; 1551 /* When outputting Thumb-1 code, record the last insn that provides 1552 information about condition codes, and the comparison operands. */ 1553 rtx thumb1_cc_insn; 1554 rtx thumb1_cc_op0; 1555 rtx thumb1_cc_op1; 1556 /* Also record the CC mode that is supported. */ 1557 machine_mode thumb1_cc_mode; 1558 /* Set to 1 after arm_reorg has started. */ 1559 int after_arm_reorg; 1560} 1561machine_function; 1562#endif 1563 1564/* As in the machine_function, a global set of call-via labels, for code 1565 that is in text_section. */ 1566extern GTY(()) rtx thumb_call_via_label[14]; 1567 1568/* The number of potential ways of assigning to a co-processor. */ 1569#define ARM_NUM_COPROC_SLOTS 1 1570 1571/* Enumeration of procedure calling standard variants. We don't really 1572 support all of these yet. */ 1573enum arm_pcs 1574{ 1575 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1576 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1577 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1578 /* This must be the last AAPCS variant. */ 1579 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1580 ARM_PCS_ATPCS, /* ATPCS. */ 1581 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1582 ARM_PCS_UNKNOWN 1583}; 1584 1585/* Default procedure calling standard of current compilation unit. */ 1586extern enum arm_pcs arm_pcs_default; 1587 1588#if !defined (USED_FOR_TARGET) 1589/* A C type for declaring a variable that is used as the first argument of 1590 `FUNCTION_ARG' and other related values. */ 1591typedef struct 1592{ 1593 /* This is the number of registers of arguments scanned so far. */ 1594 int nregs; 1595 /* This is the number of iWMMXt register arguments scanned so far. */ 1596 int iwmmxt_nregs; 1597 int named_count; 1598 int nargs; 1599 /* Which procedure call variant to use for this call. */ 1600 enum arm_pcs pcs_variant; 1601 1602 /* AAPCS related state tracking. */ 1603 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1604 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1605 this argument, or -1 if using core 1606 registers. */ 1607 int aapcs_ncrn; 1608 int aapcs_next_ncrn; 1609 rtx aapcs_reg; /* Register assigned to this argument. */ 1610 int aapcs_partial; /* How many bytes are passed in regs (if 1611 split between core regs and stack. 1612 Zero otherwise. */ 1613 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1614 int can_split; /* Argument can be split between core regs 1615 and the stack. */ 1616 /* Private data for tracking VFP register allocation */ 1617 unsigned aapcs_vfp_regs_free; 1618 unsigned aapcs_vfp_reg_alloc; 1619 int aapcs_vfp_rcount; 1620 MACHMODE aapcs_vfp_rmode; 1621} CUMULATIVE_ARGS; 1622#endif 1623 1624#define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1625 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) 1626 1627#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1628 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 1629 1630/* For AAPCS, padding should never be below the argument. For other ABIs, 1631 * mimic the default. */ 1632#define PAD_VARARGS_DOWN \ 1633 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1634 1635/* Initialize a variable CUM of type CUMULATIVE_ARGS 1636 for a call to a function whose data type is FNTYPE. 1637 For a library call, FNTYPE is 0. 1638 On the ARM, the offset starts at 0. */ 1639#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1640 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1641 1642/* 1 if N is a possible register number for function argument passing. 1643 On the ARM, r0-r3 are used to pass args. */ 1644#define FUNCTION_ARG_REGNO_P(REGNO) \ 1645 (IN_RANGE ((REGNO), 0, 3) \ 1646 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ 1647 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1648 || (TARGET_IWMMXT_ABI \ 1649 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1650 1651 1652/* If your target environment doesn't prefix user functions with an 1653 underscore, you may wish to re-define this to prevent any conflicts. */ 1654#ifndef ARM_MCOUNT_NAME 1655#define ARM_MCOUNT_NAME "*mcount" 1656#endif 1657 1658/* Call the function profiler with a given profile label. The Acorn 1659 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1660 On the ARM the full profile code will look like: 1661 .data 1662 LP1 1663 .word 0 1664 .text 1665 mov ip, lr 1666 bl mcount 1667 .word LP1 1668 1669 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1670 will output the .text section. 1671 1672 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1673 ``prof'' doesn't seem to mind about this! 1674 1675 Note - this version of the code is designed to work in both ARM and 1676 Thumb modes. */ 1677#ifndef ARM_FUNCTION_PROFILER 1678#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1679{ \ 1680 char temp[20]; \ 1681 rtx sym; \ 1682 \ 1683 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1684 IP_REGNUM, LR_REGNUM); \ 1685 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1686 fputc ('\n', STREAM); \ 1687 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1688 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1689 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1690} 1691#endif 1692 1693#ifdef THUMB_FUNCTION_PROFILER 1694#define FUNCTION_PROFILER(STREAM, LABELNO) \ 1695 if (TARGET_ARM) \ 1696 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1697 else \ 1698 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1699#else 1700#define FUNCTION_PROFILER(STREAM, LABELNO) \ 1701 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1702#endif 1703 1704/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1705 the stack pointer does not matter. The value is tested only in 1706 functions that have frame pointers. 1707 No definition is equivalent to always zero. 1708 1709 On the ARM, the function epilogue recovers the stack pointer from the 1710 frame. */ 1711#define EXIT_IGNORE_STACK 1 1712 1713#define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1714 1715/* Determine if the epilogue should be output as RTL. 1716 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1717#define USE_RETURN_INSN(ISCOND) \ 1718 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1719 1720/* Definitions for register eliminations. 1721 1722 This is an array of structures. Each structure initializes one pair 1723 of eliminable registers. The "from" register number is given first, 1724 followed by "to". Eliminations of the same "from" register are listed 1725 in order of preference. 1726 1727 We have two registers that can be eliminated on the ARM. First, the 1728 arg pointer register can often be eliminated in favor of the stack 1729 pointer register. Secondly, the pseudo frame pointer register can always 1730 be eliminated; it is replaced with either the stack or the real frame 1731 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1732 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1733 1734#define ELIMINABLE_REGS \ 1735{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1736 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1737 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1738 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1739 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1740 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1741 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1742 1743/* Define the offset between two registers, one to be eliminated, and the 1744 other its replacement, at the start of a routine. */ 1745#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1746 if (TARGET_ARM) \ 1747 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1748 else \ 1749 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1750 1751/* Special case handling of the location of arguments passed on the stack. */ 1752#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1753 1754/* Initialize data used by insn expanders. This is called from insn_emit, 1755 once for every function before code is generated. */ 1756#define INIT_EXPANDERS arm_init_expanders () 1757 1758/* Length in units of the trampoline for entering a nested function. */ 1759#define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1760 1761/* Alignment required for a trampoline in bits. */ 1762#define TRAMPOLINE_ALIGNMENT 32 1763 1764/* Addressing modes, and classification of registers for them. */ 1765#define HAVE_POST_INCREMENT 1 1766#define HAVE_PRE_INCREMENT TARGET_32BIT 1767#define HAVE_POST_DECREMENT TARGET_32BIT 1768#define HAVE_PRE_DECREMENT TARGET_32BIT 1769#define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1770#define HAVE_POST_MODIFY_DISP TARGET_32BIT 1771#define HAVE_PRE_MODIFY_REG TARGET_32BIT 1772#define HAVE_POST_MODIFY_REG TARGET_32BIT 1773 1774enum arm_auto_incmodes 1775 { 1776 ARM_POST_INC, 1777 ARM_PRE_INC, 1778 ARM_POST_DEC, 1779 ARM_PRE_DEC 1780 }; 1781 1782#define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1783 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1784#define USE_LOAD_POST_INCREMENT(mode) \ 1785 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1786#define USE_LOAD_PRE_INCREMENT(mode) \ 1787 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1788#define USE_LOAD_POST_DECREMENT(mode) \ 1789 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1790#define USE_LOAD_PRE_DECREMENT(mode) \ 1791 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1792 1793#define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1794#define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1795#define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1796#define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1797 1798/* Macros to check register numbers against specific register classes. */ 1799 1800/* These assume that REGNO is a hard or pseudo reg number. 1801 They give nonzero only if REGNO is a hard reg of the suitable class 1802 or a pseudo reg currently allocated to a suitable hard reg. 1803 Since they use reg_renumber, they are safe only once reg_renumber 1804 has been allocated, which happens in reginfo.c during register 1805 allocation. */ 1806#define TEST_REGNO(R, TEST, VALUE) \ 1807 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 1808 1809/* Don't allow the pc to be used. */ 1810#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1811 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1812 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1813 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1814 1815#define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1816 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1817 || (GET_MODE_SIZE (MODE) >= 4 \ 1818 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1819 1820#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1821 (TARGET_THUMB1 \ 1822 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1823 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1824 1825/* Nonzero if X can be the base register in a reg+reg addressing mode. 1826 For Thumb, we can not use SP + reg, so reject SP. */ 1827#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1828 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1829 1830/* For ARM code, we don't care about the mode, but for Thumb, the index 1831 must be suitable for use in a QImode load. */ 1832#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1833 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1834 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1835 1836/* Maximum number of registers that can appear in a valid memory address. 1837 Shifts in addresses can't be by a register. */ 1838#define MAX_REGS_PER_ADDRESS 2 1839 1840/* Recognize any constant value that is a valid address. */ 1841/* XXX We can address any constant, eventually... */ 1842/* ??? Should the TARGET_ARM here also apply to thumb2? */ 1843#define CONSTANT_ADDRESS_P(X) \ 1844 (GET_CODE (X) == SYMBOL_REF \ 1845 && (CONSTANT_POOL_ADDRESS_P (X) \ 1846 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1847 1848/* True if SYMBOL + OFFSET constants must refer to something within 1849 SYMBOL's section. */ 1850#define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1851 1852/* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1853#ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1854#define TARGET_DEFAULT_WORD_RELOCATIONS 0 1855#endif 1856 1857#ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1858#define SUBTARGET_NAME_ENCODING_LENGTHS 1859#endif 1860 1861/* This is a C fragment for the inside of a switch statement. 1862 Each case label should return the number of characters to 1863 be stripped from the start of a function's name, if that 1864 name starts with the indicated character. */ 1865#define ARM_NAME_ENCODING_LENGTHS \ 1866 case '*': return 1; \ 1867 SUBTARGET_NAME_ENCODING_LENGTHS 1868 1869/* This is how to output a reference to a user-level label named NAME. 1870 `assemble_name' uses this. */ 1871#undef ASM_OUTPUT_LABELREF 1872#define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1873 arm_asm_output_labelref (FILE, NAME) 1874 1875/* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1876#define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1877 if (TARGET_THUMB2) \ 1878 thumb2_asm_output_opcode (STREAM); 1879 1880/* The EABI specifies that constructors should go in .init_array. 1881 Other targets use .ctors for compatibility. */ 1882#ifndef ARM_EABI_CTORS_SECTION_OP 1883#define ARM_EABI_CTORS_SECTION_OP \ 1884 "\t.section\t.init_array,\"aw\",%init_array" 1885#endif 1886#ifndef ARM_EABI_DTORS_SECTION_OP 1887#define ARM_EABI_DTORS_SECTION_OP \ 1888 "\t.section\t.fini_array,\"aw\",%fini_array" 1889#endif 1890#define ARM_CTORS_SECTION_OP \ 1891 "\t.section\t.ctors,\"aw\",%progbits" 1892#define ARM_DTORS_SECTION_OP \ 1893 "\t.section\t.dtors,\"aw\",%progbits" 1894 1895/* Define CTORS_SECTION_ASM_OP. */ 1896#undef CTORS_SECTION_ASM_OP 1897#undef DTORS_SECTION_ASM_OP 1898#ifndef IN_LIBGCC2 1899# define CTORS_SECTION_ASM_OP \ 1900 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1901# define DTORS_SECTION_ASM_OP \ 1902 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1903#else /* !defined (IN_LIBGCC2) */ 1904/* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1905 so we cannot use the definition above. */ 1906# ifdef __ARM_EABI__ 1907/* The .ctors section is not part of the EABI, so we do not define 1908 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1909 from trying to use it. We do define it when doing normal 1910 compilation, as .init_array can be used instead of .ctors. */ 1911/* There is no need to emit begin or end markers when using 1912 init_array; the dynamic linker will compute the size of the 1913 array itself based on special symbols created by the static 1914 linker. However, we do need to arrange to set up 1915 exception-handling here. */ 1916# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1917# define CTOR_LIST_END /* empty */ 1918# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1919# define DTOR_LIST_END /* empty */ 1920# else /* !defined (__ARM_EABI__) */ 1921# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1922# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1923# endif /* !defined (__ARM_EABI__) */ 1924#endif /* !defined (IN_LIBCC2) */ 1925 1926/* True if the operating system can merge entities with vague linkage 1927 (e.g., symbols in COMDAT group) during dynamic linking. */ 1928#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1929#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1930#endif 1931 1932#define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1933 1934/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1935 and check its validity for a certain class. 1936 We have two alternate definitions for each of them. 1937 The usual definition accepts all pseudo regs; the other rejects 1938 them unless they have been allocated suitable hard regs. 1939 The symbol REG_OK_STRICT causes the latter definition to be used. 1940 Thumb-2 has the same restrictions as arm. */ 1941#ifndef REG_OK_STRICT 1942 1943#define ARM_REG_OK_FOR_BASE_P(X) \ 1944 (REGNO (X) <= LAST_ARM_REGNUM \ 1945 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1946 || REGNO (X) == FRAME_POINTER_REGNUM \ 1947 || REGNO (X) == ARG_POINTER_REGNUM) 1948 1949#define ARM_REG_OK_FOR_INDEX_P(X) \ 1950 ((REGNO (X) <= LAST_ARM_REGNUM \ 1951 && REGNO (X) != STACK_POINTER_REGNUM) \ 1952 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1953 || REGNO (X) == FRAME_POINTER_REGNUM \ 1954 || REGNO (X) == ARG_POINTER_REGNUM) 1955 1956#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1957 (REGNO (X) <= LAST_LO_REGNUM \ 1958 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1959 || (GET_MODE_SIZE (MODE) >= 4 \ 1960 && (REGNO (X) == STACK_POINTER_REGNUM \ 1961 || (X) == hard_frame_pointer_rtx \ 1962 || (X) == arg_pointer_rtx))) 1963 1964#define REG_STRICT_P 0 1965 1966#else /* REG_OK_STRICT */ 1967 1968#define ARM_REG_OK_FOR_BASE_P(X) \ 1969 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1970 1971#define ARM_REG_OK_FOR_INDEX_P(X) \ 1972 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 1973 1974#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1975 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1976 1977#define REG_STRICT_P 1 1978 1979#endif /* REG_OK_STRICT */ 1980 1981/* Now define some helpers in terms of the above. */ 1982 1983#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1984 (TARGET_THUMB1 \ 1985 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 1986 : ARM_REG_OK_FOR_BASE_P (X)) 1987 1988/* For 16-bit Thumb, a valid index register is anything that can be used in 1989 a byte load instruction. */ 1990#define THUMB1_REG_OK_FOR_INDEX_P(X) \ 1991 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 1992 1993/* Nonzero if X is a hard reg that can be used as an index 1994 or if it is a pseudo reg. On the Thumb, the stack pointer 1995 is not suitable. */ 1996#define REG_OK_FOR_INDEX_P(X) \ 1997 (TARGET_THUMB1 \ 1998 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 1999 : ARM_REG_OK_FOR_INDEX_P (X)) 2000 2001/* Nonzero if X can be the base register in a reg+reg addressing mode. 2002 For Thumb, we can not use SP + reg, so reject SP. */ 2003#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 2004 REG_OK_FOR_INDEX_P (X) 2005 2006#define ARM_BASE_REGISTER_RTX_P(X) \ 2007 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 2008 2009#define ARM_INDEX_REGISTER_RTX_P(X) \ 2010 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 2011 2012/* Specify the machine mode that this machine uses 2013 for the index in the tablejump instruction. */ 2014#define CASE_VECTOR_MODE Pmode 2015 2016#define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ 2017 || (TARGET_THUMB1 \ 2018 && (optimize_size || flag_pic))) 2019 2020#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 2021 (TARGET_THUMB1 \ 2022 ? (min >= 0 && max < 512 \ 2023 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 2024 : min >= -256 && max < 256 \ 2025 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 2026 : min >= 0 && max < 8192 \ 2027 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 2028 : min >= -4096 && max < 4096 \ 2029 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 2030 : SImode) \ 2031 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 2032 : (max >= 0x200) ? HImode \ 2033 : QImode)) 2034 2035/* signed 'char' is most compatible, but RISC OS wants it unsigned. 2036 unsigned is probably best, but may break some code. */ 2037#ifndef DEFAULT_SIGNED_CHAR 2038#define DEFAULT_SIGNED_CHAR 0 2039#endif 2040 2041/* Max number of bytes we can move from memory to memory 2042 in one reasonably fast instruction. */ 2043#define MOVE_MAX 4 2044 2045#undef MOVE_RATIO 2046#define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2047 2048/* Define if operations between registers always perform the operation 2049 on the full register even if a narrower mode is specified. */ 2050#define WORD_REGISTER_OPERATIONS 2051 2052/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2053 will either zero-extend or sign-extend. The value of this macro should 2054 be the code that says which one of the two operations is implicitly 2055 done, UNKNOWN if none. */ 2056#define LOAD_EXTEND_OP(MODE) \ 2057 (TARGET_THUMB ? ZERO_EXTEND : \ 2058 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2059 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2060 2061/* Nonzero if access to memory by bytes is slow and undesirable. */ 2062#define SLOW_BYTE_ACCESS 0 2063 2064#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 2065 2066/* Immediate shift counts are truncated by the output routines (or was it 2067 the assembler?). Shift counts in a register are truncated by ARM. Note 2068 that the native compiler puts too large (> 32) immediate shift counts 2069 into a register and shifts by the register, letting the ARM decide what 2070 to do instead of doing that itself. */ 2071/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2072 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2073 On the arm, Y in a register is used modulo 256 for the shift. Only for 2074 rotates is modulo 32 used. */ 2075/* #define SHIFT_COUNT_TRUNCATED 1 */ 2076 2077/* All integers have the same format so truncation is easy. */ 2078#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2079 2080/* Calling from registers is a massive pain. */ 2081#define NO_FUNCTION_CSE 1 2082 2083/* The machine modes of pointers and functions */ 2084#define Pmode SImode 2085#define FUNCTION_MODE Pmode 2086 2087#define ARM_FRAME_RTX(X) \ 2088 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2089 || (X) == arg_pointer_rtx) 2090 2091/* Try to generate sequences that don't involve branches, we can then use 2092 conditional instructions. */ 2093#define BRANCH_COST(speed_p, predictable_p) \ 2094 (current_tune->branch_cost (speed_p, predictable_p)) 2095 2096/* False if short circuit operation is preferred. */ 2097#define LOGICAL_OP_NON_SHORT_CIRCUIT \ 2098 ((optimize_size) \ 2099 ? (TARGET_THUMB ? false : true) \ 2100 : (current_tune->logical_op_non_short_circuit[TARGET_ARM])) 2101 2102 2103/* Position Independent Code. */ 2104/* We decide which register to use based on the compilation options and 2105 the assembler in use; this is more general than the APCS restriction of 2106 using sb (r9) all the time. */ 2107extern unsigned arm_pic_register; 2108 2109/* The register number of the register used to address a table of static 2110 data addresses in memory. */ 2111#define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2112 2113/* We can't directly access anything that contains a symbol, 2114 nor can we indirect via the constant pool. One exception is 2115 UNSPEC_TLS, which is always PIC. */ 2116#define LEGITIMATE_PIC_OPERAND_P(X) \ 2117 (!(symbol_mentioned_p (X) \ 2118 || label_mentioned_p (X) \ 2119 || (GET_CODE (X) == SYMBOL_REF \ 2120 && CONSTANT_POOL_ADDRESS_P (X) \ 2121 && (symbol_mentioned_p (get_pool_constant (X)) \ 2122 || label_mentioned_p (get_pool_constant (X))))) \ 2123 || tls_mentioned_p (X)) 2124 2125/* We need to know when we are making a constant pool; this determines 2126 whether data needs to be in the GOT or can be referenced via a GOT 2127 offset. */ 2128extern int making_const_table; 2129 2130/* Handle pragmas for compatibility with Intel's compilers. */ 2131/* Also abuse this to register additional C specific EABI attributes. */ 2132#define REGISTER_TARGET_PRAGMAS() do { \ 2133 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2134 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2135 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2136 arm_lang_object_attributes_init(); \ 2137} while (0) 2138 2139/* Condition code information. */ 2140/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2141 return the mode to be used for the comparison. */ 2142 2143#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2144 2145#define REVERSIBLE_CC_MODE(MODE) 1 2146 2147#define REVERSE_CONDITION(CODE,MODE) \ 2148 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2149 ? reverse_condition_maybe_unordered (code) \ 2150 : reverse_condition (code)) 2151 2152#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2153 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2154#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2155 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2156 2157#define CC_STATUS_INIT \ 2158 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2159 2160#undef ASM_APP_ON 2161#define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ 2162 "\t.syntax divided\n") 2163 2164#undef ASM_APP_OFF 2165#define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax divided\n" : \ 2166 "\t.thumb\n\t.syntax unified\n") 2167 2168/* Output a push or a pop instruction (only used when profiling). 2169 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2170 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2171 that r7 isn't used by the function profiler, so we can use it as a 2172 scratch reg. WARNING: This isn't safe in the general case! It may be 2173 sensitive to future changes in final.c:profile_function. */ 2174#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2175 do \ 2176 { \ 2177 if (TARGET_ARM) \ 2178 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ 2179 STACK_POINTER_REGNUM, REGNO); \ 2180 else if (TARGET_THUMB1 \ 2181 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2182 { \ 2183 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2184 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2185 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2186 } \ 2187 else \ 2188 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2189 } while (0) 2190 2191 2192/* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2193#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2194 do \ 2195 { \ 2196 if (TARGET_ARM) \ 2197 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ 2198 STACK_POINTER_REGNUM, REGNO); \ 2199 else if (TARGET_THUMB1 \ 2200 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2201 { \ 2202 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2203 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2204 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2205 } \ 2206 else \ 2207 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2208 } while (0) 2209 2210#define ADDR_VEC_ALIGN(JUMPTABLE) \ 2211 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2212 2213/* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2214 default alignment from elfos.h. */ 2215#undef ASM_OUTPUT_BEFORE_CASE_LABEL 2216#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2217 2218#define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2219 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2220 ? 1 : 0) 2221 2222#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2223 do \ 2224 { \ 2225 if (TARGET_THUMB) \ 2226 { \ 2227 if (is_called_in_ARM_mode (DECL) \ 2228 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ 2229 && cfun->is_thunk)) \ 2230 fprintf (STREAM, "\t.code 32\n") ; \ 2231 else if (TARGET_THUMB1) \ 2232 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ 2233 else \ 2234 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ 2235 } \ 2236 if (TARGET_POKE_FUNCTION_NAME) \ 2237 arm_poke_function_name (STREAM, (const char *) NAME); \ 2238 } \ 2239 while (0) 2240 2241/* For aliases of functions we use .thumb_set instead. */ 2242#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2243 do \ 2244 { \ 2245 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2246 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2247 \ 2248 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2249 { \ 2250 fprintf (FILE, "\t.thumb_set "); \ 2251 assemble_name (FILE, LABEL1); \ 2252 fprintf (FILE, ","); \ 2253 assemble_name (FILE, LABEL2); \ 2254 fprintf (FILE, "\n"); \ 2255 } \ 2256 else \ 2257 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2258 } \ 2259 while (0) 2260 2261#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2262/* To support -falign-* switches we need to use .p2align so 2263 that alignment directives in code sections will be padded 2264 with no-op instructions, rather than zeroes. */ 2265#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2266 if ((LOG) != 0) \ 2267 { \ 2268 if ((MAX_SKIP) == 0) \ 2269 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2270 else \ 2271 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2272 (int) (LOG), (int) (MAX_SKIP)); \ 2273 } 2274#endif 2275 2276/* Add two bytes to the length of conditionally executed Thumb-2 2277 instructions for the IT instruction. */ 2278#define ADJUST_INSN_LENGTH(insn, length) \ 2279 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2280 length += 2; 2281 2282/* Only perform branch elimination (by making instructions conditional) if 2283 we're optimizing. For Thumb-2 check if any IT instructions need 2284 outputting. */ 2285#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2286 if (TARGET_ARM && optimize) \ 2287 arm_final_prescan_insn (INSN); \ 2288 else if (TARGET_THUMB2) \ 2289 thumb2_final_prescan_insn (INSN); \ 2290 else if (TARGET_THUMB1) \ 2291 thumb1_final_prescan_insn (INSN) 2292 2293#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2294 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2295 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2296 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2297 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2298 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2299 : 0)))) 2300 2301/* A C expression whose value is RTL representing the value of the return 2302 address for the frame COUNT steps up from the current frame. */ 2303 2304#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2305 arm_return_addr (COUNT, FRAME) 2306 2307/* Mask of the bits in the PC that contain the real return address 2308 when running in 26-bit mode. */ 2309#define RETURN_ADDR_MASK26 (0x03fffffc) 2310 2311/* Pick up the return address upon entry to a procedure. Used for 2312 dwarf2 unwind information. This also enables the table driven 2313 mechanism. */ 2314#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2315#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2316 2317/* Used to mask out junk bits from the return address, such as 2318 processor state, interrupt status, condition codes and the like. */ 2319#define MASK_RETURN_ADDR \ 2320 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2321 in 26 bit mode, the condition codes must be masked out of the \ 2322 return address. This does not apply to ARM6 and later processors \ 2323 when running in 32 bit mode. */ \ 2324 ((arm_arch4 || TARGET_THUMB) \ 2325 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2326 : arm_gen_return_addr_mask ()) 2327 2328 2329/* Do not emit .note.GNU-stack by default. */ 2330#ifndef NEED_INDICATE_EXEC_STACK 2331#define NEED_INDICATE_EXEC_STACK 0 2332#endif 2333 2334#define TARGET_ARM_ARCH \ 2335 (arm_base_arch) \ 2336 2337#define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2) 2338#define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2) 2339 2340/* The highest Thumb instruction set version supported by the chip. */ 2341#define TARGET_ARM_ARCH_ISA_THUMB \ 2342 (arm_arch_thumb2 ? 2 \ 2343 : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0)) 2344 2345/* Expands to an upper-case char of the target's architectural 2346 profile. */ 2347#define TARGET_ARM_ARCH_PROFILE \ 2348 (!arm_arch_notm \ 2349 ? 'M' \ 2350 : (arm_arch7 \ 2351 ? (strlen (arm_arch_name) >=3 \ 2352 ? (arm_arch_name[strlen (arm_arch_name) - 3]) \ 2353 : 0) \ 2354 : 0)) 2355 2356/* Bit-field indicating what size LDREX/STREX loads/stores are available. 2357 Bit 0 for bytes, up to bit 3 for double-words. */ 2358#define TARGET_ARM_FEATURE_LDREX \ 2359 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2360 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2361 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2362 2363/* Set as a bit mask indicating the available widths of hardware floating 2364 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2365 32-bit support, bit 3 indicates 64-bit support. */ 2366#define TARGET_ARM_FP \ 2367 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ 2368 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ 2369 : 0) 2370 2371 2372/* Set as a bit mask indicating the available widths of floating point 2373 types for hardware NEON floating point. This is the same as 2374 TARGET_ARM_FP without the 64-bit bit set. */ 2375#define TARGET_NEON_FP \ 2376 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ 2377 : 0) 2378 2379/* The maximum number of parallel loads or stores we support in an ldm/stm 2380 instruction. */ 2381#define MAX_LDM_STM_OPS 4 2382 2383#define BIG_LITTLE_SPEC \ 2384 " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}" 2385 2386extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2387#define BIG_LITTLE_CPU_SPEC_FUNCTIONS \ 2388 { "rewrite_mcpu", arm_rewrite_mcpu }, 2389 2390#define ASM_CPU_SPEC \ 2391 " %{mcpu=generic-*:-march=%*;" \ 2392 " :%{march=*:-march=%*}}" \ 2393 BIG_LITTLE_SPEC 2394 2395/* -mcpu=native handling only makes sense with compiler running on 2396 an ARM chip. */ 2397#if defined(__arm__) 2398extern const char *host_detect_local_cpu (int argc, const char **argv); 2399# define EXTRA_SPEC_FUNCTIONS \ 2400 { "local_cpu_detect", host_detect_local_cpu }, \ 2401 BIG_LITTLE_CPU_SPEC_FUNCTIONS 2402 2403# define MCPU_MTUNE_NATIVE_SPECS \ 2404 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2405 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2406 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2407#else 2408# define MCPU_MTUNE_NATIVE_SPECS "" 2409# define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS 2410#endif 2411 2412#define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS 2413#define TARGET_SUPPORTS_WIDE_INT 1 2414#endif /* ! GCC_ARM_H */ 2415