1#objdump: -dr --prefix-addresses --show-raw-insn
2#name: MIPS64r6 n32 instructions
3#as: -n32
4#source: r6-64.s
5
6# Check MIPSR6 64 instructions
7
8.*: +file format .*mips.*
9
10Disassembly of section .text:
110+0000 <[^>]*> 0064109c 	dmul	v0,v1,a0
120+0004 <[^>]*> 006410dc 	dmuh	v0,v1,a0
130+0008 <[^>]*> 0064109e 	ddiv	v0,v1,a0
140+000c <[^>]*> 0064109d 	dmulu	v0,v1,a0
150+0010 <[^>]*> 006410dd 	dmuhu	v0,v1,a0
160+0014 <[^>]*> 006410de 	dmod	v0,v1,a0
170+0018 <[^>]*> 0064109f 	ddivu	v0,v1,a0
180+001c <[^>]*> 006410df 	dmodu	v0,v1,a0
190+0020 <[^>]*> 00641015 	dlsa	v0,v1,a0,0x1
200+0024 <[^>]*> 006410d5 	dlsa	v0,v1,a0,0x4
210+0028 <[^>]*> 00601052 	dclz	v0,v1
220+002c <[^>]*> 00601053 	dclo	v0,v1
230+0030 <[^>]*> 7c628037 	lld	v0,-256\(v1\)
240+0034 <[^>]*> 7c627fb7 	lld	v0,255\(v1\)
250+0038 <[^>]*> 7c628027 	scd	v0,-256\(v1\)
260+003c <[^>]*> 7c627fa7 	scd	v0,255\(v1\)
270+0040 <[^>]*> 7c432224 	dalign	a0,v0,v1,0
280+0044 <[^>]*> 7c432264 	dalign	a0,v0,v1,1
290+0048 <[^>]*> 7c4322a4 	dalign	a0,v0,v1,2
300+004c <[^>]*> 7c4322e4 	dalign	a0,v0,v1,3
310+0050 <[^>]*> 7c432324 	dalign	a0,v0,v1,4
320+0054 <[^>]*> 7c432364 	dalign	a0,v0,v1,5
330+0058 <[^>]*> 7c4323a4 	dalign	a0,v0,v1,6
340+005c <[^>]*> 7c4323e4 	dalign	a0,v0,v1,7
350+0060 <[^>]*> 7c022024 	dbitswap	a0,v0
360+0064 <[^>]*> 7443ffff 	daui	v1,v0,0xffff
370+0068 <[^>]*> 0466ffff 	dahi	v1,v1,0xffff
380+006c <[^>]*> 047effff 	dati	v1,v1,0xffff
390+0070 <[^>]*> ec900000 	lwupc	a0,00000070 <[^>]*>
40[	]*70: R_MIPS_PC19_S2	\.L1.1
410+0074 <[^>]*> ec900000 	lwupc	a0,00000074 <[^>]*>
42[	]*74: R_MIPS_PC19_S2	L0.-0x100000
430+0078 <[^>]*> ec900000 	lwupc	a0,00000078 <[^>]*>
44[	]*78: R_MIPS_PC19_S2	L0.+0xffffc
450+007c <[^>]*> ec940000 	lwupc	a0,fff0007c <[^>]*>
460+0080 <[^>]*> ec93ffff 	lwupc	a0,0010007c <[^>]*>
470+0084 <[^>]*> ec980000 	ldpc	a0,00000080 <[^>]*>
48[	]*84: R_MIPS_PC18_S3	\.L1.1
490+0088 <[^>]*> ec980000 	ldpc	a0,00000088 <[^>]*>
50[	]*88: R_MIPS_PC18_S3	\.L1.1
510+008c <[^>]*> 00000000 	nop
520+0090 <[^>]*> ec980000 	ldpc	a0,00000090 <[^>]*>
53[	]*90: R_MIPS_PC18_S3	\.L3.1-0x100000
540+0094 <[^>]*> ec980000 	ldpc	a0,00000090 <[^>]*>
55[	]*94: R_MIPS_PC18_S3	\.L3.1-0x100000
560+0098 <[^>]*> ec980000 	ldpc	a0,00000098 <[^>]*>
57[	]*98: R_MIPS_PC18_S3	\.L3.2\+0xffff8
580+009c <[^>]*> ec980000 	ldpc	a0,00000098 <[^>]*>
59[	]*9c: R_MIPS_PC18_S3	\.L3.2\+0xffff8
600+00a0 <[^>]*> ec9a0000 	ldpc	a0,fff000a0 <[^>]*>
610+00a4 <[^>]*> ec9a0000 	ldpc	a0,fff000a0 <[^>]*>
620+00a8 <[^>]*> ec99ffff 	ldpc	a0,001000a0 <[^>]*>
630+00ac <[^>]*> ec99ffff 	ldpc	a0,001000a0 <[^>]*>
64	\.\.\.
65