1#objdump: -dr --prefix-addresses --show-raw-insn
2#name: MIPS ISA override code generation
3#as: -32
4#source: isa-override-1.s
5
6.*: +file format .*mips.*
7
8Disassembly of section \.text:
9[0-9a-f]+ <[^>]*> 8c820000 	lw	v0,0\(a0\)
10[0-9a-f]+ <[^>]*> 8c830004 	lw	v1,4\(a0\)
11[0-9a-f]+ <[^>]*> 3c0189ab 	lui	at,0x89ab
12[0-9a-f]+ <[^>]*> 00411025 	or	v0,v0,at
13[0-9a-f]+ <[^>]*> d4820000 	ldc1	\$f2,0\(a0\)
14[0-9a-f]+ <[^>]*> 3c013ff0 	lui	at,0x3ff0
15[0-9a-f]+ <[^>]*> 44e11000 	mthc1	at,\$f2
16[0-9a-f]+ <[^>]*> 3c0189ab 	lui	at,0x89ab
17[0-9a-f]+ <[^>]*> 44811000 	mtc1	at,\$f2
18[0-9a-f]+ <[^>]*> dc820000 	ld	v0,0\(a0\)
19[0-9a-f]+ <[^>]*> 340189ab 	li	at,0x89ab
20[0-9a-f]+ <[^>]*> 00010c38 	dsll	at,at,0x10
21[0-9a-f]+ <[^>]*> 00411025 	or	v0,v0,at
22[0-9a-f]+ <[^>]*> 3c029000 	lui	v0,0x9000
23[0-9a-f]+ <[^>]*> 00021438 	dsll	v0,v0,0x10
24[0-9a-f]+ <[^>]*> 34428000 	ori	v0,v0,0x8000
25[0-9a-f]+ <[^>]*> 00021438 	dsll	v0,v0,0x10
26[0-9a-f]+ <[^>]*> d4820000 	ldc1	\$f2,0\(a0\)
27[0-9a-f]+ <[^>]*> 3c013ff0 	lui	at,0x3ff0
28[0-9a-f]+ <[^>]*> 00010c38 	dsll	at,at,0x10
29[0-9a-f]+ <[^>]*> 342189ab 	ori	at,at,0x89ab
30[0-9a-f]+ <[^>]*> 00010c38 	dsll	at,at,0x10
31[0-9a-f]+ <[^>]*> 44a11000 	dmtc1	at,\$f2
32[0-9a-f]+ <[^>]*> 8c820000 	lw	v0,0\(a0\)
33[0-9a-f]+ <[^>]*> 8c830004 	lw	v1,4\(a0\)
34[0-9a-f]+ <[^>]*> 3c0189ab 	lui	at,0x89ab
35[0-9a-f]+ <[^>]*> 00411025 	or	v0,v0,at
36[0-9a-f]+ <[^>]*> d4820000 	ldc1	\$f2,0\(a0\)
37[0-9a-f]+ <[^>]*> 3c013ff0 	lui	at,0x3ff0
38[0-9a-f]+ <[^>]*> 44e11000 	mthc1	at,\$f2
39[0-9a-f]+ <[^>]*> 3c0189ab 	lui	at,0x89ab
40[0-9a-f]+ <[^>]*> 44811000 	mtc1	at,\$f2
41[0-9a-f]+ <[^>]*> 8c820000 	lw	v0,0\(a0\)
42[0-9a-f]+ <[^>]*> 8c830004 	lw	v1,4\(a0\)
43[0-9a-f]+ <[^>]*> 3c0189ab 	lui	at,0x89ab
44[0-9a-f]+ <[^>]*> 00411025 	or	v0,v0,at
45[0-9a-f]+ <[^>]*> d4820000 	ldc1	\$f2,0\(a0\)
46[0-9a-f]+ <[^>]*> 3c013ff0 	lui	at,0x3ff0
47[0-9a-f]+ <[^>]*> 44e11000 	mthc1	at,\$f2
48[0-9a-f]+ <[^>]*> 3c0189ab 	lui	at,0x89ab
49[0-9a-f]+ <[^>]*> 44811000 	mtc1	at,\$f2
50	\.\.\.
51