1#objdump: -dr --prefix-addresses --show-raw-insn 2#name: MIPS MIPS32 instructions 3#source: mips32.s 4#as: -32 5 6# Check MIPS32 instruction assembly (microMIPS). 7 8.*: +file format .*mips.* 9 10Disassembly of section \.text: 11[0-9a-f]+ <[^>]*> 0022 4b3c clo at,v0 12[0-9a-f]+ <[^>]*> 0064 5b3c clz v1,a0 13[0-9a-f]+ <[^>]*> 00c5 cb3c madd a1,a2 14[0-9a-f]+ <[^>]*> 0107 db3c maddu a3,t0 15[0-9a-f]+ <[^>]*> 0149 eb3c msub t1,t2 16[0-9a-f]+ <[^>]*> 018b fb3c msubu t3,t4 17[0-9a-f]+ <[^>]*> 01ee 6a10 mul t5,t6,t7 18[0-9a-f]+ <[^>]*> 6090 2000 pref 0x4,0\(s0\) 19[0-9a-f]+ <[^>]*> 6091 27ff pref 0x4,2047\(s1\) 20[0-9a-f]+ <[^>]*> 6092 2800 pref 0x4,-2048\(s2\) 21[0-9a-f]+ <[^>]*> 0000 0800 ssnop 22[0-9a-f]+ <[^>]*> 20a1 6000 cache 0x5,0\(at\) 23[0-9a-f]+ <[^>]*> 20a2 67ff cache 0x5,2047\(v0\) 24[0-9a-f]+ <[^>]*> 20a3 6800 cache 0x5,-2048\(v1\) 25[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000 26[0-9a-f]+ <[^>]*> 0081 0950 addu at,at,a0 27[0-9a-f]+ <[^>]*> 20a1 6000 cache 0x5,0\(at\) 28[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768 29[0-9a-f]+ <[^>]*> 00a1 0950 addu at,at,a1 30[0-9a-f]+ <[^>]*> 20a1 6fff cache 0x5,-1\(at\) 31[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000 32[0-9a-f]+ <[^>]*> 20a1 6000 cache 0x5,0\(at\) 33[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768 34[0-9a-f]+ <[^>]*> 20a1 6fff cache 0x5,-1\(at\) 35[0-9a-f]+ <[^>]*> 0000 f37c eret 36[0-9a-f]+ <[^>]*> 0000 037c tlbp 37[0-9a-f]+ <[^>]*> 0000 137c tlbr 38[0-9a-f]+ <[^>]*> 0000 237c tlbwi 39[0-9a-f]+ <[^>]*> 0000 337c tlbwr 40[0-9a-f]+ <[^>]*> 0000 937c wait 41[0-9a-f]+ <[^>]*> 0000 937c wait 42[0-9a-f]+ <[^>]*> 0345 937c wait 0x345 43[0-9a-f]+ <[^>]*> 4680 break 44[0-9a-f]+ <[^>]*> 4680 break 45[0-9a-f]+ <[^>]*> 0345 0007 break 0x345 46[0-9a-f]+ <[^>]*> 0048 d147 break 0x48,0x345 47[0-9a-f]+ <[^>]*> 46c0 sdbbp 48[0-9a-f]+ <[^>]*> 46c0 sdbbp 49[0-9a-f]+ <[^>]*> 0345 db7c sdbbp 0x345 50 \.\.\. 51