1// Copyright 2017 The Fuchsia Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#pragma once 6 7 8//Fields of command register 9 10#define SDHCI_CMD_IDX(c) ((c) << 24) 11#define SDHCI_RESP_MASK (0x3 << 16) 12#define SDHCI_CMD_RESP_LEN_EMPTY (0x0 << 16) 13#define SDHCI_CMD_RESP_LEN_136 (0x1 << 16) 14#define SDHCI_CMD_RESP_LEN_48 (0x2 << 16) 15#define SDHCI_CMD_RESP_LEN_48B (0x3 << 16) 16 17#define SDHCI_CMD_RESP_CRC_CHECK (0x1 << 19) 18#define SDHCI_CMD_RESP_CMD_IDX_CHECK (0x1 << 20) 19#define SDHCI_CMD_RESP_DATA_PRESENT (0x1 << 21) 20 21#define SDHCI_CMD_TYPE_NORMAL (0x0 << 22) 22#define SDHCI_CMD_TYPE_SUSPEND (0x1 << 22) 23#define SDHCI_CMD_TYPE_RESUME (0x2 << 22) 24#define SDHCI_CMD_TYPE_ABORT (0x3 << 22) 25 26#define SDHCI_CMD_DMA_EN (1 << 0) 27#define SDHCI_CMD_BLKCNT_EN (1 << 1) 28#define SDHCI_CMD_AUTO12 (1 << 2) 29#define SDHCI_CMD_AUTO23 (2 << 2) 30#define SDHCI_CMD_READ (1 << 4) 31#define SDHCI_CMD_MULTI_BLK (1 << 5) 32 33 34typedef struct sdhci_regs { 35 uint32_t arg2; // 00h 36 uint32_t blkcntsiz; // 04h 37 uint32_t arg1; // 08h 38 uint32_t cmd; // 0Ch 39#define SDHCI_XFERMODE_DMA_ENABLE (1 << 0) 40 41 uint32_t resp0; // 10h 42 uint32_t resp1; // 14h 43 uint32_t resp2; // 18h 44 uint32_t resp3; // 1Ch 45 uint32_t data; // 20h 46 uint32_t state; // 24h 47#define SDHCI_STATE_CMD_INHIBIT (1 << 0) 48#define SDHCI_STATE_DAT_INHIBIT (1 << 1) 49#define SDHCI_STATE_DAT_LINE_ACTIVE (1 << 2) 50#define SDHCI_STATE_RETUNING_REQUEST (1 << 3) 51#define SDHCI_STATE_WRITE_TRANSFER_ACTIVE (1 << 8) 52#define SDHCI_STATE_READ_TRANSFER_ACTIVE (1 << 9) 53#define SDHCI_STATE_BUFFER_WRITE_ENABLE (1 << 10) 54#define SDHCI_STATE_BUFFER_READ_ENABLE (1 << 11) 55#define SDHCI_STATE_CARD_INSERTED (1 << 16) 56#define SDHCI_STATE_CARD_STATE_STABLE (1 << 17) 57#define SDHCI_STATE_CARD_DETECT_PIN_LEVEL (1 << 18) 58#define SDHCI_STATE_WRITE_PROTECT (1 << 19) 59#define SDHCI_STATE_CMD_LINE_SIGNAL_LVL (1 << 24) 60 61 uint32_t ctrl0; // 28h 62#define SDHCI_HOSTCTRL_LED_ON (1 << 0) 63#define SDHCI_HOSTCTRL_FOUR_BIT_BUS_WIDTH (1 << 1) 64#define SDHCI_HOSTCTRL_HIGHSPEED_ENABLE (1 << 2) 65#define SDHCI_HOSTCTRL_DMA_SELECT_ADMA2 (3 << 3) 66#define SDHCI_HOSTCTRL_EXT_DATA_WIDTH (1 << 5) 67#define SDHCI_PWRCTRL_SD_BUS_POWER (1 << 8) 68#define SDHCI_PWRCTRL_SD_BUS_VOLTAGE_MASK (7 << 9) 69#define SDHCI_PWRCTRL_SD_BUS_VOLTAGE_3P3V (7 << 9) 70#define SDHCI_PWRCTRL_SD_BUS_VOLTAGE_3P0V (6 << 9) 71#define SDHCI_PWRCTRL_SD_BUS_VOLTAGE_1P8V (5 << 9) 72#define SDHCI_EMMC_HW_RESET (1 << 12) 73 74 uint32_t ctrl1; // 2Ch 75#define SDHCI_INTERNAL_CLOCK_ENABLE (1 << 0) 76#define SDHCI_INTERNAL_CLOCK_STABLE (1 << 1) 77#define SDHCI_SD_CLOCK_ENABLE (1 << 2) 78#define SDHCI_PROGRAMMABLE_CLOCK_GENERATOR (1 << 5) 79#define SDHCI_SOFTWARE_RESET_ALL (1 << 24) 80#define SDHCI_SOFTWARE_RESET_CMD (1 << 25) 81#define SDHCI_SOFTWARE_RESET_DAT (1 << 26) 82 83 uint32_t irq; // 30h 84 uint32_t irqmsk; // 34h 85 uint32_t irqen; // 38h 86#define SDHCI_IRQ_CMD_CPLT (1 << 0) 87#define SDHCI_IRQ_XFER_CPLT (1 << 1) 88#define SDHCI_IRQ_BLK_GAP_EVT (1 << 2) 89#define SDHCI_IRQ_DMA (1 << 3) 90#define SDHCI_IRQ_BUFF_WRITE_READY (1 << 4) 91#define SDHCI_IRQ_BUFF_READ_READY (1 << 5) 92#define SDHCI_IRQ_CARD_INSERTION (1 << 6) 93#define SDHCI_IRQ_CARD_REMOVAL (1 << 7) 94#define SDHCI_IRQ_CARD_INTERRUPT (1 << 8) 95#define SDHCI_IRQ_A (1 << 9) 96#define SDHCI_IRQ_B (1 << 10) 97#define SDHCI_IRQ_C (1 << 11) 98#define SDHCI_IRQ_RETUNING (1 << 12) 99#define SDHCI_IRQ_ERR (1 << 15) 100 101#define SDHCI_IRQ_ERR_CMD_TIMEOUT (1 << 16) 102#define SDHCI_IRQ_ERR_CMD_CRC (1 << 17) 103#define SDHCI_IRQ_ERR_CMD_END_BIT (1 << 18) 104#define SDHCI_IRQ_ERR_CMD_INDEX (1 << 19) 105#define SDHCI_IRQ_ERR_CMD (SDHCI_IRQ_ERR_CMD_TIMEOUT | \ 106 SDHCI_IRQ_ERR_CMD_CRC | \ 107 SDHCI_IRQ_ERR_CMD_END_BIT | \ 108 SDHCI_IRQ_ERR_CMD_INDEX) 109#define SDHCI_IRQ_ERR_DAT_TIMEOUT (1 << 20) 110#define SDHCI_IRQ_ERR_DAT_CRC (1 << 21) 111#define SDHCI_IRQ_ERR_DAT_ENDBIT (1 << 22) 112#define SDHCI_IRQ_ERR_DAT (SDHCI_IRQ_ERR_DAT_TIMEOUT | \ 113 SDHCI_IRQ_ERR_DAT_CRC | \ 114 SDHCI_IRQ_ERR_DAT_ENDBIT) 115#define SDHCI_IRQ_ERR_CURRENT_LIMIT (1 << 23) 116#define SDHCI_IRQ_ERR_AUTO_CMD (1 << 24) 117#define SDHCI_IRQ_ERR_ADMA (1 << 25) 118#define SDHCI_IRQ_ERR_TUNING (1 << 26) 119#define SDHCI_IRQ_ERR_VS_1 (1 << 28) 120#define SDHCI_IRQ_ERR_VS_2 (1 << 29) 121#define SDHCI_IRQ_ERR_VS_3 (1 << 30) 122#define SDHCI_IRQ_ERR_VS_4 (1 << 31) 123 uint32_t ctrl2; // 3Ch 124#define SDHCI_HOSTCTRL2_UHS_MODE_SELECT_MASK (7 << 16) 125#define SDHCI_HOSTCTRL2_UHS_MODE_SELECT_SDR12 (0 << 16) 126#define SDHCI_HOSTCTRL2_UHS_MODE_SELECT_SDR25 (1 << 16) 127#define SDHCI_HOSTCTRL2_UHS_MODE_SELECT_SDR50 (2 << 16) 128#define SDHCI_HOSTCTRL2_UHS_MODE_SELECT_SDR104 (3 << 16) 129#define SDHCI_HOSTCTRL2_UHS_MODE_SELECT_DDR50 (4 << 16) 130#define SDHCI_HOSTCTRL2_UHS_MODE_SELECT_HS400 (5 << 16) 131#define SDHCI_HOSTCTRL2_1P8V_SIGNALLING_ENA (1 << 19) 132#define SDHCI_HOSTCTRL2_EXEC_TUNING (1 << 22) 133#define SDHCI_HOSTCTRL2_CLOCK_SELECT (1 << 23) 134 135 uint32_t caps0; // 40h 136#define SDHCI_CORECFG_8_BIT_SUPPORT (1 << 18) 137#define SDHCI_CORECFG_ADMA2_SUPPORT (1 << 19) 138#define SDHCI_CORECFG_3P3_VOLT_SUPPORT (1 << 24) 139#define SDHCI_CORECFG_3P0_VOLT_SUPPORT (1 << 25) 140#define SDHCI_CORECFG_1P8_VOLT_SUPPORT (1 << 26) 141#define SDHCI_CORECFG_64BIT_SUPPORT (1 << 28) 142 143 uint32_t caps1; // 44h 144 uint32_t maxcaps0; // 48h 145 uint32_t maxcaps1; // 4Ch 146 uint32_t forceirq; // 50h 147 uint32_t admaerr; // 54h 148 uint32_t admaaddr0; // 58h 149 uint32_t admaaddr1; // 5Ch 150 uint32_t preset[4]; // 60h 151 uint8_t resvd[112]; 152 uint32_t busctl; 153 154 uint8_t _reserved_4[24]; 155 156 uint32_t slotirqversion; 157#define SDHCI_VERSION_1 0x00 158#define SDHCI_VERSION_2 0x01 159#define SDHCI_VERSION_3 0x02 160} __PACKED sdhci_regs_t; 161