1// Copyright 2016 The Fuchsia Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#pragma once 6 7// clang-format off 8 9#include <hw/reg.h> 10 11#define XHCI_READ32(a) readl(a) 12#define XHCI_WRITE32(a, v) writel(v, a) 13#define XHCI_READ64(a) readll(a) 14#define XHCI_WRITE64(a, v) writell(v, a) 15 16#define XHCI_SET32(addr, mask, bits) XHCI_WRITE32(addr, (XHCI_READ32(addr) & ~(mask)) | ((bits) & (mask))) 17 18#define XHCI_MASK(start, count) (((1 << (count)) - 1) << (start)) 19#define XHCI_GET_BITS32(src, start, count) ((XHCI_READ32(src) & XHCI_MASK(start, count)) >> (start)) 20#define XHCI_SET_BITS32(dest, start, count, value) \ 21 XHCI_WRITE32(dest, (XHCI_READ32(dest) & ~XHCI_MASK(start, count)) | \ 22 (((value) << (start)) & XHCI_MASK(start, count))) 23 24// Max number of endpoints per device 25#define XHCI_NUM_EPS 32 26 27// Data buffers for TRBs are limited to 64K 28#define XHCI_MAX_DATA_BUFFER 65536 29 30// XHCI Capability Registers 31typedef struct { 32 uint8_t length; // Capability Register Length 33 uint8_t reserved; 34 uint16_t hciversion; // Interface Version Number 35 uint32_t hcsparams1; // Structural Parameters 1 36 uint32_t hcsparams2; // Structural Parameters 2 37 uint32_t hcsparams3; // Structural Parameters 3 38 uint32_t hccparams1; // Capability Parameters 1 39 uint32_t dboff; // Doorbell Offset 40 uint32_t rtsoff; // Runtime Register Space Offset 41 uint32_t hccparams2; // Capability Parameters 2 42} __PACKED xhci_cap_regs_t; 43 44// XHCI Port Register Set 45typedef volatile struct { 46 uint32_t portsc; // Port Status and Control 47 uint32_t portpmsc; // Port Power Management Status and Control 48 uint32_t portli; // Port Link Info 49 uint32_t portlpmc; // Port Hardware LPM Control 50} __PACKED xhci_port_regs_t; 51 52// XHCI Operational Registers 53typedef volatile struct { 54 uint32_t usbcmd; // USB Command 55 uint32_t usbsts; // USB Status 56 uint32_t pagesize; // Page Size 57 uint8_t reserved1[8]; 58 uint32_t dnctrl; // Device Notification Control 59 uint64_t crcr; // Command Ring Control 60 uint8_t reserved2[16]; 61 uint64_t dcbaap; // Device Context Base Address Array Pointer 62 uint32_t config; // Configure 63 uint8_t reserved3[964]; 64 xhci_port_regs_t port_regs[]; 65} __PACKED xhci_op_regs_t; 66 67// XHCI Interrupter Registers 68typedef volatile struct { 69 uint32_t iman; // Interrupter Management 70 uint32_t imod; // Interrupter Moderation 71 uint32_t erstsz; // Event Ring Segment Table Size 72 uint32_t reserved; 73 uint64_t erstba; // Event Ring Segment Table Base Address 74 uint64_t erdp; // Event Ring Dequeue Pointer 75} __PACKED xhci_intr_regs_t; 76 77// XHCI Runtime Registers 78typedef volatile struct { 79 uint32_t mfindex; // Microframe Index Register 80 uint32_t reserved[7]; 81 xhci_intr_regs_t intr_regs[1024]; 82} __PACKED xhci_runtime_regs_t; 83#define XHCI_MFINDEX_BITS 14 84 85// Slot Context 86typedef volatile struct { 87 uint32_t sc0; 88 uint32_t sc1; 89 uint32_t sc2; 90 uint32_t sc3; 91 uint32_t reserved[4]; 92} __PACKED xhci_slot_context_t; 93 94// Endpoint Context 95typedef volatile struct { 96 uint32_t epc0; 97 uint32_t epc1; 98 uint32_t epc2; 99 uint32_t tr_dequeue_hi; 100 uint32_t epc4; 101 uint32_t reserved[3]; 102} __PACKED xhci_endpoint_context_t; 103 104// Stream Context 105typedef volatile struct { 106 uint32_t sc0; 107 uint32_t sc1; 108 uint32_t sc2; 109 uint32_t reserved; 110} __PACKED xhci_stream_context_t; 111 112// Input Control Context 113typedef volatile struct { 114 uint32_t drop_context_flags; 115 uint32_t add_context_flags; 116 uint32_t reserved[5]; 117 uint32_t icc7; 118} __PACKED xhci_input_control_context_t; 119 120// Transfer Request Block 121typedef volatile struct { 122 union { 123 uint64_t ptr; 124 struct { 125 uint32_t ptr_low; 126 uint32_t ptr_high; 127 } __PACKED; 128 } __PACKED; 129 uint32_t status; 130 uint32_t control; 131} __PACKED xhci_trb_t; 132 133// Event Ring Segment Table Entry 134typedef volatile struct { 135 uint64_t ptr; 136 uint32_t size; 137 uint32_t reserved; 138} __PACKED erst_entry_t; 139 140// XHCI USB Legacy Support Extended Cap 141typedef volatile struct { 142 uint8_t cap_id; 143 uint8_t next_cap_ptr; 144 uint8_t bios_owned_sem; 145 uint8_t os_owned_sem; 146} __PACKED xhci_usb_legacy_support_cap_t; 147 148// Command register bits 149#define USBCMD_RS (1 << 0) 150#define USBCMD_HCRST (1 << 1) 151#define USBCMD_INTE (1 << 2) 152#define USBCMD_HSEE (1 << 3) 153#define USBCMD_LHCRST (1 << 7) 154#define USBCMD_CSS (1 << 8) 155#define USBCMD_CRS (1 << 9) 156#define USBCMD_EWE (1 << 10) 157#define USBCMD_EU3S (1 << 11) 158#define USBCMD_CME (1 << 12) 159 160// Status register bits 161#define USBSTS_HCH (1 << 0) 162#define USBSTS_HSE (1 << 2) 163#define USBSTS_EINT (1 << 3) 164#define USBSTS_PCD (1 << 4) 165#define USBSTS_SSS (1 << 8) 166#define USBSTS_RSS (1 << 9) 167#define USBSTS_SRE (1 << 10) 168#define USBSTS_CNR (1 << 11) 169#define USBSTS_HCE (1 << 12) 170 171#define USBSTS_CLEAR_BITS (USBSTS_HCH | USBSTS_HSE | USBSTS_EINT | USBSTS_PCD | USBSTS_SSS | \ 172 USBSTS_RSS | USBSTS_SRE | USBSTS_CNR | USBSTS_HCE) 173 174// CONFIG register bits 175#define CONFIG_MAX_SLOTS_ENABLED_START 0 176#define CONFIG_MAX_SLOTS_ENABLED_BITS 8 177#define CONFIG_U3E (1 << 8) 178#define CONFIG_CIE (1 << 9) 179 180// HCSPARAMS1 register bits 181#define HCSPARAMS1_MAX_SLOTS_START 0 182#define HCSPARAMS1_MAX_SLOTS_BITS 8 183#define HCSPARAMS1_MAX_INTRS_START 8 184#define HCSPARAMS1_MAX_INTRS_BITS 11 185#define HCSPARAMS1_MAX_PORTS_START 24 186#define HCSPARAMS1_MAX_PORTS_BITS 8 187 188// HCSPARAMS2 register bits 189#define HCSPARAMS2_IST_BITS 4 190#define HCSPARAMS2_ERST_MAX_START 4 191#define HCSPARAMS2_ERST_MAX_BITS 4 192#define HCSPARAMS2_MAX_SBBUF_HI_START 21 193#define HCSPARAMS2_MAX_SBBUF_HI_BITS 5 194#define HCSPARAMS2_SPR_START 26 195#define HCSPARAMS2_SPR_BITS 1 196#define HCSPARAMS2_MAX_SBBUF_LO_START 27 197#define HCSPARAMS2_MAX_SBBUF_LO_BITS 5 198 199// HCCPARAMS1 register bits 200#define HCCPARAMS1_AC64 (1 << 0) 201#define HCCPARAMS1_BNC (1 << 1) 202#define HCCPARAMS1_CSZ (1 << 2) 203#define HCCPARAMS1_PPC (1 << 3) 204#define HCCPARAMS1_PIND (1 << 4) 205#define HCCPARAMS1_LHRC (1 << 5) 206#define HCCPARAMS1_LTC (1 << 6) 207#define HCCPARAMS1_NSS (1 << 7) 208#define HCCPARAMS1_PAE (1 << 8) 209#define HCCPARAMS1_SPC (1 << 9) 210#define HCCPARAMS1_SEC (1 << 10) 211#define HCCPARAMS1_CFC (1 << 11) 212#define HCCPARAMS1_MAX_PSA_SIZE_START 12 213#define HCCPARAMS1_MAX_PSA_SIZE_BITS 4 214#define HCCPARAMS1_EXT_CAP_PTR_START 16 215#define HCCPARAMS1_EXT_CAP_PTR_BITS 16 216 217// HCCPARAMS2 register bits 218#define HCCPARAMS2_U3C (1 << 0) // U3 Entry Capability 219#define HCCPARAMS2_CMC (1 << 1) // Configure Endpoint Command Max Exit Latency Too Large Capability 220#define HCCPARAMS2_FSC (1 << 2) // Force Save Context Capability 221#define HCCPARAMS2_CTC (1 << 3) // Compliance Transition Capability 222#define HCCPARAMS2_LEC (1 << 4) // Large ESIT Payload Capability 223#define HCCPARAMS2_CIC (1 << 5) // Configuration Information Capability 224 225// XHCI Extended Capabilities register 226#define EXT_CAP_CAPABILITY_ID_START 0 227#define EXT_CAP_CAPABILITY_ID_BITS 8 228#define EXT_CAP_NEXT_PTR_START 8 229#define EXT_CAP_NEXT_PTR_BITS 8 230 231// XHCI Extended Capability codes 232#define EXT_CAP_USB_LEGACY_SUPPORT 1 233#define EXT_CAP_SUPPORTED_PROTOCOL 2 234#define EXT_CAP_EXT_POWER_MANAGEMENT 3 235#define EXT_CAP_IO_VIRTUALIZATION 4 236#define EXT_CAP_MESSAGE_INTERRUPT 5 237#define EXT_CAP_LOCAL_MEMORY 6 238#define EXT_CAP_USB_DEBUG_CAPABILITY 10 239#define EXT_CAP_EXT_MESSAGE_INTERRUPT 17 240 241// XHCI Supported Protocol Capability bits (word 0) 242#define EXT_CAP_SP_REV_MINOR_START 16 243#define EXT_CAP_SP_REV_MINOR_BITS 8 244#define EXT_CAP_SP_REV_MAJOR_START 24 245#define EXT_CAP_SP_REV_MAJOR_BITS 8 246 247// XHCI Supported Protocol Capability bits (word 2) 248#define EXT_CAP_SP_COMPAT_PORT_OFFSET_START 0 249#define EXT_CAP_SP_COMPAT_PORT_OFFSET_BITS 8 250#define EXT_CAP_SP_COMPAT_PORT_COUNT_START 8 251#define EXT_CAP_SP_COMPAT_PORT_COUNT_BITS 8 252#define EXT_CAP_SP_PSIC_START 28 253#define EXT_CAP_SP_PSIC_BITS 4 254 255// XHCI Supported Protocol Speed ID (PSI) bits 256#define EXT_CAP_SP_PSIV_START 0 257#define EXT_CAP_SP_PSIV_BITS 4 258#define EXT_CAP_SP_PSIE_START 4 259#define EXT_CAP_SP_PSIE_BITS 2 260#define EXT_CAP_SP_PLT_START 6 261#define EXT_CAP_SP_PLT_BITS 2 262#define EXT_CAP_SP_PFD (1 << 8) 263#define EXT_CAP_SP_PLT_START 6 264#define EXT_CAP_SP_PSIM_START 16 265#define EXT_CAP_SP_PSIM_BITS 16 266 267// Command Ring Control Register bits 268#define CRCR_RCS (1 << 0) 269#define CRCR_CS (1 << 1) 270#define CRCR_CA (1 << 2) 271#define CRCR_CRR (1 << 3) 272 273// Interrupter register bits 274#define IMAN_IP (1 << 0) // Interrupt Pending 275#define IMAN_IE (1 << 1) // Interrupt Enable 276#define IMODI_MASK 0x0000FFFF // Interrupter Moderation Interval 277#define IMODC_MASK 0xFFFF0000 // Interrupter Moderation Counter 278#define ERSTSZ_MASK 0x0000FFFF 279#define ERDP_DESI_START 0 // First bit of Dequeue ERST Segment Index 280#define ERDP_DESI_BITS 2 // Bit length of Dequeue ERST Segment Index 281#define ERDP_EHB (1 << 3) // Event Handler Busy (set this bit to clear) 282 283// PORTSC bits 284#define PORTSC_CCS (1 << 0) // Current Connect Status 285#define PORTSC_PED (1 << 1) // Port Enabled/Disabled 286#define PORTSC_OCA (1 << 3) // Over-current Active 287#define PORTSC_PR (1 << 4) // Port Reset 288#define PORTSC_PLS_START 5 // Port Link State 289#define PORTSC_PLS_BITS 4 290#define PORTSC_PP (1 << 9) // Port Power 291#define PORTSC_SPEED_START 10 // Port Speed 292#define PORTSC_SPEED_BITS 4 293#define PORTSC_PIC_START 14 // Port Indicator Control 294#define PORTSC_PIC_BITS 2 295#define PORTSC_LWS (1 << 16) // Port Link State Write Strobe 296#define PORTSC_CSC (1 << 17) // Connect Status Change 297#define PORTSC_PEC (1 << 18) // Port Enabled/Disabled Change 298#define PORTSC_WRC (1 << 19) // Warm Port Reset Change 299#define PORTSC_OCC (1 << 20) // Over-current Change 300#define PORTSC_PRC (1 << 21) // Port Reset Change 301#define PORTSC_PLC (1 << 22) // Port Link State Change 302#define PORTSC_CEC (1 << 23) // Port Config Error Change 303#define PORTSC_CAS (1 << 24) // Cold Attach Status 304#define PORTSC_WCE (1 << 25) // Wake on Connect Enable 305#define PORTSC_WDE (1 << 26) // Wake on Disconnect Enable 306#define PORTSC_WOE (1 << 27) // Wake on Over-current Enable 307#define PORTSC_DR (1 << 30) // Device Removable 308#define PORTSC_WPR (1 << 31) // Warm Port Reset 309 310// PORTSC control bits 311#define PORTSC_CONTROL_BITS (PORTSC_PR | PORTSC_PP | PORTSC_LWS | \ 312 PORTSC_WCE | PORTSC_WDE | PORTSC_WOE | \ 313 XHCI_MASK(PORTSC_PLS_START, PORTSC_PLS_BITS) | \ 314 XHCI_MASK(PORTSC_PIC_START, PORTSC_PIC_BITS)) 315 316// PORTSC status bits, set to clear 317#define PORTSC_STATUS_BITS (PORTSC_CSC | PORTSC_PEC | PORTSC_WRC | PORTSC_OCC | \ 318 PORTSC_PRC | PORTSC_PLC | PORTSC_CEC | PORTSC_CAS) 319 320// TRB types 321#define TRB_TRANSFER_NORMAL 1 322#define TRB_TRANSFER_SETUP 2 323#define TRB_TRANSFER_DATA 3 324#define TRB_TRANSFER_STATUS 4 325#define TRB_TRANSFER_ISOCH 5 326#define TRB_LINK 6 327#define TRB_TRANSFER_EVENT_DATA 7 328#define TRB_TRANSFER_NOOP 8 329#define TRB_CMD_ENABLE_SLOT 9 330#define TRB_CMD_DISABLE_SLOT 10 331#define TRB_CMD_ADDRESS_DEVICE 11 332#define TRB_CMD_CONFIGURE_EP 12 333#define TRB_CMD_EVAL_CONTEXT 13 334#define TRB_CMD_RESET_ENDPOINT 14 335#define TRB_CMD_STOP_ENDPOINT 15 336#define TRB_CMD_SET_TR_DEQUEUE 16 337#define TRB_CMD_RESET_DEVICE 17 338#define TRB_CMD_FORCE_EVENT 18 339#define TRB_CMD_NEGOTIATE_BW 19 340#define TRB_CMD_SET_LATENCY 20 341#define TRB_CMD_GET_PORT_BW 21 342#define TRB_CMD_FORCE_HEADER 22 343#define TRB_CMD_NOOP 23 344#define TRB_EVENT_TRANSFER 32 345#define TRB_EVENT_COMMAND_COMP 33 346#define TRB_EVENT_PORT_STATUS_CHANGE 34 347#define TRB_EVENT_BANDWITH_REQ 35 348#define TRB_EVENT_DOORBELL 36 349#define TRB_EVENT_HOST_CONTROLLER 37 350#define TRB_EVENT_DEVICE_NOTIFY 38 351#define TRB_EVENT_MFINDEX_WRAP 39 352 353// TRB condition codes 354#define TRB_CC_SUCCESS 1 355#define TRB_CC_DATA_BUFFER_ERROR 2 356#define TRB_CC_BABBLE_DETECTED_ERROR 3 357#define TRB_CC_USB_TRANSACTION_ERROR 4 358#define TRB_CC_TRB_ERROR 5 359#define TRB_CC_STALL_ERROR 6 360#define TRB_CC_RESOURCE_ERROR 7 361#define TRB_CC_BANDWIDTH_ERROR 8 362#define TRB_CC_NO_SLOTS_AVAILABLE_ERROR 9 363#define TRB_CC_INVALID_STREAM_TYPE_ERROR 10 364#define TRB_CC_SLOT_NOT_ENABLED_ERROR 11 365#define TRB_CC_ENDPOINT_NOT_ENABLED_ERROR 12 366#define TRB_CC_SHORT_PACKET 13 367#define TRB_CC_RING_UNDERRUN 14 368#define TRB_CC_RING_OVERRUN 15 369#define TRB_CC_VF_EVENT_RING_FULL_ERROR 16 370#define TRB_CC_PARAMETER_ERROR 17 371#define TRB_CC_BANDWIDTH_OVERRUN_ERROR 18 372#define TRB_CC_CONTEXT_STATE_ERROR 19 373#define TRB_CC_NO_PING_RESPONSE_ERROR 20 374#define TRB_CC_EVENT_RING_FULL_ERROR 21 375#define TRB_CC_INCOMPATIBLE_DEVICE_ERROR 22 376#define TRB_CC_MISSED_SERVICE_ERROR 23 377#define TRB_CC_COMMAND_RING_STOPPED 24 378#define TRB_CC_COMMAND_ABORTED 25 379#define TRB_CC_STOPPED 26 380#define TRB_CC_STOPPED_LENGTH_INVALID 27 381#define TRB_CC_STOPPED_SHORT_PACKET 28 382#define TRB_CC_MAX_EXIT_LATENCY_ERROR 29 383#define TRB_CC_ISOCH_BUFFER_OVERRUN 31 384#define TRB_CC_EVENT_LOST_ERROR 32 385#define TRB_CC_UNDEFINED_ERROR 33 386#define TRB_CC_INVALID_STREAM_ID_ERROR 34 387#define TRB_CC_SECONDARY_BANDWIDTH_ERROR 35 388#define TRB_CC_SPLIT_TRANSACTION_ERROR 36 389 390// TRB type is in bits 10 - 15 of TRB control field 391#define TRB_TYPE_START 10 392#define TRB_TYPE_BITS 6 393#define TRB_TYPE_MASK (((1 << TRB_TYPE_BITS) - 1) << TRB_TYPE_START) 394 395// TRB Flags (bits on TRB control field) 396#define TRB_C (1 << 0) // Marks enqueue pointer location 397#define TRB_TC (1 << 1) // Toggles interpretation of cycle bit 398#define TRB_CHAIN (1 << 4) // Associates TRB with next TRB 399#define TRB_BSR (1 << 9) // Block Set Address Request 400 401// Event TRB bits 402#define EVT_TRB_CCP_START 0 // Command Completion Parameter 403#define EVT_TRB_CCP_BITS 24 404#define EVT_TRB_CC_START 24 // Completion Code (also used for Transfer event TRBs) 405#define EVT_TRB_CC_BITS 8 406 407// Port Status Change Event TRB bits 408#define EVT_TRB_PORT_ID_START 24 // ID of root hub port that changed 409#define EVT_TRB_PORT_ID_BITS 8 410 411// Transfer event TRB bits 412#define EVT_TRB_XFER_LENGTH_START 0 413#define EVT_TRB_XFER_LENGTH_BITS 24 414#define EVT_TRB_EP_ID_START 16 415#define EVT_TRB_EP_ID_BITS 5 416#define EVT_TRB_ED (1 << 2) // event was generated by event data TRB 417 418// Transfer TRB bits 419#define SETUP_TRB_REQ_TYPE_START 0 420#define SETUP_TRB_REQ_TYPE_BITS 8 421#define SETUP_TRB_REQUEST_START 8 422#define SETUP_TRB_REQUEST_BITS 8 423#define SETUP_TRB_VALUE_START 16 424#define SETUP_TRB_VALUE_BITS 16 425#define SETUP_TRB_INDEX_START 0 426#define SETUP_TRB_INDEX_BITS 16 427#define SETUP_TRB_LENGTH_START 16 428#define SETUP_TRB_LENGTH_BITS 16 429#define XFER_TRB_XFER_LENGTH_START 0 430#define XFER_TRB_XFER_LENGTH_BITS 17 431#define XFER_TRB_TD_SIZE_START 17 432#define XFER_TRB_TD_SIZE_BITS 5 433#define XFER_TRB_INTR_TARGET_START 22 434#define XFER_TRB_INTR_TARGET_BITS 10 435#define XFER_TRB_ENT (1 << 1) 436#define XFER_TRB_ISP (1 << 2) 437#define XFER_TRB_NS (1 << 3) 438#define XFER_TRB_CH (1 << 4) 439#define XFER_TRB_IOC (1 << 5) // Interrupt On Completion 440#define XFER_TRB_IDT (1 << 6) // Immediate Data 441#define XFER_TRB_DIR (1 << 16) // Transfer direction (0 = out, 1 = in) 442#define XFER_TRB_DIR_IN XFER_TRB_DIR 443#define XFER_TRB_DIR_OUT 0 444#define XFER_TRB_TRT_START 16 // Transfer type 445#define XFER_TRB_TRT_BITS 2 446 447// Isoch Transfer TRB bits 448#define XFER_TRB_SIA (1 << 31) // Schedule packet ASAP 449#define XFER_TRB_FRAME_ID_START 20 450#define XFER_TRB_FRAME_ID_BITS 11 451#define XFER_TRB_TLBPC_START 16 452#define XFER_TRB_TLBPC_BITS 4 453#define XFER_TRB_BEI (1 << 9) 454#define XFER_TRB_FRAME_TBC_START 7 455#define XFER_TRB_FRAME_TBC_BITS 2 456 457// Preshifted TRT bits 458#define XFER_TRB_TRT_NONE (0 << XFER_TRB_TRT_START) 459#define XFER_TRB_TRT_OUT (2 << XFER_TRB_TRT_START) 460#define XFER_TRB_TRT_IN (3 << XFER_TRB_TRT_START) 461 462// For various TRBs 463#define TRB_SLOT_ID_START 24 464#define TRB_SLOT_ID_BITS 8 465#define TRB_ENDPOINT_ID_START 16 466#define TRB_ENDPOINT_ID_BITS 5 467#define TRB_ADDRESS_DEVICE_BSR (1 << 9) 468 469// Slot context bits (sc0) 470#define SLOT_CTX_ROUTE_STRING_START 0 471#define SLOT_CTX_ROUTE_STRING_BITS 20 472#define SLOT_CTX_SPEED_START 20 473#define SLOT_CTX_SPEED_BITS 4 474#define SLOT_CTX_MTT_START 25 475#define SLOT_CTX_MTT_BITS 1 476#define SLOT_CTX_HUB (1 << 26) 477#define SLOT_CTX_CONTEXT_ENTRIES_START 27 478#define SLOT_CTX_CONTEXT_ENTRIES_BITS 5 479 480// Slot context bits (sc1) 481#define SLOT_CTX_MAX_EXIT_LATENCY_START 0 482#define SLOT_CTX_MAX_EXIT_LATENCY_BITS 16 483#define SLOT_CTX_ROOT_HUB_PORT_NUM_START 16 484#define SLOT_CTX_ROOT_HUB_PORT_NUM_BITS 8 485#define SLOT_CTX_ROOT_NUM_PORTS_START 24 486#define SLOT_CTX_ROOT_NUM_PORTS_BITS 8 487 488// Slot context bits (sc2) 489#define SLOT_CTX_TT_HUB_SLOT_ID_START 0 490#define SLOT_CTX_TT_HUB_SLOT_ID_BITS 8 491#define SLOT_CTX_TT_PORT_NUM_START 8 492#define SLOT_CTX_TT_PORT_NUM_BITS 8 493#define SLOT_CTX_TTT_START 16 494#define SLOT_CTX_TTT_BITS 2 495#define SLOT_CTX_INTERRUPTER_TARGET_START 22 496#define SLOT_CTX_INTERRUPTER_TARGET_BITS 10 497 498// Slot context bits (sc3) 499#define SLOT_CTX_DEVICE_ADDRESS_START 0 500#define SLOT_CTX_DEVICE_ADDRESS_BITS 8 501#define SLOT_CTX_SLOT_STATE_START 27 502#define SLOT_CTX_SLOT_STATE_BITS 5 503 504// Endpoint context bits (ec0) 505#define EP_CTX_EP_STATE_START 0 506#define EP_CTX_EP_STATE_BITS 3 507#define EP_CTX_MULT_START 8 508#define EP_CTX_MULT_BITS 2 509#define EP_CTX_MAX_P_STREAMS_START 10 510#define EP_CTX_MAX_P_STREAMS_BITS 5 511#define EP_CTX_LSA (1 << 15) 512#define EP_CTX_INTERVAL_START 16 513#define EP_CTX_INTERVAL_BITS 8 514#define EP_CTX_MAX_ESIT_PAYLOAD_HI_START 24 515#define EP_CTX_MAX_ESIT_PAYLOAD_HI_BITS 8 516 517// EP_CTX_EP_STATE values 518#define EP_CTX_STATE_DISABLED 0 519#define EP_CTX_STATE_RUNNING 1 520#define EP_CTX_STATE_HALTED 2 521#define EP_CTX_STATE_STOPPED 3 522#define EP_CTX_STATE_ERROR 4 523 524// Endpoint context bits (epc1) 525#define EP_CTX_CERR_START 1 526#define EP_CTX_CERR_BITS 2 527#define EP_CTX_EP_TYPE_START 3 528#define EP_CTX_EP_TYPE_BITS 3 529#define EP_CTX_HID (1 << 7) 530#define EP_CTX_MAX_BURST_SIZE_START 8 531#define EP_CTX_MAX_BURST_SIZE_BITS 8 532#define EP_CTX_MAX_PACKET_SIZE_START 16 533#define EP_CTX_MAX_PACKET_SIZE_BITS 16 534 535// EP_CTX_EP_TYPE values 536#define EP_CTX_EP_TYPE_ISOCH_OUT 1 537#define EP_CTX_EP_TYPE_BULK_OUT 2 538#define EP_CTX_EP_TYPE_INTERRUPT_OUT 3 539#define EP_CTX_EP_TYPE_CONTROL 4 540#define EP_CTX_EP_TYPE_ISOCH_IN 5 541#define EP_CTX_EP_TYPE_BULK_IN 6 542#define EP_CTX_EP_TYPE_INTERRUPT_IN 7 543 544// Endpoint context bits (epc2) 545#define EP_CTX_DCS (1 << 0) 546#define EP_CTX_TR_DEQUEUE_LO_MASK 0xFFFFFFF0 547 548// Endpoint context bits (epc4) 549#define EP_CTX_AVG_TRB_LENGTH_START 0 550#define EP_CTX_AVG_TRB_LENGTH_BITS 16 551#define EP_CTX_MAX_ESIT_PAYLOAD_LO_START 16 552#define EP_CTX_MAX_ESIT_PAYLOAD_LO_BITS 16 553 554// for input control context add and drop context flags 555#define XHCI_ICC_SLOT_FLAG (1 << 0) 556#define XHCI_ICC_EP_FLAG(ep) (1 << ((ep) + 1)) 557 558static inline uint32_t trb_get_type(xhci_trb_t* trb) { 559 return XHCI_GET_BITS32(&trb->control, TRB_TYPE_START, TRB_TYPE_BITS); 560} 561 562static inline void* trb_get_ptr(xhci_trb_t* trb) { 563#if (UINTPTR_MAX == UINT32_MAX) 564 return (void *)(uint32_t)XHCI_READ64(&trb->ptr); 565#else 566 return (void *)XHCI_READ64(&trb->ptr); 567#endif 568} 569 570static inline void trb_set_ptr(xhci_trb_t* trb, void* ptr) { 571#if (UINTPTR_MAX == UINT32_MAX) 572 XHCI_WRITE64(&trb->ptr, (uint32_t)ptr); 573#else 574 XHCI_WRITE64(&trb->ptr, (uint64_t)ptr); 575#endif 576} 577 578static inline void trb_set_control(xhci_trb_t* trb, uint32_t type, uint32_t flags) { 579 XHCI_WRITE32(&trb->control, ((type << TRB_TYPE_START) & TRB_TYPE_MASK) | flags); 580} 581