1// Copyright 2018 The Fuchsia Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#pragma once 6 7#include <assert.h> 8 9#include "xhci-hw.h" 10 11// clang-format off 12 13// Debug Capability Structure (XHCI Spec, Table 7-16, p. 526) 14typedef volatile struct { 15 uint32_t dcid; // Capability ID 16 uint32_t dcdb; // Doorbell 17 18 // Event Ring Management 19 uint32_t dcerstsz; // Event Ring Segment Table Size 20 uint32_t reserved1; 21 uint64_t dcerstba; // Event Ring Segment Table Base Address 22 uint64_t dcerdp; // Event Ring Dequeue Pointer 23 24 uint32_t dcctrl; // Control 25 uint32_t dcst; // Status 26 27 // Port Management 28 uint32_t dcportsc; // Port Status and Control 29 30 uint32_t reserved2; 31 32 // Endpoint Management 33 uint64_t dccp; // Debug Capability Context Pointer 34 35 // Device Descriptor Information 36 uint32_t dcddi1; // Device Descriptor Info Register 1 37 uint32_t dcddi2; // Device Descriptor Info Register 2 38} __PACKED xdc_debug_cap_regs_t; 39 40static_assert(sizeof(xdc_debug_cap_regs_t) == 0x40, "xdc debug cap wrong size"); 41 42// Debug Capability Info Context (DbCIC) Data Structure (XHCI Spec, Figure 7-11, p.537) 43typedef volatile struct { 44 uint64_t str_0_desc_addr; 45 uint64_t manufacturer_desc_addr; 46 uint64_t product_desc_addr; 47 uint64_t serial_num_desc_addr; 48 49 uint8_t str_0_desc_len; 50 uint8_t manufacturer_desc_len; 51 uint8_t product_desc_len; 52 uint8_t serial_num_desc_len; 53 54 uint32_t reserved[7]; 55} __PACKED xdc_dbcic_t; 56 57static_assert(sizeof(xdc_dbcic_t) == 0x40, "xdc dbcic wrong size"); 58 59// Debug Capability Context Data Structure (XHCI Spec, Figure 7-10, p. 536) 60typedef volatile struct { 61 xdc_dbcic_t dbcic; 62 63 // These are the 64-byte versions of an Endpoint Context. 64 // They have an extra 32 bytes reserved. 65 xhci_endpoint_context_t out_epc; 66 uint32_t reserved1[8]; 67 68 xhci_endpoint_context_t in_epc; 69 uint32_t reserved2[8]; 70} __PACKED xdc_context_data_t; 71 72static_assert(sizeof(xdc_context_data_t) == 0xC0, "xdc context data wrong size"); 73 74// Debug Capability Doorbell Register (DCDB) bits 75#define DCDB_DB_START 8 76#define DCDB_DB_BITS 8 77 78// Doorbell values to write to the DCDB. 79#define DCDB_DB_EP_OUT 0 80#define DCDB_DB_EP_IN 1 81 82// Debug Capability Control Register (DCCTRL) bits 83#define DCCTRL_DCR (1 << 0) 84#define DCCTRL_LSE (1 << 1) 85#define DCCTRL_HOT (1 << 2) 86#define DCCTRL_HIT (1 << 3) 87#define DCCTRL_DRC (1 << 4) 88#define DCCTRL_MAX_BURST_START 16 89#define DCCTRL_MAX_BURST_BITS 8 90#define DCCTRL_DCE (1 << 31) 91 92// Debug Capability Status Register (DCST) bits 93#define DCST_ER_NOT_EMPTY_START 0 94#define DCST_ER_NOT_EMPTY_BITS 1 95#define DCST_PORT_NUM_START 24 96#define DCST_PORT_NUM_BITS 8 97 98// Debug Capability Port Status and Control Register (DCPORTSC) bits 99#define DCPORTSC_CCS (1 << 0) 100#define DCPORTSC_PED (1 << 1) 101#define DCPORTSC_PR (1 << 4) 102#define DCPORTSC_PLS_START 5 103#define DCPORTSC_PLS_BITS 4 104#define DCPORTSC_PS_START 10 105#define DCPORTSC_PS_BITS 4 106#define DCPORTSC_CSC (1 << 17) 107#define DCPORTSC_PRC (1 << 21) 108#define DCPORTSC_PLC (1 << 22) 109#define DCPORTSC_CEC (1 << 23) 110 111// Debug Capability Device Descriptor Info Register 1 (DCDDI1) bits 112#define DCDDI1_VENDOR_ID_START 16 113#define DCDDI1_VENDOR_ID_BITS 16 114 115// Debug Capability Device Descriptor Info Register 2 (DCDDI2) bits 116#define DCDDI2_PRODUCT_ID_START 0 117#define DCDDI2_PRODUCT_ID_BITS 16 118#define DCDDI2_DEVICE_REVISION_START 16 119#define DCDDI2_DEVICE_REVISION_BITS 16 120 121// Device Context Index for the bulk endpoint TRBs. 122#define EP_OUT_DEV_CTX_IDX 2 123#define EP_IN_DEV_CTX_IDX 3 124