1// Copyright 2018 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#pragma once
6
7#include <hw/reg.h>
8#include <lib/sync/completion.h>
9#include <ddk/protocol/platform-bus.h>
10#include <ddk/protocol/platform-defs.h>
11#include <ddk/protocol/platform-device.h>
12#include <ddk/protocol/mailbox.h>
13#include <ddk/protocol/scpi.h>
14#include <ddk/debug.h>
15#include <threads.h>
16
17#define SCPI_ERROR(fmt, ...) zxlogf(ERROR, "[%s %d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
18#define SCPI_INFO(fmt, ...) zxlogf(INFO, "[%s %d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
19
20#define CMD_ID_SHIFT            0
21#define CMD_ID_MASK             0xff
22#define CMD_SENDER_ID_SHIFT     8
23#define CMD_SENDER_ID_MASK      0xff
24#define CMD_DATA_SIZE_SHIFT     20
25#define CMD_DATA_SIZE_MASK      0x1ff
26#define PACK_SCPI_CMD(cmd, sender, txsz)               \
27                                    ((((cmd) & CMD_ID_MASK) << CMD_ID_SHIFT) |          \
28                                    (((sender) & CMD_SENDER_ID_MASK) << CMD_SENDER_ID_SHIFT) |  \
29                                    (((txsz) & CMD_DATA_SIZE_MASK) << CMD_DATA_SIZE_SHIFT))
30
31
32typedef struct {
33    zx_device_t*                        zxdev;
34    platform_device_protocol_t          pdev;
35    mailbox_protocol_t                  mailbox;
36    mtx_t                               lock;
37} aml_scpi_t;
38
39enum aml_scpi_client_id {
40    SCPI_CL_NONE,
41    SCPI_CL_CLOCKS,
42    SCPI_CL_DVFS,
43    SCPI_CL_POWER,
44    SCPI_CL_THERMAL,
45    SCPI_CL_REMOTE,
46    SCPI_CL_LED_TIMER,
47    SCPI_MAX,
48 };
49
50enum aml_scpi_cmd {
51    SCPI_CMD_INVALID                = 0x00,
52    SCPI_CMD_SCPI_READY             = 0x01,
53    SCPI_CMD_SCPI_CAPABILITIES      = 0x02,
54    SCPI_CMD_EVENT                  = 0x03,
55    SCPI_CMD_SET_CSS_PWR_STATE      = 0x04,
56    SCPI_CMD_GET_CSS_PWR_STATE      = 0x05,
57    SCPI_CMD_CFG_PWR_STATE_STAT     = 0x06,
58    SCPI_CMD_GET_PWR_STATE_STAT     = 0x07,
59    SCPI_CMD_SYS_PWR_STATE          = 0x08,
60    SCPI_CMD_L2_READY               = 0x09,
61    SCPI_CMD_SET_AP_TIMER           = 0x0a,
62    SCPI_CMD_CANCEL_AP_TIME         = 0x0b,
63    SCPI_CMD_DVFS_CAPABILITIES      = 0x0c,
64    SCPI_CMD_GET_DVFS_INFO          = 0x0d,
65    SCPI_CMD_SET_DVFS               = 0x0e,
66    SCPI_CMD_GET_DVFS               = 0x0f,
67    SCPI_CMD_GET_DVFS_STAT          = 0x10,
68    SCPI_CMD_SET_RTC                = 0x11,
69    SCPI_CMD_GET_RTC                = 0x12,
70    SCPI_CMD_CLOCK_CAPABILITIES     = 0x13,
71    SCPI_CMD_SET_CLOCK_INDEX        = 0x14,
72    SCPI_CMD_SET_CLOCK_VALUE        = 0x15,
73    SCPI_CMD_GET_CLOCK_VALUE        = 0x16,
74    SCPI_CMD_PSU_CAPABILITIES       = 0x17,
75    SCPI_CMD_SET_PSU                = 0x18,
76    SCPI_CMD_GET_PSU                = 0x19,
77    SCPI_CMD_SENSOR_CAPABILITIES    = 0x1a,
78    SCPI_CMD_SENSOR_INFO            = 0x1b,
79    SCPI_CMD_SENSOR_VALUE           = 0x1c,
80    SCPI_CMD_SENSOR_CFG_PERIODIC    = 0x1d,
81    SCPI_CMD_SENSOR_CFG_BOUNDS      = 0x1e,
82    SCPI_CMD_SENSOR_ASYNC_VALUE     = 0x1f,
83    SCPI_CMD_SET_USR_DATA           = 0x20,
84    SCPI_CMD_MAX                    = 0x21,
85 };
86
87#define VALID_CMD(cmd)           (cmd>SCPI_CMD_INVALID && cmd<SCPI_CMD_MAX)
88
89static uint32_t aml_high_priority_cmds[] = {
90    SCPI_CMD_GET_DVFS,
91    SCPI_CMD_SET_DVFS,
92    SCPI_CMD_SET_CLOCK_VALUE,
93};
94
95static uint32_t aml_low_priority_cmds[] = {
96    SCPI_CMD_GET_DVFS_INFO,
97    SCPI_CMD_SENSOR_CAPABILITIES,
98    SCPI_CMD_SENSOR_INFO,
99    SCPI_CMD_SENSOR_VALUE,
100 };
101
102static uint32_t aml_secure_cmds[] = {
103    SCPI_CMD_SET_CSS_PWR_STATE,
104    SCPI_CMD_SYS_PWR_STATE,
105};
106