1// Copyright 2018 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#include <zircon/compiler.h>
6
7#pragma once
8
9// clang-format off
10// Please don't touch my columns.
11
12#define APP_LTSSM_ENABLE                      (1 << 7)
13
14#define PORT_LINK_CTRL_OFF                    (0x710)
15#define PLC_VENDOR_SPECIFIC_DLLP_REQ          (1 << 0)
16#define PLC_SCRAMBLE_DISABLE                  (1 << 1)
17#define PLC_LOOPBACK_ENABLE                   (1 << 2)
18#define PLC_RESET_ASSERT                      (1 << 3)
19#define PLC_DLL_LINK_EN                       (1 << 5)
20#define PLC_LINK_DISABLE                      (1 << 6)
21#define PLC_FAST_LINK_MODE                    (1 << 7)
22#define PLC_LINK_RATE_MASK                    (0xF << 8)
23#define PLC_LINK_CAPABLE_MASK                 (0x3F << 16)
24    #define PLC_LINK_CAPABLE_X1               (0x01 << 16)
25    #define PLC_LINK_CAPABLE_X2               (0x03 << 16)
26    #define PLC_LINK_CAPABLE_X4               (0x07 << 16)
27    #define PLC_LINK_CAPABLE_X8               (0x0f << 16)
28    #define PLC_LINK_CAPABLE_X16              (0x1f << 16)
29#define PLC_BEACON_ENABLE                     (1 << 24)
30#define PLC_CORRUPT_LCRC_ENABLE               (1 << 25)
31#define PLC_EXTENDED_SYNC_H                   (1 << 26)
32#define PLC_TRANSMIT_LANE_REVERSAL_ENABLE     (1 << 27)
33
34#define GEN2_CTRL_OFF                         (0x80C)
35#define G2_CTRL_FAST_TRAINING_SEQ_MASK        (0xFF << 0)
36#define G2_CTRL_NUM_OF_LANES_MASK             (0x1F << 8)
37    #define G2_CTRL_NO_OF_LANES(x)            ((x) << 8)
38#define G2_CTRL_PRE_DET_LANE_MASK             (0x07 << 13)
39#define G2_CTRL_AUTO_LANE_FLIP_CTRL_EN        (1 << 16)
40#define G2_CTRL_DIRECT_SPEED_CHANGE           (1 << 17)
41#define G2_CTRL_CONFIG_PHY_TX_CHANGE          (1 << 18)
42#define G2_CTRL_CONFIG_TX_COMP_RX             (1 << 19)
43#define G2_CTRL_SEL_DEEMPHASIS                (1 << 20)
44#define G2_CTRL_GEN1_EI_INFERENCE             (1 << 21)
45
46#define PCIE_CTRL_STS_OFF                     (0x78)
47#define PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MASK     (0x7 << 5)
48
49#define PCIE_TYPE1_STS_CMD_OFF                (0x04)
50#define PCIE_TYPE1_STS_CMD_IO_ENABLE          (1 << 0)
51#define PCIE_TYPE1_STS_CMD_MEM_SPACE_ENABLE   (1 << 1)
52#define PCIE_TYPE1_STS_CMD_BUS_MASTER_ENABLE  (1 << 2)
53
54#define PCIE_CFG_STATUS12                     (0x30)
55    #define PCIE_CFG12_SMLH_UP                (0x01 << 6)
56    #define PCIE_CFG12_RDLH_UP                (0x01 << 16)
57    #define PCIE_CFG12_LTSSM_MASK             (0x1f << 10)
58    #define PCIE_CFG12_LTSSM_UP               (0x11 << 10)
59
60#define PCIE_HEADER_TYPE_MASK                 (0x7f)
61#define PCIE_HEADER_TYPE0                     (0x0)
62#define PCIE_HEADER_TYPE1                     (0x1)
63#define PCIE_HEADER_TYPE1                     (0x1)
64#define PCIE_HEADER_BUS_REG_OFF               (0x18)
65
66#define PCI_TYPE1_BAR0  (0x10)
67#define PCI_TYPE1_BAR1  (0x14)
68
69typedef struct pci_bus_reg {
70    uint8_t primary_bus;
71    uint8_t secondary_bus;
72    uint8_t subordinate_bus;
73    uint8_t secondary_lat_timer;
74}  __PACKED pci_bus_reg_t;
75