1// Copyright 2018 The Fuchsia Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#pragma once 6 7#define KB(x) (x << 10) 8#define MB(x) (x << 20) 9#define GB(x) (x << 30) 10 11/* iMX8M Top Level A53 memory map */ 12#define IMX8M_PCIE_1_BASE 0x18000000 13#define IMX8M_PCIE_1_LENGTH MB(128) 14#define IMX8M_PCIE_2_BASE 0x20000000 15#define IMX8M_PCIE_2_LENGTH MB(128) 16#define IMX8M_A53_DAP_BASE 0x28000000 17#define IMX8M_A53_DAP_LENGHT MB(16) 18#define IMX8M_GPU_BASE 0x38000000 19#define IMX8M_GPU_LENGTH KB(64) 20#define IMX8M_USB1_BASE 0x38100000 21#define IMX8M_USB1_LENGTH MB(1) 22#define IMX8M_USB2_BASE 0x38200000 23#define IMX8M_USB2_LENGTH MB(1) 24#define IMX8M_VPU_BASE 0x38300000 25#define IMX8M_VPU_LENGTH MB(2) 26#define IMX8M_GIC_BASE 0x38800000 27#define IMX8M_GIC_LENGTH MB(1) 28#define IMX8M_I2C1_BASE 0x30A20000 29#define IMX8M_I2C1_LENGTH 20 30#define IMX8M_I2C2_BASE 0x30A30000 31#define IMX8M_I2C2_LENGTH 20 32#define IMX8M_I2C3_BASE 0x30A40000 33#define IMX8M_I2C3_LENGTH 20 34#define IMX8M_I2C4_BASE 0x30A50000 35#define IMX8M_I2C4_LENGTH 20 36 37/* iMX8M AIPS (Peripheral) Memory */ 38#define IMX8M_AIPS_LENGTH KB(64) 39#define IMX8M_AIPS_GPIO1_BASE 0x30200000 40#define IMX8M_AIPS_GPIO2_BASE 0x30210000 41#define IMX8M_AIPS_GPIO3_BASE 0x30220000 42#define IMX8M_AIPS_GPIO4_BASE 0x30230000 43#define IMX8M_AIPS_GPIO5_BASE 0x30240000 44#define IMX8M_AIPS_WDOG1_BASE 0x30280000 45#define IMX8M_AIPS_WDOG2_BASE 0x30290000 46#define IMX8M_AIPS_WDOG3_BASE 0x302A0000 47#define IMX8M_AIPS_GPT1_BASE 0x302D0000 48#define IMX8M_AIPS_GPT2_BASE 0x302E0000 49#define IMX8M_AIPS_GPT3_BASE 0x302F0000 50#define IMX8M_AIPS_IOMUXC_BASE 0x30330000 51#define IMX8M_AIPS_IOMUXC_GPR_BASE 0x30340000 52#define IMX8M_AIPS_CCM_BASE 0x30380000 53#define IMX8M_AIPS_GPC_BASE 0x303A0000 54#define IMX8M_AIPS_PWM1_BASE 0x30660000 55#define IMX8M_AIPS_PWM2_BASE 0x30670000 56#define IMX8M_AIPS_PWM3_BASE 0x30680000 57#define IMX8M_AIPS_PWM4_BASE 0x30690000 58#define IMX8M_AIPS_GPT6_BASE 0x306E0000 59#define IMX8M_AIPS_GPT5_BASE 0x306F0000 60#define IMX8M_AIPS_GPT4_BASE 0x30700000 61#define IMX8M_AIPS_SPDIF1_BASE 0x30810000 62#define IMX8M_AIPS_ECSPI1_BASE 0x30820000 63#define IMX8M_AIPS_ECSPI2_BASE 0x30830000 64#define IMX8M_AIPS_ECSPI3_BASE 0x30840000 65#define IMX8M_AIPS_UART1_BASE 0x30860000 66#define IMX8M_AIPS_UART3_BASE 0x30880000 67#define IMX8M_AIPS_UART2_BASE 0x30890000 68#define IMX8M_AIPS_SPDIF2_BASE 0x308A0000 69#define IMX8M_AIPS_MIPI_PHY_BASE 0x30A00000 70#define IMX8M_AIPS_MIPI_DSI_BASE 0x30A10000 71#define IMX8M_AIPS_I2C1_BASE 0x30A20000 72#define IMX8M_AIPS_I2C2_BASE 0x30A30000 73#define IMX8M_AIPS_I2C3_BASE 0x30A40000 74#define IMX8M_AIPS_I2C4_BASE 0x30A50000 75#define IMX8M_AIPS_UART4_BASE 0x30A60000 76#define IMX8M_AIPS_USDHC1_BASE 0x30B40000 77#define IMX8M_AIPS_USDHC2_BASE 0x30B50000 78#define IMX8M_AIPS_QSPI_BASE 0x30BB0000 79#define IMX8M_AIPS_ENET1_BASE 0x30BE0000 80#define IMX8M_AIPS_DC_MST0_BASE 0x32E00000 81#define IMX8M_AIPS_DC_MST1_BASE 0x32E10000 82#define IMX8M_AIPS_DC_MST2_BASE 0x32E20000 83#define IMX8M_AIPS_DC_MST3_BASE 0x32E30000 84 85 #define IMX8M_A53_INTR_BOOT (32 + 0) 86 #define IMX8M_A53_INTR_DAP (32 + 1) 87 #define IMX8M_A53_INTR_SDMA1 (32 + 2) 88 #define IMX8M_A53_INTR_GPU (32 + 3) 89 #define IMX8M_A53_INTR_SNVS_LP_WRAPPER (32 + 4) 90 #define IMX8M_A53_INTR_LCDIF (32 + 5) 91 #define IMX8M_A53_INTR_SPDIF1 (32 + 6) 92 #define IMX8M_A53_INTR_H264DEC (32 + 7) 93 #define IMX8M_A53_INTR_VPUDMA (32 + 8) 94 #define IMX8M_A53_INTR_QOS (32 + 9) 95 #define IMX8M_A53_INTR_WDOG3 (32 + 10) 96 #define IMX8M_A53_INTR_HS (32 + 11) 97 #define IMX8M_A53_INTR_APBHDMA (32 + 12) 98 #define IMX8M_A53_INTR_SPDIF2 (32 + 13) 99 #define IMX8M_A53_INTR_SPDIF2 (32 + 13) 100 #define IMX8M_A53_INTR_RAWNAND_BCH_COMP (32 + 14) 101 #define IMX8M_A53_INTR_RAWNAND_GPMI_TO (32 + 15) 102 #define IMX8M_A53_INTR_HDMI_IPS (32 + 16) 103 #define IMX8M_A53_INTR_HDMI_IPSx (32 + 17) 104 #define IMX8M_A53_INTR_HDMI_IPSy (32 + 18) 105 #define IMX8M_A53_INTR_SNVS_HP_WRAPPER_NOTZ (32 + 19) 106 #define IMX8M_A53_INTR_SNVS_HP_WRAPPER_TZ (32 + 20) 107 #define IMX8M_A53_INTR_CSU (32 + 21) 108 #define IMX8M_A53_INTR_USDHC1 (32 + 22) 109 #define IMX8M_A53_INTR_USDHC2 (32 + 23) 110 #define IMX8M_A53_INTR_DC8000_CONTROL (32 + 24) 111 #define IMX8M_A53_INTR_DTRC_WRAPPER (32 + 25) 112 #define IMX8M_A53_INTR_UART1 (32 + 26) 113 #define IMX8M_A53_INTR_UART2 (32 + 27) 114 #define IMX8M_A53_INTR_UART3 (32 + 28) 115 #define IMX8M_A53_INTR_UART4 (32 + 29) 116 #define IMX8M_A53_INTR_VP9DEC (32 + 30) 117 #define IMX8M_A53_INTR_ECSPI1 (32 + 31) 118 #define IMX8M_A53_INTR_ECSPI2 (32 + 32) 119 #define IMX8M_A53_INTR_ECSPI3 (32 + 33) 120 #define IMX8M_A53_INTR_MIPI_DSI (32 + 34) 121 #define IMX8M_A53_INTR_I2C1 (32 + 35) 122 #define IMX8M_A53_INTR_I2C2 (32 + 36) 123 #define IMX8M_A53_INTR_I2C3 (32 + 37) 124 #define IMX8M_A53_INTR_I2C4 (32 + 38) 125 #define IMX8M_A53_INTR_RDC (32 + 39) 126 #define IMX8M_A53_INTR_USB1 (32 + 40) 127 #define IMX8M_A53_INTR_USB2 (32 + 41) 128 #define IMX8M_A53_INTR_CSI1 (32 + 42) 129 #define IMX8M_A53_INTR_CSI2 (32 + 43) 130 #define IMX8M_A53_INTR_MIPI_CSI1 (32 + 44) 131 #define IMX8M_A53_INTR_MIPI_CSI2 (32 + 45) 132 #define IMX8M_A53_INTR_GPT6 (32 + 46) 133 #define IMX8M_A53_INTR_SCTR0 (32 + 47) 134 #define IMX8M_A53_INTR_SCTR1 (32 + 48) 135 #define IMX8M_A53_INTR_ANAMIX_ALARM (32 + 49) 136 #define IMX8M_A53_INTR_ANAMIX_CRIT_ALARM (32 + 49) 137 #define IMX8M_A53_INTR_RESERVED (32 + 49) 138 #define IMX8M_A53_INTR_SAI3_RX (32 + 50) 139 #define IMX8M_A53_INTR_SAI3_RX_ASYNC (32 + 50) 140 #define IMX8M_A53_INTR_SAI3_TX (32 + 50) 141 #define IMX8M_A53_INTR_SAI3_TX_ASYNC (32 + 50) 142 #define IMX8M_A53_INTR_GPT5 (32 + 51) 143 #define IMX8M_A53_INTR_GPT4 (32 + 52) 144 #define IMX8M_A53_INTR_GPT3 (32 + 53) 145 #define IMX8M_A53_INTR_GPT2 (32 + 54) 146 #define IMX8M_A53_INTR_GPT1 (32 + 55) 147 #define IMX8M_A53_INTR_GPIO1_INT7 (32 + 56) 148 #define IMX8M_A53_INTR_GPIO1_INT6 (32 + 57) 149 #define IMX8M_A53_INTR_GPIO1_INT5 (32 + 58) 150 #define IMX8M_A53_INTR_GPIO1_INT4 (32 + 59) 151 #define IMX8M_A53_INTR_GPIO1_INT3 (32 + 60) 152 #define IMX8M_A53_INTR_GPIO1_INT2 (32 + 61) 153 #define IMX8M_A53_INTR_GPIO1_INT1 (32 + 62) 154 #define IMX8M_A53_INTR_GPIO1_INT0 (32 + 63) 155 #define IMX8M_A53_INTR_GPIO1_INT_COMB_0_15 (32 + 64) 156 #define IMX8M_A53_INTR_GPIO1_INT_COMP_16_31 (32 + 65) 157 #define IMX8M_A53_INTR_GPIO2_INT_COMB_0_15 (32 + 66) 158 #define IMX8M_A53_INTR_GPIO2_INT_COMP_16_31 (32 + 67) 159 #define IMX8M_A53_INTR_GPIO3_INT_COMB_0_15 (32 + 68) 160 #define IMX8M_A53_INTR_GPIO3_INT_COMP_16_31 (32 + 69) 161 #define IMX8M_A53_INTR_GPIO4_INT_COMB_0_15 (32 + 70) 162 #define IMX8M_A53_INTR_GPIO4_INT_COMP_16_31 (32 + 71) 163 #define IMX8M_A53_INTR_GPIO5_INT_COMB_0_15 (32 + 72) 164 #define IMX8M_A53_INTR_GPIO5_INT_COMP_16_31 (32 + 73) 165 #define IMX8M_A53_INTR_PCIE_CTRL2 (32 + 74) 166 #define IMX8M_A53_INTR_PCIE_CTRL2x (32 + 75) 167 #define IMX8M_A53_INTR_PCIE_CTRL2y (32 + 76) 168 #define IMX8M_A53_INTR_PCIE_CTRL2z (32 + 77) 169 #define IMX8M_A53_INTR_WDOG1 (32 + 78) 170 #define IMX8M_A53_INTR_WDOG2 (32 + 79) 171 #define IMX8M_A53_INTR_PCIE_CTRL2zz (32 + 80) 172 #define IMX8M_A53_INTR_PWM1 (32 + 81) 173 #define IMX8M_A53_INTR_PWM2 (32 + 82) 174 #define IMX8M_A53_INTR_PWM3 (32 + 83) 175 #define IMX8M_A53_INTR_PWM4 (32 + 84) 176 #define IMX8M_A53_INTR_CCMSRCGPCMIX_CCM1 (32 + 85) 177 #define IMX8M_A53_INTR_CCMSRCGPCMIX_CMM2 (32 + 86) 178 #define IMX8M_A53_INTR_CCMSRCGPCMIX_GPC1 (32 + 87) 179 #define IMX8M_A53_INTR_MU (32 + 88) 180 #define IMX8M_A53_INTR_CCMSRCGPCMIX (32 + 89) 181 #define IMX8M_A53_INTR_SAI5_RX (32 + 90) 182 #define IMX8M_A53_INTR_SAI5_RX_ASYNC (32 + 90) 183 #define IMX8M_A53_INTR_SAI5_TX (32 + 90) 184 #define IMX8M_A53_INTR_SAI5_TX_ASYNC (32 + 90) 185 #define IMX8M_A53_INTR_SAI6_RX (32 + 90) 186 #define IMX8M_A53_INTR_SAI6_RX_ASYNC (32 + 90) 187 #define IMX8M_A53_INTR_SAI6_TX (32 + 90) 188 #define IMX8M_A53_INTR_SAI6_TX_ASYNC (32 + 90) 189 #define IMX8M_A53_INTR_RTIC (32 + 91) 190 #define IMX8M_A53_INTR_CPU_PMUIRQ_0 (32 + 92) 191 #define IMX8M_A53_INTR_CPU_PMUIRQ_1 (32 + 92) 192 #define IMX8M_A53_INTR_CPU_PMUIRQ_2 (32 + 92) 193 #define IMX8M_A53_INTR_CPU_PMUIRQ_3 (32 + 92) 194 #define IMX8M_A53_INTR_CPU_NCTIIRQ_0 (32 + 93) 195 #define IMX8M_A53_INTR_CPU_NCTIIRQ_2 (32 + 93) 196 #define IMX8M_A53_INTR_CPU_NCTIIRQ_3 (32 + 93) 197 #define IMX8M_A53_INTR_CPU_NCTIIRQ_4 (32 + 93) 198 #define IMX8M_A53_INTR_CCMSRCGPCMIX_WDOG (32 + 94) 199 #define IMX8M_A53_INTR_SAI1_RX (32 + 95) 200 #define IMX8M_A53_INTR_SAI1_RX_ASYNC (32 + 95) 201 #define IMX8M_A53_INTR_SAI1_TX (32 + 95) 202 #define IMX8M_A53_INTR_SAI1_TX_ASYNC (32 + 95) 203 #define IMX8M_A53_INTR_SAI2_RX (32 + 96) 204 #define IMX8M_A53_INTR_SAI2_RX_ASYNC (32 + 96) 205 #define IMX8M_A53_INTR_SAI2_TX (32 + 96) 206 #define IMX8M_A53_INTR_SAI2_TX_ASYNC (32 + 96) 207 #define IMX8M_A53_INTR_MU_M4 (32 + 97) 208 #define IMX8M_A53_INTR_DDR (32 + 98) 209 #define IMX8M_A53_INTR_SAI4_RX (32 + 100) 210 #define IMX8M_A53_INTR_SAI4_RX_ASYNC (32 + 100) 211 #define IMX8M_A53_INTR_SAI4_TX (32 + 100) 212 #define IMX8M_A53_INTR_SAI4_TX_ASYNC (32 + 100) 213 #define IMX8M_A53_INTR_CPU_ERR_AXI (32 + 101) 214 #define IMX8M_A53_INTR_CPU_L2_RAM_ECC (32 + 102) 215 #define IMX8M_A53_INTR_SDMA2 (32 + 103) 216 #define IMX8M_A53_INTR_RESERVED4 (32 + 104) 217 #define IMX8M_A53_INTR_CAAM_WRAPPER (32 + 105) 218 #define IMX8M_A53_INTR_CAAM_WRAPPERx (32 + 106) 219 #define IMX8M_A53_INTR_QSPI (32 + 107) 220 #define IMX8M_A53_INTR_TZASC (32 + 108) 221 #define IMX8M_A53_INTR_RESERVED1 (32 + 109) 222 #define IMX8M_A53_INTR_RESERVED2 (32 + 110) 223 #define IMX8M_A53_INTR_RESERVED3 (32 + 111) 224 #define IMX8M_A53_INTR_PERFMON1 (32 + 112) 225 #define IMX8M_A53_INTR_PERFMON2 (32 + 113) 226 #define IMX8M_A53_INTR_CAAM_WRAPPER_JQ (32 + 114) 227 #define IMX8M_A53_INTR_CAAM_WRAPPER_RECOVER (32 + 115) 228 #define IMX8M_A53_INTR_HS_IRQ (32 + 116) 229 #define IMX8M_A53_INTR_HEVCDEC (32 + 117) 230 #define IMX8M_A53_INTR_ENET1_MAC0_RX_BUFFER_DONE (32 + 118) 231 #define IMX8M_A53_INTR_ENET1_MAC0_RX_FRAME_DONE (32 + 118) 232 #define IMX8M_A53_INTR_ENET1_MAC0_TX_BUFFER_DONE (32 + 118) 233 #define IMX8M_A53_INTR_ENET1_MAC0_TX_FRAME_DONE (32 + 118) 234 #define IMX8M_A53_INTR_ENET1_MAC0_RX_BUFFER_DONEx (32 + 119) 235 #define IMX8M_A53_INTR_ENET1_MAC0_RX_FRAME_DONEx (32 + 119) 236 #define IMX8M_A53_INTR_ENET1_MAC0_TX_BUFFER_DONEx (32 + 119) 237 #define IMX8M_A53_INTR_ENET1_MAC0_TX_FRAME_DONEx (32 + 119) 238 #define IMX8M_A53_INTR_ENET1_MAC0_PERI_TIMER_OF (32 + 120) 239 #define IMX8M_A53_INTR_ENET1_MAC0_TIME_STAMP_AVAIL (32 + 120) 240 #define IMX8M_A53_INTR_ENET1_MAC0_PAYLOAD_RX_ERROR (32 + 120) 241 #define IMX8M_A53_INTR_ENET1_MAC0_TX_FIFO_UNDERRUN (32 + 120) 242 #define IMX8M_A53_INTR_ENET1_MAC0_COLL_RETRY_LIMIT (32 + 120) 243 #define IMX8M_A53_INTR_ENET1_MAC0_LATE_COLLISION (32 + 120) 244 #define IMX8M_A53_INTR_ENET1_MAC0_ETHERNET_BUS_ERROR (32 + 120) 245 #define IMX8M_A53_INTR_ENET1_MAC0_MII_DATA_TRANSFER (32 + 120) 246 #define IMX8M_A53_INTR_ENET1_MAC0_RX_BUFFER_DONEy (32 + 120) 247 #define IMX8M_A53_INTR_ENET1_MAC0_RX_FRAME_DONEy (32 + 120) 248 #define IMX8M_A53_INTR_ENET1_MAC0_TX_BUFFER_DONEy (32 + 120) 249 #define IMX8M_A53_INTR_ENET1_MAC0_TX_FRAME_DONEy (32 + 120) 250 #define IMX8M_A53_INTR_ENET1_MAC0_GRACEFUL_STOP_ (32 + 120) 251 #define IMX8M_A53_INTR_ENET1_MAC0_BABBLING_TX_ERR (32 + 120) 252 #define IMX8M_A53_INTR_ENET1_MAC0_BABBLING_RX_ERR (32 + 120) 253 #define IMX8M_A53_INTR_ENET1_MAC0_RX_FLUSH_FRAME0 (32 + 120) 254 #define IMX8M_A53_INTR_ENET1_MAC0_RX_FLUSH_FRAME1 (32 + 120) 255 #define IMX8M_A53_INTR_ENET1_MAC0_RX_FLUSH_FRAME2 (32 + 120) 256 #define IMX8M_A53_INTR_ENET1_MAC0_WAKEUP_REQUEST_SYNC (32 + 120) 257 #define IMX8M_A53_INTR_ENET1_MAC0_BABBLING_RX_ERR (32 + 120) 258 #define IMX8M_A53_INTR_ENET1_MAC0_WAKEUP_REQ_SYNC (32 + 120) 259 #define IMX8M_A53_INTR_ENET1_1588_INTR (32 + 121) 260 #define IMX8M_A53_INTR_PCIE_CTRL1 (32 + 122) 261 #define IMX8M_A53_INTR_PCIE_CTRL1x (32 + 123) 262 #define IMX8M_A53_INTR_PCIE_CTRL1y (32 + 124) 263 #define IMX8M_A53_INTR_PCIE_CTRL1z (32 + 125) 264 #define IMX8M_A53_INTR_RESERVED5 (32 + 126) 265 #define IMX8M_A53_INTR_PCIE_CTRL1zz (32 + 127) 266 267/* USB PHY CTRL Registers (undocumented) */ 268#define USB_PHY_CTRL0 (0xF0040) 269#define PHY_CTRL0_REF_SSP_EN (1 << 2) 270#define USB_PHY_CTRL1 (0xF0044) 271#define PHY_CTRL1_RESET (1 << 0) 272#define PHY_CTRL1_ATERESET (1 << 3) 273#define PHY_CTRL1_VDATSRCENB0 (1 << 19) 274#define PHY_CTRL1_VDATDETENB0 (1 << 20) 275#define USB_PHY_CTRL2 (0xF0048) 276#define PHY_CTRL2_TXENABLEN0 (1 << 8) 277