1// Copyright 2016 The Fuchsia Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#pragma once 6 7// clang-format off 8 9#define ASIX_VID 0x0B95 10#define AX88179_PID 0x1790 11 12#define AX88179_PHY_ID 0x03 13 14// Vendor commands 15#define AX88179_REQ_MAC 0x01 16#define AX88179_REQ_PHY 0x02 17#define AX88179_REQ_WKUP 0x03 18#define AX88179_REQ_NVS 0x04 19#define AX88179_REQ_EFUSE 0x05 20#define AX88179_REQ_EFUSE_RELOAD 0x06 21#define AX88179_REQ_MFA 0x10 22#define AX88179_REQ_USB 0x81 23#define AX88179_REQ_WATCHDOG 0x91 24 25// MAC registers 26#define AX88179_MAC_ 27#define AX88179_MAC_PLSR 0x02 28#define AX88179_MAC_GSR 0x03 29#define AX88179_MAC_SMSR 0x04 30#define AX88179_MAC_CSR 0x05 31#define AX88179_MAC_EAR 0x07 32#define AX88179_MAC_EDLR 0x08 33#define AX88179_MAC_EDHR 0x09 34#define AX88179_MAC_ECR 0x0a 35#define AX88179_MAC_RCR 0x0b 36#define AX88179_MAC_IPGCR 0x0d 37#define AX88179_MAC_NIDR 0x10 38#define AX88179_MAC_MFA 0x16 39#define AX88179_MAC_TR 0x1e 40#define AX88179_MAC_DSCR 0x20 41#define AX88179_MAC_MSR 0x22 42#define AX88179_MAC_MMSR 0x24 43#define AX88179_MAC_GPIOCR 0x25 44#define AX88179_MAC_EPPRCR 0x26 45#define AX88179_MAC_JLCR 0x29 46#define AX88179_MAC_VCR 0x2a 47#define AX88179_MAC_RQCR 0x2e 48#define AX88179_MAC_RQTLR 0x2f 49#define AX88179_MAC_RQTHR 0x30 50#define AX88179_MAC_RQSIZE 0x31 51#define AX88179_MAC_RQIFGR 0x32 52#define AX88179_MAC_CLKSR 0x33 53#define AX88179_MAC_CRCR 0x34 54#define AX88179_MAC_CTCR 0x35 55#define AX88179_MAC_CPCR 0x36 56#define AX88179_MAC_PWLHR 0x54 57#define AX88179_MAC_PWLLR 0x55 58#define AX88179_MAC_TXFBR 0x56 59#define AX88179_MAC_RXFBLR 0x57 60#define AX88179_MAC_RXFBHR 0x58 61#define AX88179_MAC_PINCR 0x70 62#define AX88179_MAC_LEDCR 0x73 63 64// PHY registers 65#define AX88179_PHY_BMCR 0x00 66#define AX88179_PHY_BMSR 0x01 67#define AX88179_PHY_PHYID1 0x02 68#define AX88179_PHY_PHYID2 0x03 69#define AX88179_PHY_ANAR 0x04 70#define AX88179_PHY_ANLPAR 0x05 71#define AX88179_PHY_ANER 0x06 72#define AX88179_PHY_ANNPTR 0x07 73#define AX88179_PHY_ANNPRR 0x08 74#define AX88179_PHY_GBCR 0x09 75#define AX88179_PHY_GBSR 0x0a 76#define AX88179_PHY_MACR 0x0d 77#define AX88179_PHY_MAADR 0x0e 78#define AX88179_PHY_GBESR 0x0f 79#define AX88179_PHY_PHYCR 0x10 80#define AX88179_PHY_PHYSR 0x11 81#define AX88179_PHY_INER 0x12 82#define AX88179_PHY_INSR 0x13 83#define AX88179_PHY_RXERC 0x18 84#define AX88179_PHY_PAGSEL 0x1f 85#define AX88179_PHY_ELEDIR1 0x05 86#define AX88179_PHY_ELEDIR2 0x06 87#define AX88179_PHY_EPAGSR 0x1e 88#define AX88179_PHY_LEDACR 0x1a 89#define AX88179_PHY_LEDCR 0x1c 90 91#define AX88179_PHY_MMD_PC1R 0x00 92#define AX88179_PHY_MMD_PS1R 0x01 93#define AX88179_PHY_MMD_EEECR 0x14 94#define AX88179_PHY_MMD_EEEWER 0x16 95#define AX88179_PHY_MMD_EEEAR 0x3c 96#define AX88179_PHY_MMD_EEELPAR 0x3d 97 98// USB registers 99#define AX88179_USB_EP2FIFO 0x5c 100#define AX88179_USB_EP3FIFO 0x8c 101#define AX88179_USB_U1U2CTL 0x310 102 103// Register bits -- define as needed 104#define AX88179_PLSR_USB_FS (1 << 0) 105#define AX88179_PLSR_USB_HS (1 << 1) 106#define AX88179_PLSR_USB_SS (1 << 2) 107#define AX88179_PLSR_USB_MASK (AX88179_PLSR_USB_FS|AX88179_PLSR_USB_HS|AX88179_PLSR_USB_SS) 108 109#define AX88179_PLSR_EPHY_10 (1 << 4) 110#define AX88179_PLSR_EPHY_100 (1 << 5) 111#define AX88179_PLSR_EPHY_1000 (1 << 6) 112#define AX88179_PLSR_EPHY_MASK (AX88179_PLSR_EPHY_10|AX88179_PLSR_EPHY_100|AX88179_PLSR_EPHY_1000) 113 114#define AX88179_PHYSR_SPEED (3 << 14) 115#define AX88179_PHYSR_DUPLEX (1 << 13) 116 117// PROMISC = receive everything 118#define AX88179_RCR_PROMISC (1 << 0) 119// AMALL = receive all multicast. 120#define AX88179_RCR_AMALL (1 << 1) 121// AB = receive all broadcast. 122#define AX88179_RCR_AB (1 << 3) 123// AM = use multicast filter (ignored if AMALL is set) 124#define AX88179_RCR_AM (1 << 4) 125// AP = accept physical through multicast filter 126#define AX88179_RCR_AP (1 << 5) 127// SO = start operation 128#define AX88179_RCR_SO (1 << 7) 129// DROP_CRC_N 1 = don't drop CRC field (default 0) 130#define AX88179_RCR_DROP_CRCE_N (1 << 8) 131// IPE_N = enable IP alignment 132#define AX88179_RCR_IPE_N (1 << 9) 133 134// Headers 135#define AX88179_RX_DROPPKT 0x80000000 136#define AX88179_RX_MIIER 0x40000000 137#define AX88179_RX_CRCER 0x20000000 138#define AX88179_RX_PKTLEN 0x1fff0000 139#define AX88179_RX_BMC 0x00008000 140#define AX88179_RX_VLANPRI 0x00007000 141#define AX88179_RX_OK 0x00000800 142#define AX88179_RX_VLANIND 0x00000700 143#define AX88179_RX_COE 0x000000ff 144 145//#define AX88179_RX_COE_??? 0x80 146#define AX88179_RX_COE_L3_MASK 0x60 147#define AX88179_RX_COE_L3_IPV6 0x40 148#define AX88179_RX_COE_L3_IPV4 0x20 149 150#define AX88179_RX_COE_L4_MASK 0x1c 151#define AX88179_RX_COE_L4_ICMPv6 0x11 152#define AX88179_RX_COE_L4_TCP 0x10 153#define AX88179_RX_COE_L4_IGMP 0x0c 154#define AX88179_RX_COE_L4_ICMP 0x08 155#define AX88179_RX_COE_L4_UDP 0x04 156 157#define AX88179_RX_COE_L3_CKSUM_ERR 0x02 158#define AX88179_RX_COE_L4_CKSUM_ERR 0x01 159