1// Copyright 2018 The Fuchsia Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#include <hw/reg.h> 6#include <stdint.h> 7#include <stdlib.h> 8#include <threads.h> 9 10#include <zircon/assert.h> 11#include <zircon/threads.h> 12 13#include <ddk/binding.h> 14#include <ddk/debug.h> 15#include <ddk/device.h> 16#include <ddk/protocol/clk.h> 17#include <ddk/protocol/platform-bus.h> 18#include <ddk/protocol/platform-defs.h> 19#include <ddk/protocol/platform-device.h> 20 21#include <dev/clk/hisi-lib/hisi.h> 22#include <soc/hi3660/hi3660-hw.h> 23 24 25static hisi_clk_gate_t hi3660_clk_gates[] = { 26 { .reg = 0x0, .bit = 0, .flags = HISI_CLK_FLAG_BANK_PERI }, 27 { .reg = 0x0, .bit = 21, .flags = HISI_CLK_FLAG_BANK_PERI }, 28 { .reg = 0x0, .bit = 30, .flags = HISI_CLK_FLAG_BANK_PERI }, 29 { .reg = 0x0, .bit = 31, .flags = HISI_CLK_FLAG_BANK_PERI }, 30 { .reg = 0x10, .bit = 0, .flags = HISI_CLK_FLAG_BANK_PERI }, 31 { .reg = 0x10, .bit = 1, .flags = HISI_CLK_FLAG_BANK_PERI }, 32 { .reg = 0x10, .bit = 2, .flags = HISI_CLK_FLAG_BANK_PERI }, 33 { .reg = 0x10, .bit = 3, .flags = HISI_CLK_FLAG_BANK_PERI }, 34 { .reg = 0x10, .bit = 4, .flags = HISI_CLK_FLAG_BANK_PERI }, 35 { .reg = 0x10, .bit = 5, .flags = HISI_CLK_FLAG_BANK_PERI }, 36 { .reg = 0x10, .bit = 6, .flags = HISI_CLK_FLAG_BANK_PERI }, 37 { .reg = 0x10, .bit = 7, .flags = HISI_CLK_FLAG_BANK_PERI }, 38 { .reg = 0x10, .bit = 8, .flags = HISI_CLK_FLAG_BANK_PERI }, 39 { .reg = 0x10, .bit = 9, .flags = HISI_CLK_FLAG_BANK_PERI }, 40 { .reg = 0x10, .bit = 10, .flags = HISI_CLK_FLAG_BANK_PERI }, 41 { .reg = 0x10, .bit = 11, .flags = HISI_CLK_FLAG_BANK_PERI }, 42 { .reg = 0x10, .bit = 12, .flags = HISI_CLK_FLAG_BANK_PERI }, 43 { .reg = 0x10, .bit = 13, .flags = HISI_CLK_FLAG_BANK_PERI }, 44 { .reg = 0x10, .bit = 14, .flags = HISI_CLK_FLAG_BANK_PERI }, 45 { .reg = 0x10, .bit = 15, .flags = HISI_CLK_FLAG_BANK_PERI }, 46 { .reg = 0x10, .bit = 16, .flags = HISI_CLK_FLAG_BANK_PERI }, 47 { .reg = 0x10, .bit = 17, .flags = HISI_CLK_FLAG_BANK_PERI }, 48 { .reg = 0x10, .bit = 18, .flags = HISI_CLK_FLAG_BANK_PERI }, 49 { .reg = 0x10, .bit = 19, .flags = HISI_CLK_FLAG_BANK_PERI }, 50 { .reg = 0x10, .bit = 20, .flags = HISI_CLK_FLAG_BANK_PERI }, 51 { .reg = 0x10, .bit = 21, .flags = HISI_CLK_FLAG_BANK_PERI }, 52 { .reg = 0x10, .bit = 30, .flags = HISI_CLK_FLAG_BANK_PERI }, 53 { .reg = 0x10, .bit = 31, .flags = HISI_CLK_FLAG_BANK_PERI }, 54 { .reg = 0x20, .bit = 7, .flags = HISI_CLK_FLAG_BANK_PERI }, 55 { .reg = 0x20, .bit = 9, .flags = HISI_CLK_FLAG_BANK_PERI }, 56 { .reg = 0x20, .bit = 11, .flags = HISI_CLK_FLAG_BANK_PERI }, 57 { .reg = 0x20, .bit = 12, .flags = HISI_CLK_FLAG_BANK_PERI }, 58 { .reg = 0x20, .bit = 14, .flags = HISI_CLK_FLAG_BANK_PERI }, 59 { .reg = 0x20, .bit = 15, .flags = HISI_CLK_FLAG_BANK_PERI }, 60 { .reg = 0x20, .bit = 27, .flags = HISI_CLK_FLAG_BANK_PERI }, 61 { .reg = 0x30, .bit = 1, .flags = HISI_CLK_FLAG_BANK_PERI }, 62 { .reg = 0x30, .bit = 10, .flags = HISI_CLK_FLAG_BANK_PERI }, 63 { .reg = 0x30, .bit = 11, .flags = HISI_CLK_FLAG_BANK_PERI }, 64 { .reg = 0x30, .bit = 12, .flags = HISI_CLK_FLAG_BANK_PERI }, 65 { .reg = 0x30, .bit = 13, .flags = HISI_CLK_FLAG_BANK_PERI }, 66 { .reg = 0x30, .bit = 14, .flags = HISI_CLK_FLAG_BANK_PERI }, 67 { .reg = 0x30, .bit = 15, .flags = HISI_CLK_FLAG_BANK_PERI }, 68 { .reg = 0x30, .bit = 16, .flags = HISI_CLK_FLAG_BANK_PERI }, 69 { .reg = 0x30, .bit = 17, .flags = HISI_CLK_FLAG_BANK_PERI }, 70 { .reg = 0x30, .bit = 28, .flags = HISI_CLK_FLAG_BANK_PERI }, 71 { .reg = 0x30, .bit = 29, .flags = HISI_CLK_FLAG_BANK_PERI }, 72 { .reg = 0x30, .bit = 30, .flags = HISI_CLK_FLAG_BANK_PERI }, 73 { .reg = 0x30, .bit = 31, .flags = HISI_CLK_FLAG_BANK_PERI }, 74 { .reg = 0x40, .bit = 1, .flags = HISI_CLK_FLAG_BANK_PERI }, 75 { .reg = 0x40, .bit = 4, .flags = HISI_CLK_FLAG_BANK_PERI }, 76 { .reg = 0x40, .bit = 17, .flags = HISI_CLK_FLAG_BANK_PERI }, 77 { .reg = 0x40, .bit = 19, .flags = HISI_CLK_FLAG_BANK_PERI }, 78 { .reg = 0x50, .bit = 16, .flags = HISI_CLK_FLAG_BANK_PERI }, 79 { .reg = 0x50, .bit = 17, .flags = HISI_CLK_FLAG_BANK_PERI }, 80 { .reg = 0x50, .bit = 18, .flags = HISI_CLK_FLAG_BANK_PERI }, 81 { .reg = 0x50, .bit = 21, .flags = HISI_CLK_FLAG_BANK_PERI }, 82 { .reg = 0x50, .bit = 28, .flags = HISI_CLK_FLAG_BANK_PERI }, 83 { .reg = 0x50, .bit = 29, .flags = HISI_CLK_FLAG_BANK_PERI }, 84 { .reg = 0x420, .bit = 5, .flags = HISI_CLK_FLAG_BANK_PERI }, 85 { .reg = 0x420, .bit = 7, .flags = HISI_CLK_FLAG_BANK_PERI }, 86 { .reg = 0x420, .bit = 8, .flags = HISI_CLK_FLAG_BANK_PERI }, 87 { .reg = 0x420, .bit = 9, .flags = HISI_CLK_FLAG_BANK_PERI }, 88 89 { .reg = 0x258, .bit = 7, .flags = HISI_CLK_FLAG_BANK_SCTRL }, 90 { .reg = 0x260, .bit = 11, .flags = HISI_CLK_FLAG_BANK_SCTRL }, 91 { .reg = 0x260, .bit = 12, .flags = HISI_CLK_FLAG_BANK_SCTRL }, 92 { .reg = 0x260, .bit = 13, .flags = HISI_CLK_FLAG_BANK_SCTRL }, 93 { .reg = 0x268, .bit = 11, .flags = HISI_CLK_FLAG_BANK_SCTRL }, 94}; 95 96static_assert(HI3660_SEP_CLK_GATE_COUNT == countof(hi3660_clk_gates), 97 "hi3660_clk_gates[] and hisi_3660_sep_gate_clk_idx count mismatch"); 98 99static const char hi3660_clk_name[] = "hi3660-clk"; 100 101static zx_status_t hi3660_clk_bind(void* ctx, zx_device_t* parent) { 102 return hisi_clk_init(hi3660_clk_name, hi3660_clk_gates, 103 countof(hi3660_clk_gates), parent); 104} 105 106static zx_driver_ops_t hi3660_clk_driver_ops = { 107 .version = DRIVER_OPS_VERSION, 108 .bind = hi3660_clk_bind, 109}; 110 111ZIRCON_DRIVER_BEGIN(hi3660_clk, hi3660_clk_driver_ops, "zircon", "0.1", 3) 112 BI_ABORT_IF(NE, BIND_PROTOCOL, ZX_PROTOCOL_PLATFORM_DEV), 113 BI_ABORT_IF(NE, BIND_PLATFORM_DEV_VID, PDEV_VID_96BOARDS), 114 BI_MATCH_IF(EQ, BIND_PLATFORM_DEV_DID, PDEV_DID_HI3660_CLK), 115ZIRCON_DRIVER_END(hi3660_clk) 116