1// Copyright 2016 The Fuchsia Authors
2// Copyright (c) 2015 Travis Geiselbrecht
3//
4// Use of this source code is governed by a MIT-style
5// license that can be found in the LICENSE file or at
6// https://opensource.org/licenses/MIT
7
8#pragma once
9
10/* up to 30 GB of ram */
11#define MEMORY_BASE_PHYS     (0x40000000)
12
13/* memory map of peripherals, from qemu hw/arm/virt.c */
14#if 0
15static const MemMapEntry a15memmap[] = {
16    /* Space up to 0x8000000 is reserved for a boot ROM */
17    [VIRT_FLASH] =              {          0, 0x08000000 },
18    [VIRT_CPUPERIPHS] =         { 0x08000000, 0x00020000 },
19    /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
20    [VIRT_GIC_DIST] =           { 0x08000000, 0x00010000 },
21    [VIRT_GIC_CPU] =            { 0x08010000, 0x00010000 },
22    [VIRT_GIC_V2M] =            { 0x08020000, 0x00001000 },
23    [VIRT_UART] =               { 0x09000000, 0x00001000 },
24    [VIRT_RTC] =                { 0x09010000, 0x00001000 },
25    [VIRT_FW_CFG] =             { 0x09020000, 0x0000000a },
26    [VIRT_MMIO] =               { 0x0a000000, 0x00000200 },
27    /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
28    [VIRT_PLATFORM_BUS] =       { 0x0c000000, 0x02000000 },
29    [VIRT_PCIE_MMIO] =          { 0x10000000, 0x2eff0000 },
30    [VIRT_PCIE_PIO] =           { 0x3eff0000, 0x00010000 },
31    [VIRT_PCIE_ECAM] =          { 0x3f000000, 0x01000000 },
32    [VIRT_MEM] =                { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
33};
34
35static const int a15irqmap[] = {
36    [VIRT_UART] = 1,
37    [VIRT_RTC] = 2,
38    [VIRT_PCIE] = 3, /* ... to 6 */
39    [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
40    [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
41    [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
42};
43#endif
44
45/* map all of 0-1GB into kernel space in one shot */
46#define PERIPHERAL_BASE_PHYS (0)
47#define PERIPHERAL_BASE_SIZE (0x40000000UL) // 1GB
48
49#define PERIPHERAL_BASE_VIRT (0xffffffffc0000000ULL) // -1GB
50
51/* individual peripherals in this mapping */
52#define CPUPRIV_BASE_VIRT   (PERIPHERAL_BASE_VIRT + 0x08000000)
53#define CPUPRIV_BASE_PHYS   (PERIPHERAL_BASE_PHYS + 0x08000000)
54#define CPUPRIV_SIZE        (0x00020000)
55#define UART_BASE           (PERIPHERAL_BASE_VIRT + 0x09000000)
56#define UART_SIZE           (0x00001000)
57#define RTC_BASE            (PERIPHERAL_BASE_VIRT + 0x09010000)
58#define RTC_BASE_PHYS       (PERIPHERAL_BASE_PHYS + 0x09010000)
59#define RTC_SIZE            (0x00001000)
60#define FW_CFG_BASE         (PERIPHERAL_BASE_VIRT + 0x09020000)
61#define FW_CFG_SIZE         (0x00001000)
62#define NUM_VIRTIO_TRANSPORTS 32
63#define VIRTIO_BASE         (PERIPHERAL_BASE_VIRT + 0x0a000000)
64#define VIRTIO_SIZE         (NUM_VIRTIO_TRANSPORTS * 0x200)
65#define PCIE_MMIO_BASE_PHYS ((zx_paddr_t)(PERIPHERAL_BASE_PHYS + 0x10000000))
66#define PCIE_MMIO_SIZE      (0x2eff0000)
67#define PCIE_PIO_BASE_PHYS  ((zx_paddr_t)(PERIPHERAL_BASE_PHYS + 0x3eff0000))
68#define PCIE_PIO_SIZE       (0x00010000)
69#define PCIE_ECAM_BASE_PHYS ((zx_paddr_t)(PERIPHERAL_BASE_PHYS + 0x3f000000))
70#define PCIE_ECAM_SIZE      (0x01000000)
71#define GICV2M_FRAME_PHYS   (PERIPHERAL_BASE_PHYS + 0x08020000)
72
73// Unused MMIO ranges for test drivers
74#define TEST_MMIO_1         (PERIPHERAL_BASE_PHYS + 0)
75#define TEST_MMIO_1_SIZE    0x1000
76#define TEST_MMIO_2         (PERIPHERAL_BASE_PHYS + 0x1000)
77#define TEST_MMIO_2_SIZE    0x2000
78#define TEST_MMIO_3         (PERIPHERAL_BASE_PHYS + 0x3000)
79#define TEST_MMIO_3_SIZE    0x3000
80#define TEST_MMIO_4         (PERIPHERAL_BASE_PHYS + 0x6000)
81#define TEST_MMIO_4_SIZE    0x4000
82
83/* interrupts */
84#define ARM_GENERIC_TIMER_VIRTUAL_INT 27
85#define ARM_GENERIC_TIMER_PHYSICAL_INT 30
86#define UART0_INT       (32 + 1)
87#define RTC_INT         (32 + 2)
88#define PCIE_INT_BASE   (32 + 3)
89#define PCIE_INT_COUNT  (4)
90#define VIRTIO0_INT     (32 + 16)
91
92#define MAX_INT 288
93
94