1// Copyright 2018 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#define HAS_DEVICE_TREE 1
6
7static const zbi_cpu_config_t cpu_config = {
8    .cluster_count = 2,
9    .clusters = {
10        {
11            .cpu_count = 4,
12        },
13        {
14            .cpu_count = 4,
15        },
16    },
17};
18
19static const zbi_mem_range_t mem_config[] = {
20    {
21        .type = ZBI_MEM_RANGE_RAM,
22        .length = 0xc0000000, // 3GB
23    },
24    {
25        .type = ZBI_MEM_RANGE_PERIPHERAL,
26        .paddr = 0xe8100000,
27        .length = 0x17f00000,
28    },
29    {
30        // memory to reserve to avoid stomping on bootloader data
31        .type = ZBI_MEM_RANGE_RESERVED,
32        .paddr = 0x00000000,
33        .length = 0x00080000,
34    },
35    {
36        // bl31
37        .type = ZBI_MEM_RANGE_RESERVED,
38        .paddr = 0x20200000,
39        .length = 0x200000,
40    },
41    {
42        // pstore
43        .type = ZBI_MEM_RANGE_RESERVED,
44        .paddr = 0x20a00000,
45        .length = 0x100000,
46    },
47    {
48        // lpmx-core
49        .type = ZBI_MEM_RANGE_RESERVED,
50        .paddr = 0x89b80000,
51        .length = 0x100000,
52    },
53    {
54        // lpmcu
55        .type = ZBI_MEM_RANGE_RESERVED,
56        .paddr = 0x89c80000,
57        .length = 0x40000,
58    },
59};
60
61static const dcfg_simple_t uart_driver = {
62    .mmio_phys = 0xfff32000,
63    .irq = 111,
64};
65
66static const dcfg_arm_gicv2_driver_t gicv2_driver = {
67    .mmio_phys = 0xe82b0000,
68    .gicd_offset = 0x1000,
69    .gicc_offset = 0x2000,
70    .gich_offset = 0x4000,
71    .gicv_offset = 0x6000,
72    .ipi_base = 12,
73};
74
75static const dcfg_arm_psci_driver_t psci_driver = {
76    .use_hvc = false,
77};
78
79static const dcfg_arm_generic_timer_driver_t timer_driver = {
80    .irq_phys = 30,
81    .irq_virt = 27,
82};
83
84static const dcfg_hisilicon_power_driver_t power_driver = {
85    .sctrl_phys = 0xfff0a000,
86    .pmu_phys = 0xfff34000,
87};
88
89static const zbi_platform_id_t platform_id = {
90    .vid = PDEV_VID_96BOARDS,
91    .pid = PDEV_PID_HIKEY960,
92    .board_name = "hikey960",
93};
94
95static void append_board_boot_item(zbi_header_t* bootdata) {
96    // add CPU configuration
97    append_boot_item(bootdata, ZBI_TYPE_CPU_CONFIG, 0, &cpu_config,
98                    sizeof(zbi_cpu_config_t) +
99                    sizeof(zbi_cpu_cluster_t) * cpu_config.cluster_count);
100
101    // add memory configuration
102    append_boot_item(bootdata, ZBI_TYPE_MEM_CONFIG, 0, &mem_config,
103                    sizeof(zbi_mem_range_t) * countof(mem_config));
104
105    // add kernel drivers
106    append_boot_item(bootdata, ZBI_TYPE_KERNEL_DRIVER, KDRV_PL011_UART, &uart_driver,
107                    sizeof(uart_driver));
108    append_boot_item(bootdata, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GIC_V2, &gicv2_driver,
109                    sizeof(gicv2_driver));
110    append_boot_item(bootdata, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_PSCI, &psci_driver,
111                    sizeof(psci_driver));
112    append_boot_item(bootdata, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GENERIC_TIMER, &timer_driver,
113                    sizeof(timer_driver));
114    append_boot_item(bootdata, ZBI_TYPE_KERNEL_DRIVER, KDRV_HISILICON_POWER, &power_driver,
115                    sizeof(power_driver));
116
117    // add platform ID
118    append_boot_item(bootdata, ZBI_TYPE_PLATFORM_ID, 0, &platform_id, sizeof(platform_id));
119}
120