1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 5 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer, 13 * without modification, immediately at the beginning of the file. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#ifndef _AHCI_H_ 31#define _AHCI_H_ 32 33/* ATA register defines */ 34#define ATA_DATA 0 /* (RW) data */ 35 36#define ATA_FEATURE 1 /* (W) feature */ 37#define ATA_F_DMA 0x01 /* enable DMA */ 38#define ATA_F_OVL 0x02 /* enable overlap */ 39 40#define ATA_COUNT 2 /* (W) sector count */ 41 42#define ATA_SECTOR 3 /* (RW) sector # */ 43#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 44#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 45#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 46#define ATA_D_LBA 0x40 /* use LBA addressing */ 47#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 48 49#define ATA_COMMAND 7 /* (W) command */ 50 51#define ATA_ERROR 8 /* (R) error */ 52#define ATA_E_ILI 0x01 /* illegal length */ 53#define ATA_E_NM 0x02 /* no media */ 54#define ATA_E_ABORT 0x04 /* command aborted */ 55#define ATA_E_MCR 0x08 /* media change request */ 56#define ATA_E_IDNF 0x10 /* ID not found */ 57#define ATA_E_MC 0x20 /* media changed */ 58#define ATA_E_UNC 0x40 /* uncorrectable data */ 59#define ATA_E_ICRC 0x80 /* UDMA crc error */ 60#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 61 62#define ATA_IREASON 9 /* (R) interrupt reason */ 63#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 64#define ATA_I_IN 0x02 /* read (1) | write (0) */ 65#define ATA_I_RELEASE 0x04 /* released bus (1) */ 66#define ATA_I_TAGMASK 0xf8 /* tag mask */ 67 68#define ATA_STATUS 10 /* (R) status */ 69#define ATA_ALTSTAT 11 /* (R) alternate status */ 70#define ATA_S_ERROR 0x01 /* error */ 71#define ATA_S_INDEX 0x02 /* index */ 72#define ATA_S_CORR 0x04 /* data corrected */ 73#define ATA_S_DRQ 0x08 /* data request */ 74#define ATA_S_DSC 0x10 /* drive seek completed */ 75#define ATA_S_SERVICE 0x10 /* drive needs service */ 76#define ATA_S_DWF 0x20 /* drive write fault */ 77#define ATA_S_DMA 0x20 /* DMA ready */ 78#define ATA_S_READY 0x40 /* drive ready */ 79#define ATA_S_BUSY 0x80 /* busy */ 80 81#define ATA_CONTROL 12 /* (W) control */ 82#define ATA_A_IDS 0x02 /* disable interrupts */ 83#define ATA_A_RESET 0x04 /* RESET controller */ 84#define ATA_A_4BIT 0x08 /* 4 head bits */ 85#define ATA_A_HOB 0x80 /* High Order Byte enable */ 86 87/* SATA register defines */ 88#define ATA_SSTATUS 13 89#define ATA_SS_DET_MASK 0x0000000f 90#define ATA_SS_DET_NO_DEVICE 0x00000000 91#define ATA_SS_DET_DEV_PRESENT 0x00000001 92#define ATA_SS_DET_PHY_ONLINE 0x00000003 93#define ATA_SS_DET_PHY_OFFLINE 0x00000004 94 95#define ATA_SS_SPD_MASK 0x000000f0 96#define ATA_SS_SPD_NO_SPEED 0x00000000 97#define ATA_SS_SPD_GEN1 0x00000010 98#define ATA_SS_SPD_GEN2 0x00000020 99#define ATA_SS_SPD_GEN3 0x00000030 100 101#define ATA_SS_IPM_MASK 0x00000f00 102#define ATA_SS_IPM_NO_DEVICE 0x00000000 103#define ATA_SS_IPM_ACTIVE 0x00000100 104#define ATA_SS_IPM_PARTIAL 0x00000200 105#define ATA_SS_IPM_SLUMBER 0x00000600 106#define ATA_SS_IPM_DEVSLEEP 0x00000800 107 108#define ATA_SERROR 14 109#define ATA_SE_DATA_CORRECTED 0x00000001 110#define ATA_SE_COMM_CORRECTED 0x00000002 111#define ATA_SE_DATA_ERR 0x00000100 112#define ATA_SE_COMM_ERR 0x00000200 113#define ATA_SE_PROT_ERR 0x00000400 114#define ATA_SE_HOST_ERR 0x00000800 115#define ATA_SE_PHY_CHANGED 0x00010000 116#define ATA_SE_PHY_IERROR 0x00020000 117#define ATA_SE_COMM_WAKE 0x00040000 118#define ATA_SE_DECODE_ERR 0x00080000 119#define ATA_SE_PARITY_ERR 0x00100000 120#define ATA_SE_CRC_ERR 0x00200000 121#define ATA_SE_HANDSHAKE_ERR 0x00400000 122#define ATA_SE_LINKSEQ_ERR 0x00800000 123#define ATA_SE_TRANSPORT_ERR 0x01000000 124#define ATA_SE_UNKNOWN_FIS 0x02000000 125#define ATA_SE_EXCHANGED 0x04000000 126 127#define ATA_SCONTROL 15 128#define ATA_SC_DET_MASK 0x0000000f 129#define ATA_SC_DET_IDLE 0x00000000 130#define ATA_SC_DET_RESET 0x00000001 131#define ATA_SC_DET_DISABLE 0x00000004 132 133#define ATA_SC_SPD_MASK 0x000000f0 134#define ATA_SC_SPD_NO_SPEED 0x00000000 135#define ATA_SC_SPD_SPEED_GEN1 0x00000010 136#define ATA_SC_SPD_SPEED_GEN2 0x00000020 137#define ATA_SC_SPD_SPEED_GEN3 0x00000030 138 139#define ATA_SC_IPM_MASK 0x00000f00 140#define ATA_SC_IPM_NONE 0x00000000 141#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 142#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 143#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400 144 145#define ATA_SACTIVE 16 146 147#define AHCI_MAX_PORTS 32 148#define AHCI_MAX_SLOTS 32 149#define AHCI_MAX_IRQS 16 150 151/* SATA AHCI v1.0 register defines */ 152#define AHCI_CAP 0x00 153#define AHCI_CAP_NPMASK 0x0000001f 154#define AHCI_CAP_SXS 0x00000020 155#define AHCI_CAP_EMS 0x00000040 156#define AHCI_CAP_CCCS 0x00000080 157#define AHCI_CAP_NCS 0x00001F00 158#define AHCI_CAP_NCS_SHIFT 8 159#define AHCI_CAP_PSC 0x00002000 160#define AHCI_CAP_SSC 0x00004000 161#define AHCI_CAP_PMD 0x00008000 162#define AHCI_CAP_FBSS 0x00010000 163#define AHCI_CAP_SPM 0x00020000 164#define AHCI_CAP_SAM 0x00080000 165#define AHCI_CAP_ISS 0x00F00000 166#define AHCI_CAP_ISS_SHIFT 20 167#define AHCI_CAP_SCLO 0x01000000 168#define AHCI_CAP_SAL 0x02000000 169#define AHCI_CAP_SALP 0x04000000 170#define AHCI_CAP_SSS 0x08000000 171#define AHCI_CAP_SMPS 0x10000000 172#define AHCI_CAP_SSNTF 0x20000000 173#define AHCI_CAP_SNCQ 0x40000000 174#define AHCI_CAP_64BIT 0x80000000 175 176#define AHCI_GHC 0x04 177#define AHCI_GHC_AE 0x80000000 178#define AHCI_GHC_MRSM 0x00000004 179#define AHCI_GHC_IE 0x00000002 180#define AHCI_GHC_HR 0x00000001 181 182#define AHCI_IS 0x08 183#define AHCI_PI 0x0c 184#define AHCI_VS 0x10 185 186#define AHCI_CCCC 0x14 187#define AHCI_CCCC_TV_MASK 0xffff0000 188#define AHCI_CCCC_TV_SHIFT 16 189#define AHCI_CCCC_CC_MASK 0x0000ff00 190#define AHCI_CCCC_CC_SHIFT 8 191#define AHCI_CCCC_INT_MASK 0x000000f8 192#define AHCI_CCCC_INT_SHIFT 3 193#define AHCI_CCCC_EN 0x00000001 194#define AHCI_CCCP 0x18 195 196#define AHCI_EM_LOC 0x1C 197#define AHCI_EM_CTL 0x20 198#define AHCI_EM_MR 0x00000001 199#define AHCI_EM_TM 0x00000100 200#define AHCI_EM_RST 0x00000200 201#define AHCI_EM_LED 0x00010000 202#define AHCI_EM_SAFTE 0x00020000 203#define AHCI_EM_SES2 0x00040000 204#define AHCI_EM_SGPIO 0x00080000 205#define AHCI_EM_SMB 0x01000000 206#define AHCI_EM_XMT 0x02000000 207#define AHCI_EM_ALHD 0x04000000 208#define AHCI_EM_PM 0x08000000 209 210#define AHCI_CAP2 0x24 211#define AHCI_CAP2_BOH 0x00000001 212#define AHCI_CAP2_NVMP 0x00000002 213#define AHCI_CAP2_APST 0x00000004 214#define AHCI_CAP2_SDS 0x00000008 215#define AHCI_CAP2_SADM 0x00000010 216#define AHCI_CAP2_DESO 0x00000020 217 218#define AHCI_OFFSET 0x100 219#define AHCI_STEP 0x80 220 221#define AHCI_P_CLB 0x00 222#define AHCI_P_CLBU 0x04 223#define AHCI_P_FB 0x08 224#define AHCI_P_FBU 0x0c 225#define AHCI_P_IS 0x10 226#define AHCI_P_IE 0x14 227#define AHCI_P_IX_DHR 0x00000001 228#define AHCI_P_IX_PS 0x00000002 229#define AHCI_P_IX_DS 0x00000004 230#define AHCI_P_IX_SDB 0x00000008 231#define AHCI_P_IX_UF 0x00000010 232#define AHCI_P_IX_DP 0x00000020 233#define AHCI_P_IX_PC 0x00000040 234#define AHCI_P_IX_MP 0x00000080 235 236#define AHCI_P_IX_PRC 0x00400000 237#define AHCI_P_IX_IPM 0x00800000 238#define AHCI_P_IX_OF 0x01000000 239#define AHCI_P_IX_INF 0x04000000 240#define AHCI_P_IX_IF 0x08000000 241#define AHCI_P_IX_HBD 0x10000000 242#define AHCI_P_IX_HBF 0x20000000 243#define AHCI_P_IX_TFE 0x40000000 244#define AHCI_P_IX_CPD 0x80000000 245 246#define AHCI_P_CMD 0x18 247#define AHCI_P_CMD_ST 0x00000001 248#define AHCI_P_CMD_SUD 0x00000002 249#define AHCI_P_CMD_POD 0x00000004 250#define AHCI_P_CMD_CLO 0x00000008 251#define AHCI_P_CMD_FRE 0x00000010 252#define AHCI_P_CMD_CCS_MASK 0x00001f00 253#define AHCI_P_CMD_CCS_SHIFT 8 254#define AHCI_P_CMD_ISS 0x00002000 255#define AHCI_P_CMD_FR 0x00004000 256#define AHCI_P_CMD_CR 0x00008000 257#define AHCI_P_CMD_CPS 0x00010000 258#define AHCI_P_CMD_PMA 0x00020000 259#define AHCI_P_CMD_HPCP 0x00040000 260#define AHCI_P_CMD_MPSP 0x00080000 261#define AHCI_P_CMD_CPD 0x00100000 262#define AHCI_P_CMD_ESP 0x00200000 263#define AHCI_P_CMD_FBSCP 0x00400000 264#define AHCI_P_CMD_APSTE 0x00800000 265#define AHCI_P_CMD_ATAPI 0x01000000 266#define AHCI_P_CMD_DLAE 0x02000000 267#define AHCI_P_CMD_ALPE 0x04000000 268#define AHCI_P_CMD_ASP 0x08000000 269#define AHCI_P_CMD_ICC_MASK 0xf0000000 270#define AHCI_P_CMD_NOOP 0x00000000 271#define AHCI_P_CMD_ACTIVE 0x10000000 272#define AHCI_P_CMD_PARTIAL 0x20000000 273#define AHCI_P_CMD_SLUMBER 0x60000000 274#define AHCI_P_CMD_DEVSLEEP 0x80000000 275 276#define AHCI_P_TFD 0x20 277#define AHCI_P_SIG 0x24 278#define AHCI_P_SSTS 0x28 279#define AHCI_P_SCTL 0x2c 280#define AHCI_P_SERR 0x30 281#define AHCI_P_SACT 0x34 282#define AHCI_P_CI 0x38 283#define AHCI_P_SNTF 0x3C 284#define AHCI_P_FBS 0x40 285#define AHCI_P_FBS_EN 0x00000001 286#define AHCI_P_FBS_DEC 0x00000002 287#define AHCI_P_FBS_SDE 0x00000004 288#define AHCI_P_FBS_DEV 0x00000f00 289#define AHCI_P_FBS_DEV_SHIFT 8 290#define AHCI_P_FBS_ADO 0x0000f000 291#define AHCI_P_FBS_ADO_SHIFT 12 292#define AHCI_P_FBS_DWE 0x000f0000 293#define AHCI_P_FBS_DWE_SHIFT 16 294#define AHCI_P_DEVSLP 0x44 295#define AHCI_P_DEVSLP_ADSE 0x00000001 296#define AHCI_P_DEVSLP_DSP 0x00000002 297#define AHCI_P_DEVSLP_DETO 0x000003fc 298#define AHCI_P_DEVSLP_DETO_SHIFT 2 299#define AHCI_P_DEVSLP_MDAT 0x00007c00 300#define AHCI_P_DEVSLP_MDAT_SHIFT 10 301#define AHCI_P_DEVSLP_DITO 0x01ff8000 302#define AHCI_P_DEVSLP_DITO_SHIFT 15 303#define AHCI_P_DEVSLP_DM 0x0e000000 304#define AHCI_P_DEVSLP_DM_SHIFT 25 305 306/* Just to be sure, if building as module. */ 307#if MAXPHYS < 512 * 1024 308#undef MAXPHYS 309#define MAXPHYS 512 * 1024 310#endif 311/* Pessimistic prognosis on number of required S/G entries */ 312#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8)) 313/* Command list. 32 commands. First, 1Kbyte aligned. */ 314#define AHCI_CL_OFFSET 0 315#define AHCI_CL_SIZE 32 316/* Command tables. Up to 32 commands, Each, 128byte aligned. */ 317#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS) 318#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16) 319/* Total main work area. */ 320#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots) 321 322#endif /* _AHCI_H_ */ 323