1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1996, by Peter Wemm and Steve Passe 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#ifndef _X86_APICREG_H_ 29#define _X86_APICREG_H_ 30 31/* 32 * Local && I/O APIC definitions. 33 */ 34 35/* 36 * Pentium P54C+ Built-in APIC 37 * (Advanced programmable Interrupt Controller) 38 * 39 * Base Address of Built-in APIC in memory location 40 * is 0xfee00000. 41 * 42 * Map of APIC Registers: 43 * 44 * Offset (hex) Description Read/Write state 45 * 000 Reserved 46 * 010 Reserved 47 * 020 ID Local APIC ID R/W 48 * 030 VER Local APIC Version R 49 * 040 Reserved 50 * 050 Reserved 51 * 060 Reserved 52 * 070 Reserved 53 * 080 Task Priority Register R/W 54 * 090 Arbitration Priority Register R 55 * 0A0 Processor Priority Register R 56 * 0B0 EOI Register W 57 * 0C0 RRR Remote read R 58 * 0D0 Logical Destination R/W 59 * 0E0 Destination Format Register 0..27 R; 28..31 R/W 60 * 0F0 SVR Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W 61 * 100 ISR 000-031 R 62 * 110 ISR 032-063 R 63 * 120 ISR 064-095 R 64 * 130 ISR 095-128 R 65 * 140 ISR 128-159 R 66 * 150 ISR 160-191 R 67 * 160 ISR 192-223 R 68 * 170 ISR 224-255 R 69 * 180 TMR 000-031 R 70 * 190 TMR 032-063 R 71 * 1A0 TMR 064-095 R 72 * 1B0 TMR 095-128 R 73 * 1C0 TMR 128-159 R 74 * 1D0 TMR 160-191 R 75 * 1E0 TMR 192-223 R 76 * 1F0 TMR 224-255 R 77 * 200 IRR 000-031 R 78 * 210 IRR 032-063 R 79 * 220 IRR 064-095 R 80 * 230 IRR 095-128 R 81 * 240 IRR 128-159 R 82 * 250 IRR 160-191 R 83 * 260 IRR 192-223 R 84 * 270 IRR 224-255 R 85 * 280 Error Status Register R 86 * 290 Reserved 87 * 2A0 Reserved 88 * 2B0 Reserved 89 * 2C0 Reserved 90 * 2D0 Reserved 91 * 2E0 Reserved 92 * 2F0 Local Vector Table (CMCI) R/W 93 * 300 ICR_LOW Interrupt Command Reg. (0-31) R/W 94 * 310 ICR_HI Interrupt Command Reg. (32-63) R/W 95 * 320 Local Vector Table (Timer) R/W 96 * 330 Local Vector Table (Thermal) R/W (PIV+) 97 * 340 Local Vector Table (Performance) R/W (P6+) 98 * 350 LVT1 Local Vector Table (LINT0) R/W 99 * 360 LVT2 Local Vector Table (LINT1) R/W 100 * 370 LVT3 Local Vector Table (ERROR) R/W 101 * 380 Initial Count Reg. for Timer R/W 102 * 390 Current Count of Timer R 103 * 3A0 Reserved 104 * 3B0 Reserved 105 * 3C0 Reserved 106 * 3D0 Reserved 107 * 3E0 Timer Divide Configuration Reg. R/W 108 * 3F0 Reserved 109 */ 110 111/****************************************************************************** 112 * global defines, etc. 113 */ 114 115/****************************************************************************** 116 * LOCAL APIC structure 117 */ 118 119#ifndef LOCORE 120#include <sys/types.h> 121 122#define PAD3 int : 32; int : 32; int : 32 123#define PAD4 int : 32; int : 32; int : 32; int : 32 124 125struct LAPIC { 126 /* reserved */ PAD4; 127 /* reserved */ PAD4; 128 u_int32_t id; PAD3; 129 u_int32_t version; PAD3; 130 /* reserved */ PAD4; 131 /* reserved */ PAD4; 132 /* reserved */ PAD4; 133 /* reserved */ PAD4; 134 u_int32_t tpr; PAD3; 135 u_int32_t apr; PAD3; 136 u_int32_t ppr; PAD3; 137 u_int32_t eoi; PAD3; 138 /* reserved */ PAD4; 139 u_int32_t ldr; PAD3; 140 u_int32_t dfr; PAD3; 141 u_int32_t svr; PAD3; 142 u_int32_t isr0; PAD3; 143 u_int32_t isr1; PAD3; 144 u_int32_t isr2; PAD3; 145 u_int32_t isr3; PAD3; 146 u_int32_t isr4; PAD3; 147 u_int32_t isr5; PAD3; 148 u_int32_t isr6; PAD3; 149 u_int32_t isr7; PAD3; 150 u_int32_t tmr0; PAD3; 151 u_int32_t tmr1; PAD3; 152 u_int32_t tmr2; PAD3; 153 u_int32_t tmr3; PAD3; 154 u_int32_t tmr4; PAD3; 155 u_int32_t tmr5; PAD3; 156 u_int32_t tmr6; PAD3; 157 u_int32_t tmr7; PAD3; 158 u_int32_t irr0; PAD3; 159 u_int32_t irr1; PAD3; 160 u_int32_t irr2; PAD3; 161 u_int32_t irr3; PAD3; 162 u_int32_t irr4; PAD3; 163 u_int32_t irr5; PAD3; 164 u_int32_t irr6; PAD3; 165 u_int32_t irr7; PAD3; 166 u_int32_t esr; PAD3; 167 /* reserved */ PAD4; 168 /* reserved */ PAD4; 169 /* reserved */ PAD4; 170 /* reserved */ PAD4; 171 /* reserved */ PAD4; 172 /* reserved */ PAD4; 173 u_int32_t lvt_cmci; PAD3; 174 u_int32_t icr_lo; PAD3; 175 u_int32_t icr_hi; PAD3; 176 u_int32_t lvt_timer; PAD3; 177 u_int32_t lvt_thermal; PAD3; 178 u_int32_t lvt_pcint; PAD3; 179 u_int32_t lvt_lint0; PAD3; 180 u_int32_t lvt_lint1; PAD3; 181 u_int32_t lvt_error; PAD3; 182 u_int32_t icr_timer; PAD3; 183 u_int32_t ccr_timer; PAD3; 184 /* reserved */ PAD4; 185 /* reserved */ PAD4; 186 /* reserved */ PAD4; 187 /* reserved */ PAD4; 188 u_int32_t dcr_timer; PAD3; 189 /* reserved */ PAD4; 190}; 191 192typedef struct LAPIC lapic_t; 193 194enum LAPIC_REGISTERS { 195 LAPIC_ID = 0x2, 196 LAPIC_VERSION = 0x3, 197 LAPIC_TPR = 0x8, 198 LAPIC_APR = 0x9, 199 LAPIC_PPR = 0xa, 200 LAPIC_EOI = 0xb, 201 LAPIC_LDR = 0xd, 202 LAPIC_DFR = 0xe, /* Not in x2APIC */ 203 LAPIC_SVR = 0xf, 204 LAPIC_ISR0 = 0x10, 205 LAPIC_ISR1 = 0x11, 206 LAPIC_ISR2 = 0x12, 207 LAPIC_ISR3 = 0x13, 208 LAPIC_ISR4 = 0x14, 209 LAPIC_ISR5 = 0x15, 210 LAPIC_ISR6 = 0x16, 211 LAPIC_ISR7 = 0x17, 212 LAPIC_TMR0 = 0x18, 213 LAPIC_TMR1 = 0x19, 214 LAPIC_TMR2 = 0x1a, 215 LAPIC_TMR3 = 0x1b, 216 LAPIC_TMR4 = 0x1c, 217 LAPIC_TMR5 = 0x1d, 218 LAPIC_TMR6 = 0x1e, 219 LAPIC_TMR7 = 0x1f, 220 LAPIC_IRR0 = 0x20, 221 LAPIC_IRR1 = 0x21, 222 LAPIC_IRR2 = 0x22, 223 LAPIC_IRR3 = 0x23, 224 LAPIC_IRR4 = 0x24, 225 LAPIC_IRR5 = 0x25, 226 LAPIC_IRR6 = 0x26, 227 LAPIC_IRR7 = 0x27, 228 LAPIC_ESR = 0x28, 229 LAPIC_LVT_CMCI = 0x2f, 230 LAPIC_ICR_LO = 0x30, 231 LAPIC_ICR_HI = 0x31, /* Not in x2APIC */ 232 LAPIC_LVT_TIMER = 0x32, 233 LAPIC_LVT_THERMAL = 0x33, 234 LAPIC_LVT_PCINT = 0x34, 235 LAPIC_LVT_LINT0 = 0x35, 236 LAPIC_LVT_LINT1 = 0x36, 237 LAPIC_LVT_ERROR = 0x37, 238 LAPIC_ICR_TIMER = 0x38, 239 LAPIC_CCR_TIMER = 0x39, 240 LAPIC_DCR_TIMER = 0x3e, 241 LAPIC_SELF_IPI = 0x3f, /* Only in x2APIC */ 242 LAPIC_EXT_FEATURES = 0x40, /* AMD */ 243 LAPIC_EXT_CTRL = 0x41, /* AMD */ 244 LAPIC_EXT_SEOI = 0x42, /* AMD */ 245 LAPIC_EXT_IER0 = 0x48, /* AMD */ 246 LAPIC_EXT_IER1 = 0x49, /* AMD */ 247 LAPIC_EXT_IER2 = 0x4a, /* AMD */ 248 LAPIC_EXT_IER3 = 0x4b, /* AMD */ 249 LAPIC_EXT_IER4 = 0x4c, /* AMD */ 250 LAPIC_EXT_IER5 = 0x4d, /* AMD */ 251 LAPIC_EXT_IER6 = 0x4e, /* AMD */ 252 LAPIC_EXT_IER7 = 0x4f, /* AMD */ 253 LAPIC_EXT_LVT0 = 0x50, /* AMD */ 254 LAPIC_EXT_LVT1 = 0x51, /* AMD */ 255 LAPIC_EXT_LVT2 = 0x52, /* AMD */ 256 LAPIC_EXT_LVT3 = 0x53, /* AMD */ 257}; 258 259#define LAPIC_MEM_MUL 0x10 260 261/* 262 * Although some registers are available on AMD processors only, 263 * it's not a big waste to reserve them on all platforms. 264 * However, we need to watch out for this space being assigned for 265 * non-APIC purposes in the future processor models. 266 */ 267#define LAPIC_MEM_REGION ((LAPIC_EXT_LVT3 + 1) * LAPIC_MEM_MUL) 268 269/****************************************************************************** 270 * I/O APIC structure 271 */ 272 273struct IOAPIC { 274 u_int32_t ioregsel; PAD3; 275 u_int32_t iowin; PAD3; 276}; 277 278typedef struct IOAPIC ioapic_t; 279 280#undef PAD4 281#undef PAD3 282 283#endif /* !LOCORE */ 284 285/****************************************************************************** 286 * various code 'logical' values 287 */ 288 289/****************************************************************************** 290 * LOCAL APIC defines 291 */ 292 293/* default physical locations of LOCAL (CPU) APICs */ 294#define DEFAULT_APIC_BASE 0xfee00000 295 296/* constants relating to APIC ID registers */ 297#define APIC_ID_MASK 0xff000000 298#define APIC_ID_SHIFT 24 299#define APIC_ID_CLUSTER 0xf0 300#define APIC_ID_CLUSTER_ID 0x0f 301#define APIC_MAX_CLUSTER 0xe 302#define APIC_MAX_INTRACLUSTER_ID 3 303#define APIC_ID_CLUSTER_SHIFT 4 304 305/* fields in VER */ 306#define APIC_VER_VERSION 0x000000ff 307#define APIC_VER_MAXLVT 0x00ff0000 308#define MAXLVTSHIFT 16 309#define APIC_VER_EOI_SUPPRESSION 0x01000000 310#define APIC_VER_AMD_EXT_SPACE 0x80000000 311 312/* fields in LDR */ 313#define APIC_LDR_RESERVED 0x00ffffff 314 315/* fields in DFR */ 316#define APIC_DFR_RESERVED 0x0fffffff 317#define APIC_DFR_MODEL_MASK 0xf0000000 318#define APIC_DFR_MODEL_FLAT 0xf0000000 319#define APIC_DFR_MODEL_CLUSTER 0x00000000 320 321/* fields in SVR */ 322#define APIC_SVR_VECTOR 0x000000ff 323#define APIC_SVR_VEC_PROG 0x000000f0 324#define APIC_SVR_VEC_FIX 0x0000000f 325#define APIC_SVR_ENABLE 0x00000100 326# define APIC_SVR_SWDIS 0x00000000 327# define APIC_SVR_SWEN 0x00000100 328#define APIC_SVR_FOCUS 0x00000200 329# define APIC_SVR_FEN 0x00000000 330# define APIC_SVR_FDIS 0x00000200 331#define APIC_SVR_EOI_SUPPRESSION 0x00001000 332 333/* fields in TPR */ 334#define APIC_TPR_PRIO 0x000000ff 335# define APIC_TPR_INT 0x000000f0 336# define APIC_TPR_SUB 0x0000000f 337 338/* fields in ESR */ 339#define APIC_ESR_SEND_CS_ERROR 0x00000001 340#define APIC_ESR_RECEIVE_CS_ERROR 0x00000002 341#define APIC_ESR_SEND_ACCEPT 0x00000004 342#define APIC_ESR_RECEIVE_ACCEPT 0x00000008 343#define APIC_ESR_SEND_ILLEGAL_VECTOR 0x00000020 344#define APIC_ESR_RECEIVE_ILLEGAL_VECTOR 0x00000040 345#define APIC_ESR_ILLEGAL_REGISTER 0x00000080 346 347/* fields in ICR_LOW */ 348#define APIC_VECTOR_MASK 0x000000ff 349 350#define APIC_DELMODE_MASK 0x00000700 351# define APIC_DELMODE_FIXED 0x00000000 352# define APIC_DELMODE_LOWPRIO 0x00000100 353# define APIC_DELMODE_SMI 0x00000200 354# define APIC_DELMODE_RR 0x00000300 355# define APIC_DELMODE_NMI 0x00000400 356# define APIC_DELMODE_INIT 0x00000500 357# define APIC_DELMODE_STARTUP 0x00000600 358# define APIC_DELMODE_RESV 0x00000700 359 360#define APIC_DESTMODE_MASK 0x00000800 361# define APIC_DESTMODE_PHY 0x00000000 362# define APIC_DESTMODE_LOG 0x00000800 363 364#define APIC_DELSTAT_MASK 0x00001000 365# define APIC_DELSTAT_IDLE 0x00000000 366# define APIC_DELSTAT_PEND 0x00001000 367 368#define APIC_RESV1_MASK 0x00002000 369 370#define APIC_LEVEL_MASK 0x00004000 371# define APIC_LEVEL_DEASSERT 0x00000000 372# define APIC_LEVEL_ASSERT 0x00004000 373 374#define APIC_TRIGMOD_MASK 0x00008000 375# define APIC_TRIGMOD_EDGE 0x00000000 376# define APIC_TRIGMOD_LEVEL 0x00008000 377 378#define APIC_RRSTAT_MASK 0x00030000 379# define APIC_RRSTAT_INVALID 0x00000000 380# define APIC_RRSTAT_INPROG 0x00010000 381# define APIC_RRSTAT_VALID 0x00020000 382# define APIC_RRSTAT_RESV 0x00030000 383 384#define APIC_DEST_MASK 0x000c0000 385# define APIC_DEST_DESTFLD 0x00000000 386# define APIC_DEST_SELF 0x00040000 387# define APIC_DEST_ALLISELF 0x00080000 388# define APIC_DEST_ALLESELF 0x000c0000 389 390#define APIC_RESV2_MASK 0xfff00000 391 392#define APIC_ICRLO_RESV_MASK (APIC_RESV1_MASK | APIC_RESV2_MASK) 393 394/* fields in LVT1/2 */ 395#define APIC_LVT_VECTOR 0x000000ff 396#define APIC_LVT_DM 0x00000700 397# define APIC_LVT_DM_FIXED 0x00000000 398# define APIC_LVT_DM_SMI 0x00000200 399# define APIC_LVT_DM_NMI 0x00000400 400# define APIC_LVT_DM_INIT 0x00000500 401# define APIC_LVT_DM_EXTINT 0x00000700 402#define APIC_LVT_DS 0x00001000 403#define APIC_LVT_IIPP 0x00002000 404#define APIC_LVT_IIPP_INTALO 0x00002000 405#define APIC_LVT_IIPP_INTAHI 0x00000000 406#define APIC_LVT_RIRR 0x00004000 407#define APIC_LVT_TM 0x00008000 408#define APIC_LVT_M 0x00010000 409 410/* fields in LVT Timer */ 411#define APIC_LVTT_VECTOR 0x000000ff 412#define APIC_LVTT_DS 0x00001000 413#define APIC_LVTT_M 0x00010000 414#define APIC_LVTT_TM 0x00060000 415# define APIC_LVTT_TM_ONE_SHOT 0x00000000 416# define APIC_LVTT_TM_PERIODIC 0x00020000 417# define APIC_LVTT_TM_TSCDLT 0x00040000 418# define APIC_LVTT_TM_RSRV 0x00060000 419 420/* APIC timer current count */ 421#define APIC_TIMER_MAX_COUNT 0xffffffff 422 423/* fields in TDCR */ 424#define APIC_TDCR_2 0x00 425#define APIC_TDCR_4 0x01 426#define APIC_TDCR_8 0x02 427#define APIC_TDCR_16 0x03 428#define APIC_TDCR_32 0x08 429#define APIC_TDCR_64 0x09 430#define APIC_TDCR_128 0x0a 431#define APIC_TDCR_1 0x0b 432 433/* Constants related to AMD Extended APIC Features Register */ 434#define APIC_EXTF_ELVT_MASK 0x00ff0000 435#define APIC_EXTF_ELVT_SHIFT 16 436#define APIC_EXTF_EXTID_CAP 0x00000004 437#define APIC_EXTF_SEIO_CAP 0x00000002 438#define APIC_EXTF_IER_CAP 0x00000001 439 440/* LVT table indices */ 441#define APIC_LVT_LINT0 0 442#define APIC_LVT_LINT1 1 443#define APIC_LVT_TIMER 2 444#define APIC_LVT_ERROR 3 445#define APIC_LVT_PMC 4 446#define APIC_LVT_THERMAL 5 447#define APIC_LVT_CMCI 6 448#define APIC_LVT_MAX APIC_LVT_CMCI 449 450/* AMD extended LVT constants, seem to be assigned by fiat */ 451#define APIC_ELVT_IBS 0 /* Instruction based sampling */ 452#define APIC_ELVT_MCA 1 /* MCE thresholding */ 453#define APIC_ELVT_DEI 2 /* Deferred error interrupt */ 454#define APIC_ELVT_SBI 3 /* Sideband interface */ 455#define APIC_ELVT_MAX APIC_ELVT_SBI 456 457/****************************************************************************** 458 * I/O APIC defines 459 */ 460 461/* default physical locations of an IO APIC */ 462#define DEFAULT_IO_APIC_BASE 0xfec00000 463 464/* window register offset */ 465#define IOAPIC_WINDOW 0x10 466#define IOAPIC_EOIR 0x40 467 468#define IOAPIC_WND_SIZE 0x50 469 470/* indexes into IO APIC */ 471#define IOAPIC_ID 0x00 472#define IOAPIC_VER 0x01 473#define IOAPIC_ARB 0x02 474#define IOAPIC_REDTBL 0x10 475#define IOAPIC_REDTBL0 IOAPIC_REDTBL 476#define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02) 477#define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04) 478#define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06) 479#define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08) 480#define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a) 481#define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c) 482#define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e) 483#define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10) 484#define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12) 485#define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14) 486#define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16) 487#define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18) 488#define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a) 489#define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c) 490#define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e) 491#define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20) 492#define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22) 493#define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24) 494#define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26) 495#define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28) 496#define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a) 497#define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c) 498#define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e) 499 500/* fields in VER */ 501#define IOART_VER_VERSION 0x000000ff 502#define IOART_VER_MAXREDIR 0x00ff0000 503#define MAXREDIRSHIFT 16 504 505/* 506 * fields in the IO APIC's redirection table entries 507 */ 508#define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */ 509 510#define IOART_RESV 0x00fe0000 /* reserved */ 511 512#define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */ 513# define IOART_INTMCLR 0x00000000 /* clear, allow INTs */ 514# define IOART_INTMSET 0x00010000 /* set, inhibit INTs */ 515 516#define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */ 517# define IOART_TRGREDG 0x00000000 /* edge */ 518# define IOART_TRGRLVL 0x00008000 /* level */ 519 520#define IOART_REM_IRR 0x00004000 /* RO: remote IRR */ 521 522#define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */ 523# define IOART_INTAHI 0x00000000 /* active high */ 524# define IOART_INTALO 0x00002000 /* active low */ 525 526#define IOART_DELIVS 0x00001000 /* RO: delivery status */ 527 528#define IOART_DESTMOD 0x00000800 /* R/W: destination mode */ 529# define IOART_DESTPHY 0x00000000 /* physical */ 530# define IOART_DESTLOG 0x00000800 /* logical */ 531 532#define IOART_DELMOD 0x00000700 /* R/W: delivery mode */ 533# define IOART_DELFIXED 0x00000000 /* fixed */ 534# define IOART_DELLOPRI 0x00000100 /* lowest priority */ 535# define IOART_DELSMI 0x00000200 /* System Management INT */ 536# define IOART_DELRSV1 0x00000300 /* reserved */ 537# define IOART_DELNMI 0x00000400 /* NMI signal */ 538# define IOART_DELINIT 0x00000500 /* INIT signal */ 539# define IOART_DELRSV2 0x00000600 /* reserved */ 540# define IOART_DELEXINT 0x00000700 /* External INTerrupt */ 541 542#define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */ 543 544#endif /* _X86_APICREG_H_ */ 545