1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2005 Nate Lawson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Throttle clock frequency by using the thermal control circuit. This 31 * operates independently of SpeedStep and ACPI throttling and is supported 32 * on Pentium 4 and later models (feature TM). 33 * 34 * Reference: Intel Developer's manual v.3 #245472-012 35 * 36 * The original version of this driver was written by Ted Unangst for 37 * OpenBSD and imported by Maxim Sobolev. It was rewritten by Nate Lawson 38 * for use with the cpufreq framework. 39 */ 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/cpu.h> 45#include <sys/kernel.h> 46#include <sys/module.h> 47 48#include <machine/md_var.h> 49#include <machine/specialreg.h> 50 51#include "cpufreq_if.h" 52 53#include <contrib/dev/acpica/include/acpi.h> 54 55#include <dev/acpica/acpivar.h> 56#include "acpi_if.h" 57 58struct p4tcc_softc { 59 device_t dev; 60 int set_count; 61 int lowest_val; 62 int auto_mode; 63}; 64 65#define TCC_NUM_SETTINGS 8 66 67#define TCC_ENABLE_ONDEMAND (1<<4) 68#define TCC_REG_OFFSET 1 69#define TCC_SPEED_PERCENT(x) ((10000 * (x)) / TCC_NUM_SETTINGS) 70 71static int p4tcc_features(driver_t *driver, u_int *features); 72static void p4tcc_identify(driver_t *driver, device_t parent); 73static int p4tcc_probe(device_t dev); 74static int p4tcc_attach(device_t dev); 75static int p4tcc_detach(device_t dev); 76static int p4tcc_settings(device_t dev, struct cf_setting *sets, 77 int *count); 78static int p4tcc_set(device_t dev, const struct cf_setting *set); 79static int p4tcc_get(device_t dev, struct cf_setting *set); 80static int p4tcc_type(device_t dev, int *type); 81 82static device_method_t p4tcc_methods[] = { 83 /* Device interface */ 84 DEVMETHOD(device_identify, p4tcc_identify), 85 DEVMETHOD(device_probe, p4tcc_probe), 86 DEVMETHOD(device_attach, p4tcc_attach), 87 DEVMETHOD(device_detach, p4tcc_detach), 88 89 /* cpufreq interface */ 90 DEVMETHOD(cpufreq_drv_set, p4tcc_set), 91 DEVMETHOD(cpufreq_drv_get, p4tcc_get), 92 DEVMETHOD(cpufreq_drv_type, p4tcc_type), 93 DEVMETHOD(cpufreq_drv_settings, p4tcc_settings), 94 95 /* ACPI interface */ 96 DEVMETHOD(acpi_get_features, p4tcc_features), 97 {0, 0} 98}; 99 100static driver_t p4tcc_driver = { 101 "p4tcc", 102 p4tcc_methods, 103 sizeof(struct p4tcc_softc), 104}; 105 106DRIVER_MODULE(p4tcc, cpu, p4tcc_driver, 0, 0); 107 108static int 109p4tcc_features(driver_t *driver, u_int *features) 110{ 111 112 /* Notify the ACPI CPU that we support direct access to MSRs */ 113 *features = ACPI_CAP_THR_MSRS; 114 return (0); 115} 116 117static void 118p4tcc_identify(driver_t *driver, device_t parent) 119{ 120 121 if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM)) 122 return; 123 124 /* Make sure we're not being doubly invoked. */ 125 if (device_find_child(parent, "p4tcc", -1) != NULL) 126 return; 127 128 /* 129 * We attach a p4tcc child for every CPU since settings need to 130 * be performed on every CPU in the SMP case. See section 13.15.3 131 * of the IA32 Intel Architecture Software Developer's Manual, 132 * Volume 3, for more info. 133 */ 134 if (BUS_ADD_CHILD(parent, 10, "p4tcc", device_get_unit(parent)) 135 == NULL) 136 device_printf(parent, "add p4tcc child failed\n"); 137} 138 139static int 140p4tcc_probe(device_t dev) 141{ 142 143 if (resource_disabled("p4tcc", 0)) 144 return (ENXIO); 145 146 device_set_desc(dev, "CPU Frequency Thermal Control"); 147 return (0); 148} 149 150static int 151p4tcc_attach(device_t dev) 152{ 153 struct p4tcc_softc *sc; 154 struct cf_setting set; 155 156 sc = device_get_softc(dev); 157 sc->dev = dev; 158 sc->set_count = TCC_NUM_SETTINGS; 159 160 /* 161 * On boot, the TCC is usually in Automatic mode where reading the 162 * current performance level is likely to produce bogus results. 163 * We record that state here and don't trust the contents of the 164 * status MSR until we've set it ourselves. 165 */ 166 sc->auto_mode = TRUE; 167 168 /* 169 * XXX: After a cursory glance at various Intel specification 170 * XXX: updates it seems like these tests for errata is bogus. 171 * XXX: As far as I can tell, the failure mode is benign, in 172 * XXX: that cpus with no errata will have their bottom two 173 * XXX: STPCLK# rates disabled, so rather than waste more time 174 * XXX: hunting down intel docs, just document it and punt. /phk 175 */ 176 switch (cpu_id & 0xff) { 177 case 0x22: 178 case 0x24: 179 case 0x25: 180 case 0x27: 181 case 0x29: 182 /* 183 * These CPU models hang when set to 12.5%. 184 * See Errata O50, P44, and Z21. 185 */ 186 sc->set_count -= 1; 187 break; 188 case 0x07: /* errata N44 and P18 */ 189 case 0x0a: 190 case 0x12: 191 case 0x13: 192 case 0x62: /* Pentium D B1: errata AA21 */ 193 case 0x64: /* Pentium D C1: errata AA21 */ 194 case 0x65: /* Pentium D D0: errata AA21 */ 195 /* 196 * These CPU models hang when set to 12.5% or 25%. 197 * See Errata N44, P18l and AA21. 198 */ 199 sc->set_count -= 2; 200 break; 201 } 202 sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1; 203 204 /* 205 * Before we finish attach, switch to 100%. It's possible the BIOS 206 * set us to a lower rate. The user can override this after boot. 207 */ 208 set.freq = 10000; 209 p4tcc_set(dev, &set); 210 211 cpufreq_register(dev); 212 return (0); 213} 214 215static int 216p4tcc_detach(device_t dev) 217{ 218 struct cf_setting set; 219 int error; 220 221 error = cpufreq_unregister(dev); 222 if (error) 223 return (error); 224 225 /* 226 * Before we finish detach, switch to Automatic mode. 227 */ 228 set.freq = 10000; 229 p4tcc_set(dev, &set); 230 return(0); 231} 232 233static int 234p4tcc_settings(device_t dev, struct cf_setting *sets, int *count) 235{ 236 struct p4tcc_softc *sc; 237 int i, val; 238 239 sc = device_get_softc(dev); 240 if (sets == NULL || count == NULL) 241 return (EINVAL); 242 if (*count < sc->set_count) 243 return (E2BIG); 244 245 /* Return a list of valid settings for this driver. */ 246 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count); 247 val = TCC_NUM_SETTINGS; 248 for (i = 0; i < sc->set_count; i++, val--) { 249 sets[i].freq = TCC_SPEED_PERCENT(val); 250 sets[i].dev = dev; 251 } 252 *count = sc->set_count; 253 254 return (0); 255} 256 257static int 258p4tcc_set(device_t dev, const struct cf_setting *set) 259{ 260 struct p4tcc_softc *sc; 261 uint64_t mask, msr; 262 int val; 263 264 if (set == NULL) 265 return (EINVAL); 266 sc = device_get_softc(dev); 267 268 /* 269 * Validate requested state converts to a setting that is an integer 270 * from [sc->lowest_val .. TCC_NUM_SETTINGS]. 271 */ 272 val = set->freq * TCC_NUM_SETTINGS / 10000; 273 if (val * 10000 != set->freq * TCC_NUM_SETTINGS || 274 val < sc->lowest_val || val > TCC_NUM_SETTINGS) 275 return (EINVAL); 276 277 /* 278 * Read the current register and mask off the old setting and 279 * On-Demand bit. If the new val is < 100%, set it and the On-Demand 280 * bit, otherwise just return to Automatic mode. 281 */ 282 msr = rdmsr(MSR_THERM_CONTROL); 283 mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET; 284 msr &= ~(mask | TCC_ENABLE_ONDEMAND); 285 if (val < TCC_NUM_SETTINGS) 286 msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND; 287 wrmsr(MSR_THERM_CONTROL, msr); 288 289 /* 290 * Record whether we're now in Automatic or On-Demand mode. We have 291 * to cache this since there is no reliable way to check if TCC is in 292 * Automatic mode (i.e., at 100% or possibly 50%). Reading bit 4 of 293 * the ACPI Thermal Monitor Control Register produces 0 no matter 294 * what the current mode. 295 */ 296 if (msr & TCC_ENABLE_ONDEMAND) 297 sc->auto_mode = FALSE; 298 else 299 sc->auto_mode = TRUE; 300 301 return (0); 302} 303 304static int 305p4tcc_get(device_t dev, struct cf_setting *set) 306{ 307 struct p4tcc_softc *sc; 308 uint64_t msr; 309 int val; 310 311 if (set == NULL) 312 return (EINVAL); 313 sc = device_get_softc(dev); 314 315 /* 316 * Read the current register and extract the current setting. If 317 * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%). 318 * 319 * XXX This is not completely reliable since at high temperatures 320 * the CPU may be automatically throttling to 50% but it's the best 321 * we can do. 322 */ 323 if (!sc->auto_mode) { 324 msr = rdmsr(MSR_THERM_CONTROL); 325 val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1); 326 } else 327 val = TCC_NUM_SETTINGS; 328 329 memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set)); 330 set->freq = TCC_SPEED_PERCENT(val); 331 set->dev = dev; 332 333 return (0); 334} 335 336static int 337p4tcc_type(device_t dev, int *type) 338{ 339 340 if (type == NULL) 341 return (EINVAL); 342 343 *type = CPUFREQ_TYPE_RELATIVE; 344 return (0); 345} 346