1 2/*- 3 * Copyright (c) 2006,2007 4 * Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19#define WPI_TX_RING_COUNT 256 20#define WPI_TX_RING_LOMARK 192 21#define WPI_TX_RING_HIMARK 224 22 23#ifdef DIAGNOSTIC 24#define WPI_RX_RING_COUNT_LOG 8 25#else 26#define WPI_RX_RING_COUNT_LOG 6 27#endif 28 29#define WPI_RX_RING_COUNT (1 << WPI_RX_RING_COUNT_LOG) 30 31#define WPI_NTXQUEUES 8 32#define WPI_DRV_NTXQUEUES 5 33#define WPI_CMD_QUEUE_NUM 4 34 35#define WPI_NDMACHNLS 6 36 37/* Maximum scatter/gather. */ 38#define WPI_MAX_SCATTER 4 39 40/* 41 * Rings must be aligned on a 16K boundary. 42 */ 43#define WPI_RING_DMA_ALIGN 0x4000 44 45/* Maximum Rx buffer size. */ 46#define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */ 47 48/* 49 * Control and status registers. 50 */ 51#define WPI_HW_IF_CONFIG 0x000 52#define WPI_INT 0x008 53#define WPI_INT_MASK 0x00c 54#define WPI_FH_INT 0x010 55#define WPI_GPIO_IN 0x018 56#define WPI_RESET 0x020 57#define WPI_GP_CNTRL 0x024 58#define WPI_EEPROM 0x02c 59#define WPI_EEPROM_GP 0x030 60#define WPI_GIO 0x03c 61#define WPI_UCODE_GP1 0x054 62#define WPI_UCODE_GP1_SET 0x058 63#define WPI_UCODE_GP1_CLR 0x05c 64#define WPI_UCODE_GP2 0x060 65#define WPI_GIO_CHICKEN 0x100 66#define WPI_ANA_PLL 0x20c 67#define WPI_DBG_HPET_MEM 0x240 68#define WPI_MEM_RADDR 0x40c 69#define WPI_MEM_WADDR 0x410 70#define WPI_MEM_WDATA 0x418 71#define WPI_MEM_RDATA 0x41c 72#define WPI_PRPH_WADDR 0x444 73#define WPI_PRPH_RADDR 0x448 74#define WPI_PRPH_WDATA 0x44c 75#define WPI_PRPH_RDATA 0x450 76#define WPI_HBUS_TARG_WRPTR 0x460 77 78/* 79 * Flow-Handler registers. 80 */ 81#define WPI_FH_CBBC_CTRL(qid) (0x940 + (qid) * 8) 82#define WPI_FH_CBBC_BASE(qid) (0x944 + (qid) * 8) 83#define WPI_FH_RX_CONFIG 0xc00 84#define WPI_FH_RX_BASE 0xc04 85#define WPI_FH_RX_WPTR 0xc20 86#define WPI_FH_RX_RPTR_ADDR 0xc24 87#define WPI_FH_RSSR_TBL 0xcc0 88#define WPI_FH_RX_STATUS 0xcc4 89#define WPI_FH_TX_CONFIG(qid) (0xd00 + (qid) * 32) 90#define WPI_FH_TX_BASE 0xe80 91#define WPI_FH_MSG_CONFIG 0xe88 92#define WPI_FH_TX_STATUS 0xe90 93 94/* 95 * NIC internal memory offsets. 96 */ 97#define WPI_ALM_SCHED_MODE 0x2e00 98#define WPI_ALM_SCHED_ARASTAT 0x2e04 99#define WPI_ALM_SCHED_TXFACT 0x2e10 100#define WPI_ALM_SCHED_TXF4MF 0x2e14 101#define WPI_ALM_SCHED_TXF5MF 0x2e20 102#define WPI_ALM_SCHED_SBYPASS_MODE1 0x2e2c 103#define WPI_ALM_SCHED_SBYPASS_MODE2 0x2e30 104#define WPI_APMG_CLK_CTRL 0x3000 105#define WPI_APMG_CLK_EN 0x3004 106#define WPI_APMG_CLK_DIS 0x3008 107#define WPI_APMG_PS 0x300c 108#define WPI_APMG_PCI_STT 0x3010 109#define WPI_APMG_RFKILL 0x3014 110#define WPI_BSM_WR_CTRL 0x3400 111#define WPI_BSM_WR_MEM_SRC 0x3404 112#define WPI_BSM_WR_MEM_DST 0x3408 113#define WPI_BSM_WR_DWCOUNT 0x340c 114#define WPI_BSM_DRAM_TEXT_ADDR 0x3490 115#define WPI_BSM_DRAM_TEXT_SIZE 0x3494 116#define WPI_BSM_DRAM_DATA_ADDR 0x3498 117#define WPI_BSM_DRAM_DATA_SIZE 0x349c 118#define WPI_BSM_SRAM_BASE 0x3800 119 120/* Possible flags for register WPI_HW_IF_CONFIG. */ 121#define WPI_HW_IF_CONFIG_ALM_MB (1 << 8) 122#define WPI_HW_IF_CONFIG_ALM_MM (1 << 9) 123#define WPI_HW_IF_CONFIG_SKU_MRC (1 << 10) 124#define WPI_HW_IF_CONFIG_REV_D (1 << 11) 125#define WPI_HW_IF_CONFIG_TYPE_B (1 << 12) 126 127/* Possible flags for registers WPI_PRPH_RADDR/WPI_PRPH_WADDR. */ 128#define WPI_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 129 130/* Possible values for WPI_BSM_WR_MEM_DST. */ 131#define WPI_FW_TEXT_BASE 0x00000000 132#define WPI_FW_DATA_BASE 0x00800000 133 134/* Possible flags for WPI_GPIO_IN. */ 135#define WPI_GPIO_IN_VMAIN (1 << 9) 136 137/* Possible flags for register WPI_RESET. */ 138#define WPI_RESET_NEVO (1 << 0) 139#define WPI_RESET_SW (1 << 7) 140#define WPI_RESET_MASTER_DISABLED (1 << 8) 141#define WPI_RESET_STOP_MASTER (1 << 9) 142 143/* Possible flags for register WPI_GP_CNTRL. */ 144#define WPI_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 145#define WPI_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 146#define WPI_GP_CNTRL_INIT_DONE (1 << 2) 147#define WPI_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 148#define WPI_GP_CNTRL_SLEEP (1 << 4) 149#define WPI_GP_CNTRL_PS_MASK (7 << 24) 150#define WPI_GP_CNTRL_MAC_PS (4 << 24) 151#define WPI_GP_CNTRL_RFKILL (1 << 27) 152 153/* Possible flags for register WPI_GIO_CHICKEN. */ 154#define WPI_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 155#define WPI_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 156 157/* Possible flags for register WPI_GIO. */ 158#define WPI_GIO_L0S_ENA (1 << 1) 159 160/* Possible flags for register WPI_FH_RX_CONFIG. */ 161#define WPI_FH_RX_CONFIG_DMA_ENA (1U << 31) 162#define WPI_FH_RX_CONFIG_RDRBD_ENA (1 << 29) 163#define WPI_FH_RX_CONFIG_WRSTATUS_ENA (1 << 27) 164#define WPI_FH_RX_CONFIG_MAXFRAG (1 << 24) 165#define WPI_FH_RX_CONFIG_NRBD(x) ((x) << 20) 166#define WPI_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 167#define WPI_FH_RX_CONFIG_IRQ_TIMEOUT(x) ((x) << 4) 168 169/* Possible flags for register WPI_ANA_PLL. */ 170#define WPI_ANA_PLL_INIT (1 << 24) 171 172/* Possible flags for register WPI_UCODE_GP1*. */ 173#define WPI_UCODE_GP1_MAC_SLEEP (1 << 0) 174#define WPI_UCODE_GP1_RFKILL (1 << 1) 175#define WPI_UCODE_GP1_CMD_BLOCKED (1 << 2) 176 177/* Possible flags for register WPI_FH_RX_STATUS. */ 178#define WPI_FH_RX_STATUS_IDLE (1 << 24) 179 180/* Possible flags for register WPI_BSM_WR_CTRL. */ 181#define WPI_BSM_WR_CTRL_START_EN (1 << 30) 182#define WPI_BSM_WR_CTRL_START (1U << 31) 183 184/* Possible flags for register WPI_INT. */ 185#define WPI_INT_ALIVE (1 << 0) 186#define WPI_INT_WAKEUP (1 << 1) 187#define WPI_INT_SW_RX (1 << 3) 188#define WPI_INT_SW_ERR (1 << 25) 189#define WPI_INT_FH_TX (1 << 27) 190#define WPI_INT_HW_ERR (1 << 29) 191#define WPI_INT_FH_RX (1U << 31) 192 193/* Shortcut. */ 194#define WPI_INT_MASK_DEF \ 195 (WPI_INT_SW_ERR | WPI_INT_HW_ERR | WPI_INT_FH_TX | \ 196 WPI_INT_FH_RX | WPI_INT_ALIVE | WPI_INT_WAKEUP | \ 197 WPI_INT_SW_RX) 198 199/* Possible flags for register WPI_FH_INT. */ 200#define WPI_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 201#define WPI_FH_INT_HI_PRIOR (1 << 30) 202/* Shortcuts for the above. */ 203#define WPI_FH_INT_RX \ 204 (WPI_FH_INT_RX_CHNL(0) | \ 205 WPI_FH_INT_RX_CHNL(1) | \ 206 WPI_FH_INT_RX_CHNL(2) | \ 207 WPI_FH_INT_HI_PRIOR) 208 209/* Possible flags for register WPI_FH_TX_STATUS. */ 210#define WPI_FH_TX_STATUS_IDLE(qid) \ 211 (1 << ((qid) + 24) | 1 << ((qid) + 16)) 212 213/* Possible flags for register WPI_EEPROM. */ 214#define WPI_EEPROM_READ_VALID (1 << 0) 215 216/* Possible flags for register WPI_EEPROM_GP. */ 217#define WPI_EEPROM_VERSION 0x00000007 218#define WPI_EEPROM_GP_IF_OWNER 0x00000180 219 220/* Possible flags for register WPI_APMG_PS. */ 221#define WPI_APMG_PS_PWR_SRC_MASK (3 << 24) 222 223/* Possible flags for registers WPI_APMG_CLK_*. */ 224#define WPI_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 225#define WPI_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 226 227/* Possible flags for register WPI_APMG_PCI_STT. */ 228#define WPI_APMG_PCI_STT_L1A_DIS (1 << 11) 229 230struct wpi_shared { 231 uint32_t txbase[WPI_NTXQUEUES]; 232 uint32_t next; 233 uint32_t reserved[2]; 234} __packed; 235 236#define WPI_MAX_SEG_LEN 65520 237struct wpi_tx_desc { 238 uint8_t reserved1[3]; 239 uint8_t nsegs; 240#define WPI_PAD32(x) (roundup2(x, 4) - (x)) 241 242 struct { 243 uint32_t addr; 244 uint32_t len; 245 } __packed segs[WPI_MAX_SCATTER]; 246 uint8_t reserved2[28]; 247} __packed; 248 249struct wpi_tx_stat { 250 uint8_t rtsfailcnt; 251 uint8_t ackfailcnt; 252 uint8_t btkillcnt; 253 uint8_t rate; 254 uint32_t duration; 255 uint32_t status; 256#define WPI_TX_STATUS_SUCCESS 0x01 257#define WPI_TX_STATUS_DIRECT_DONE 0x02 258#define WPI_TX_STATUS_FAIL 0x80 259#define WPI_TX_STATUS_FAIL_SHORT_LIMIT 0x82 260#define WPI_TX_STATUS_FAIL_LONG_LIMIT 0x83 261#define WPI_TX_STATUS_FAIL_FIFO_UNDERRUN 0x84 262#define WPI_TX_STATUS_FAIL_MGMNT_ABORT 0x85 263#define WPI_TX_STATUS_FAIL_NEXT_FRAG 0x86 264#define WPI_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 265#define WPI_TX_STATUS_FAIL_NODE_PS 0x88 266#define WPI_TX_STATUS_FAIL_ABORTED 0x89 267#define WPI_TX_STATUS_FAIL_BT_RETRY 0x8a 268#define WPI_TX_STATUS_FAIL_NODE_INVALID 0x8b 269#define WPI_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 270#define WPI_TX_STATUS_FAIL_TID_DISABLE 0x8d 271#define WPI_TX_STATUS_FAIL_FRAME_FLUSHED 0x8e 272#define WPI_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f 273#define WPI_TX_STATUS_FAIL_TX_LOCKED 0x90 274#define WPI_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91 275 276} __packed; 277 278struct wpi_rx_desc { 279 uint32_t len; 280 uint8_t type; 281#define WPI_UC_READY 1 282#define WPI_RX_DONE 27 283#define WPI_TX_DONE 28 284#define WPI_START_SCAN 130 285#define WPI_SCAN_RESULTS 131 286#define WPI_STOP_SCAN 132 287#define WPI_BEACON_SENT 144 288#define WPI_RX_STATISTICS 156 289#define WPI_BEACON_STATISTICS 157 290#define WPI_STATE_CHANGED 161 291#define WPI_BEACON_MISSED 162 292 293 uint8_t flags; 294 uint8_t idx; 295 uint8_t qid; 296} __packed; 297 298#define WPI_RX_DESC_QID_MSK 0x07 299#define WPI_UNSOLICITED_RX_NOTIF 0x80 300 301struct wpi_rx_stat { 302 uint8_t len; 303#define WPI_STAT_MAXLEN 20 304 305 uint8_t id; 306 uint8_t rssi; /* received signal strength */ 307#define WPI_RSSI_OFFSET -95 308 309 uint8_t agc; /* access gain control */ 310 uint16_t signal; 311 uint16_t noise; 312} __packed; 313 314struct wpi_rx_head { 315 uint16_t chan; 316 uint16_t flags; 317#define WPI_STAT_FLAG_SHPREAMBLE (1 << 2) 318 319 uint8_t reserved; 320 uint8_t plcp; 321 uint16_t len; 322} __packed; 323 324struct wpi_rx_tail { 325 uint32_t flags; 326#define WPI_RX_NO_CRC_ERR (1 << 0) 327#define WPI_RX_NO_OVFL_ERR (1 << 1) 328/* shortcut for the above */ 329#define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 330#define WPI_RX_CIPHER_MASK (7 << 8) 331#define WPI_RX_CIPHER_CCMP (2 << 8) 332#define WPI_RX_DECRYPT_MASK (3 << 11) 333#define WPI_RX_DECRYPT_OK (3 << 11) 334 335 uint64_t tstamp; 336 uint32_t tbeacon; 337} __packed; 338 339struct wpi_tx_cmd { 340 uint8_t code; 341#define WPI_CMD_RXON 16 342#define WPI_CMD_RXON_ASSOC 17 343#define WPI_CMD_EDCA_PARAMS 19 344#define WPI_CMD_TIMING 20 345#define WPI_CMD_ADD_NODE 24 346#define WPI_CMD_DEL_NODE 25 347#define WPI_CMD_TX_DATA 28 348#define WPI_CMD_MRR_SETUP 71 349#define WPI_CMD_SET_LED 72 350#define WPI_CMD_SET_POWER_MODE 119 351#define WPI_CMD_SCAN 128 352#define WPI_CMD_SCAN_ABORT 129 353#define WPI_CMD_SET_BEACON 145 354#define WPI_CMD_TXPOWER 151 355#define WPI_CMD_BT_COEX 155 356#define WPI_CMD_GET_STATISTICS 156 357 358 uint8_t flags; 359 uint8_t idx; 360 uint8_t qid; 361 uint8_t data[124]; 362} __packed; 363 364/* Structure for command WPI_CMD_RXON. */ 365struct wpi_rxon { 366 uint8_t myaddr[IEEE80211_ADDR_LEN]; 367 uint16_t reserved1; 368 uint8_t bssid[IEEE80211_ADDR_LEN]; 369 uint16_t reserved2; 370 uint8_t wlap[IEEE80211_ADDR_LEN]; 371 uint16_t reserved3; 372 uint8_t mode; 373#define WPI_MODE_HOSTAP 1 374#define WPI_MODE_STA 3 375#define WPI_MODE_IBSS 4 376#define WPI_MODE_MONITOR 6 377 378 uint8_t air; 379 uint16_t reserved4; 380 uint8_t ofdm_mask; 381 uint8_t cck_mask; 382 uint16_t associd; 383 uint32_t flags; 384#define WPI_RXON_24GHZ (1 << 0) 385#define WPI_RXON_CCK (1 << 1) 386#define WPI_RXON_AUTO (1 << 2) 387#define WPI_RXON_SHSLOT (1 << 4) 388#define WPI_RXON_SHPREAMBLE (1 << 5) 389#define WPI_RXON_NODIVERSITY (1 << 7) 390#define WPI_RXON_ANTENNA_A (1 << 8) 391#define WPI_RXON_ANTENNA_B (1 << 9) 392#define WPI_RXON_TSF (1 << 15) 393#define WPI_RXON_CTS_TO_SELF (1 << 30) 394 395 uint32_t filter; 396#define WPI_FILTER_PROMISC (1 << 0) 397#define WPI_FILTER_CTL (1 << 1) 398#define WPI_FILTER_MULTICAST (1 << 2) 399#define WPI_FILTER_NODECRYPT (1 << 3) 400#define WPI_FILTER_BSS (1 << 5) 401#define WPI_FILTER_BEACON (1 << 6) 402#define WPI_FILTER_ASSOC (1 << 7) /* Accept associaton requests. */ 403 404 uint8_t chan; 405 uint16_t reserved5; 406} __packed; 407 408/* Structure for command WPI_CMD_RXON_ASSOC. */ 409struct wpi_assoc { 410 uint32_t flags; 411 uint32_t filter; 412 uint8_t ofdm_mask; 413 uint8_t cck_mask; 414 uint16_t reserved; 415} __packed; 416 417/* Structure for command WPI_CMD_EDCA_PARAMS. */ 418struct wpi_edca_params { 419 uint32_t flags; 420#define WPI_EDCA_UPDATE (1 << 0) 421 422 struct { 423 uint16_t cwmin; 424 uint16_t cwmax; 425 uint8_t aifsn; 426 uint8_t reserved; 427 uint16_t txoplimit; 428 } __packed ac[WME_NUM_AC]; 429} __packed; 430 431/* Structure for command WPI_CMD_TIMING. */ 432struct wpi_cmd_timing { 433 uint64_t tstamp; 434 uint16_t bintval; 435 uint16_t atim; 436 uint32_t binitval; 437 uint16_t lintval; 438 uint16_t reserved; 439} __packed; 440 441/* Structure for command WPI_CMD_ADD_NODE. */ 442struct wpi_node_info { 443 uint8_t control; 444#define WPI_NODE_UPDATE (1 << 0) 445 446 uint8_t reserved1[3]; 447 uint8_t macaddr[IEEE80211_ADDR_LEN]; 448 uint16_t reserved2; 449 uint8_t id; 450#define WPI_ID_BSS 0 451#define WPI_ID_IBSS_MIN 2 452#define WPI_ID_IBSS_MAX 23 453#define WPI_ID_BROADCAST 24 454#define WPI_ID_UNDEFINED (uint8_t)-1 455 456 uint8_t flags; 457#define WPI_FLAG_KEY_SET (1 << 0) 458 459 uint16_t reserved3; 460 uint16_t kflags; 461#define WPI_KFLAG_CCMP (1 << 1) 462#define WPI_KFLAG_KID(kid) ((kid) << 8) 463#define WPI_KFLAG_MULTICAST (1 << 14) 464 465 uint8_t tsc2; 466 uint8_t reserved4; 467 uint16_t ttak[5]; 468 uint16_t reserved5; 469 uint8_t key[IEEE80211_KEYBUF_SIZE]; 470 uint32_t action; 471#define WPI_ACTION_SET_RATE (1 << 2) 472 473 uint32_t mask; 474 uint16_t tid; 475 uint8_t plcp; 476 uint8_t antenna; 477#define WPI_ANTENNA_A (1 << 6) 478#define WPI_ANTENNA_B (1 << 7) 479#define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 480 481 uint8_t add_imm; 482 uint8_t del_imm; 483 uint16_t add_imm_start; 484} __packed; 485 486/* Structure for command WPI_CMD_DEL_NODE. */ 487struct wpi_cmd_del_node { 488 uint8_t count; 489 uint8_t reserved1[3]; 490 uint8_t macaddr[IEEE80211_ADDR_LEN]; 491 uint16_t reserved2; 492} __packed; 493 494/* Structure for command WPI_CMD_TX_DATA. */ 495struct wpi_cmd_data { 496 uint16_t len; 497 uint16_t lnext; 498 uint32_t flags; 499#define WPI_TX_NEED_RTS (1 << 1) 500#define WPI_TX_NEED_CTS (1 << 2) 501#define WPI_TX_NEED_ACK (1 << 3) 502#define WPI_TX_FULL_TXOP (1 << 7) 503#define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 504#define WPI_TX_AUTO_SEQ (1 << 13) 505#define WPI_TX_MORE_FRAG (1 << 14) 506#define WPI_TX_INSERT_TSTAMP (1 << 16) 507 508 uint8_t plcp; 509 uint8_t id; 510 uint8_t tid; 511 uint8_t security; 512#define WPI_CIPHER_WEP 1 513#define WPI_CIPHER_CCMP 2 514#define WPI_CIPHER_TKIP 3 515#define WPI_CIPHER_WEP104 9 516 517 uint8_t key[IEEE80211_KEYBUF_SIZE]; 518 uint8_t tkip[IEEE80211_WEP_MICLEN]; 519 uint32_t fnext; 520#define WPI_NEXT_STA_ID(id) ((id) << 8) 521 522 uint32_t lifetime; 523#define WPI_LIFETIME_INFINITE 0xffffffff 524 525 uint8_t ofdm_mask; 526 uint8_t cck_mask; 527 uint8_t rts_ntries; 528 uint8_t data_ntries; 529 uint16_t timeout; 530 uint16_t txop; 531} __packed; 532 533/* Structure for command WPI_CMD_SET_BEACON. */ 534struct wpi_cmd_beacon { 535 uint16_t len; 536 uint16_t reserved1; 537 uint32_t flags; /* same as wpi_cmd_data */ 538 uint8_t plcp; 539 uint8_t id; 540 uint8_t reserved2[30]; 541 uint32_t lifetime; 542 uint8_t ofdm_mask; 543 uint8_t cck_mask; 544 uint16_t reserved3[3]; 545 uint16_t tim; 546 uint8_t timsz; 547 uint8_t reserved4; 548} __packed; 549 550/* Structure for notification WPI_BEACON_MISSED. */ 551struct wpi_beacon_missed { 552 uint32_t consecutive; 553 uint32_t total; 554 uint32_t expected; 555 uint32_t received; 556} __packed; 557 558/* Structure for command WPI_CMD_MRR_SETUP. */ 559#define WPI_RIDX_MAX 11 560struct wpi_mrr_setup { 561 uint32_t which; 562#define WPI_MRR_CTL 0 563#define WPI_MRR_DATA 1 564 565 struct { 566 uint8_t plcp; 567 uint8_t flags; 568 uint8_t ntries; 569#define WPI_NTRIES_DEFAULT 2 570 571 uint8_t next; 572 } __packed rates[WPI_RIDX_MAX + 1]; 573} __packed; 574 575/* Structure for command WPI_CMD_SET_LED. */ 576struct wpi_cmd_led { 577 uint32_t unit; /* multiplier (in usecs) */ 578 uint8_t which; 579#define WPI_LED_ACTIVITY 1 580#define WPI_LED_LINK 2 581 582 uint8_t off; 583 uint8_t on; 584 uint8_t reserved; 585} __packed; 586 587/* Structure for command WPI_CMD_SET_POWER_MODE. */ 588struct wpi_pmgt_cmd { 589 uint16_t flags; 590#define WPI_PS_ALLOW_SLEEP (1 << 0) 591#define WPI_PS_NOTIFY (1 << 1) 592#define WPI_PS_SLEEP_OVER_DTIM (1 << 2) 593#define WPI_PS_PCI_PMGT (1 << 3) 594 595 uint8_t reserved[2]; 596 uint32_t rxtimeout; 597 uint32_t txtimeout; 598 uint32_t intval[5]; 599} __packed; 600 601/* Structures for command WPI_CMD_SCAN. */ 602#define WPI_SCAN_MAX_ESSIDS 4 603struct wpi_scan_essid { 604 uint8_t id; 605 uint8_t len; 606 uint8_t data[IEEE80211_NWID_LEN]; 607} __packed; 608 609struct wpi_scan_hdr { 610 uint16_t len; 611 uint8_t reserved1; 612 uint8_t nchan; 613 uint16_t quiet_time; /* timeout in milliseconds */ 614#define WPI_QUIET_TIME_DEFAULT 10 615 616 uint16_t quiet_threshold; /* min # of packets */ 617 uint16_t crc_threshold; 618 uint16_t reserved2; 619 uint32_t max_svc; /* background scans */ 620 uint32_t pause_svc; /* background scans */ 621#define WPI_PAUSE_MAX_TIME ((1 << 20) - 1) 622#define WPI_PAUSE_SCAN(nbeacons, time) ((nbeacons << 24) | time) 623 624 uint32_t flags; 625 uint32_t filter; 626 627 /* Followed by a struct wpi_cmd_data. */ 628 /* Followed by an array of 4 structs wpi_scan_essid. */ 629 /* Followed by probe request body. */ 630 /* Followed by an array of ``nchan'' structs wpi_scan_chan. */ 631} __packed; 632 633struct wpi_scan_chan { 634 uint8_t flags; 635#define WPI_CHAN_ACTIVE (1 << 0) 636#define WPI_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 637 638 uint8_t chan; 639 uint8_t rf_gain; 640 uint8_t dsp_gain; 641 uint16_t active; /* msecs */ 642 uint16_t passive; /* msecs */ 643} __packed; 644 645#define WPI_SCAN_CRC_TH_DEFAULT htole16(1) 646#define WPI_SCAN_CRC_TH_NEVER htole16(0xffff) 647 648/* Maximum size of a scan command. */ 649#define WPI_SCAN_MAXSZ (MCLBYTES - 4) 650 651#define WPI_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 652#define WPI_ACTIVE_DWELL_TIME_5GHZ (20) 653#define WPI_ACTIVE_DWELL_FACTOR_2GHZ ( 3) 654#define WPI_ACTIVE_DWELL_FACTOR_5GHZ ( 2) 655 656#define WPI_PASSIVE_DWELL_TIME_2GHZ ( 20) 657#define WPI_PASSIVE_DWELL_TIME_5GHZ ( 10) 658#define WPI_PASSIVE_DWELL_BASE (100) 659#define WPI_CHANNEL_TUNE_TIME ( 6) 660 661/* Structure for command WPI_CMD_TXPOWER. */ 662struct wpi_cmd_txpower { 663 uint8_t band; 664#define WPI_BAND_5GHZ 0 665#define WPI_BAND_2GHZ 1 666 667 uint8_t reserved; 668 uint16_t chan; 669 670 struct { 671 uint8_t plcp; 672 uint8_t rf_gain; 673 uint8_t dsp_gain; 674 uint8_t reserved; 675 } __packed rates[WPI_RIDX_MAX + 1]; 676 677} __packed; 678 679/* Structure for command WPI_CMD_BT_COEX. */ 680struct wpi_bluetooth { 681 uint8_t flags; 682#define WPI_BT_COEX_DISABLE 0 683#define WPI_BT_COEX_MODE_2WIRE 1 684#define WPI_BT_COEX_MODE_3WIRE 2 685#define WPI_BT_COEX_MODE_4WIRE 3 686 687 uint8_t lead_time; 688#define WPI_BT_LEAD_TIME_DEF 30 689 690 uint8_t max_kill; 691#define WPI_BT_MAX_KILL_DEF 5 692 693 uint8_t reserved; 694 uint32_t kill_ack; 695 uint32_t kill_cts; 696} __packed; 697 698/* Structure for WPI_UC_READY notification. */ 699struct wpi_ucode_info { 700 uint8_t minor; 701 uint8_t major; 702 uint16_t reserved1; 703 uint8_t revision[8]; 704 uint8_t type; 705 uint8_t subtype; 706 uint16_t reserved2; 707 uint32_t logptr; 708 uint32_t errptr; 709 uint32_t tstamp; 710 uint32_t valid; 711} __packed; 712 713/* Structure for WPI_START_SCAN notification. */ 714struct wpi_start_scan { 715 uint64_t tstamp; 716 uint32_t tbeacon; 717 uint8_t chan; 718 uint8_t band; 719 uint16_t reserved; 720 uint32_t status; 721} __packed; 722 723/* Structure for WPI_STOP_SCAN notification. */ 724struct wpi_stop_scan { 725 uint8_t nchan; 726 uint8_t status; 727#define WPI_SCAN_COMPLETED 1 728#define WPI_SCAN_ABORTED 2 729 730 uint8_t reserved; 731 uint8_t chan; 732 uint64_t tsf; 733} __packed; 734 735/* Structures for WPI_{RX,BEACON}_STATISTICS notification. */ 736struct wpi_rx_phy_stats { 737 uint32_t ina; 738 uint32_t fina; 739 uint32_t bad_plcp; 740 uint32_t bad_crc32; 741 uint32_t overrun; 742 uint32_t eoverrun; 743 uint32_t good_crc32; 744 uint32_t fa; 745 uint32_t bad_fina_sync; 746 uint32_t sfd_timeout; 747 uint32_t fina_timeout; 748 uint32_t no_rts_ack; 749 uint32_t rxe_limit; 750 uint32_t ack; 751 uint32_t cts; 752} __packed; 753 754struct wpi_rx_general_stats { 755 uint32_t bad_cts; 756 uint32_t bad_ack; 757 uint32_t not_bss; 758 uint32_t filtered; 759 uint32_t bad_chan; 760} __packed; 761 762struct wpi_rx_stats { 763 struct wpi_rx_phy_stats ofdm; 764 struct wpi_rx_phy_stats cck; 765 struct wpi_rx_general_stats general; 766} __packed; 767 768struct wpi_tx_stats { 769 uint32_t preamble; 770 uint32_t rx_detected; 771 uint32_t bt_defer; 772 uint32_t bt_kill; 773 uint32_t short_len; 774 uint32_t cts_timeout; 775 uint32_t ack_timeout; 776 uint32_t exp_ack; 777 uint32_t ack; 778} __packed; 779 780struct wpi_general_stats { 781 uint32_t temp; 782 uint32_t burst_check; 783 uint32_t burst; 784 uint32_t reserved[4]; 785 uint32_t sleep; 786 uint32_t slot_out; 787 uint32_t slot_idle; 788 uint32_t ttl_tstamp; 789 uint32_t tx_ant_a; 790 uint32_t tx_ant_b; 791 uint32_t exec; 792 uint32_t probe; 793} __packed; 794 795struct wpi_stats { 796 uint32_t flags; 797 struct wpi_rx_stats rx; 798 struct wpi_tx_stats tx; 799 struct wpi_general_stats general; 800} __packed; 801 802/* Possible flags for command WPI_CMD_GET_STATISTICS. */ 803#define WPI_STATISTICS_BEACON_DISABLE (1 << 1) 804 805/* Firmware error dump entry. */ 806struct wpi_fw_dump { 807 uint32_t desc; 808 uint32_t time; 809 uint32_t blink[2]; 810 uint32_t ilink[2]; 811 uint32_t data; 812} __packed; 813 814/* Firmware image file header. */ 815struct wpi_firmware_hdr { 816#define WPI_FW_MINVERSION 2144 817#define WPI_FW_NAME "wpifw" 818 819 uint16_t driver; 820 uint8_t minor; 821 uint8_t major; 822 uint32_t rtextsz; 823 uint32_t rdatasz; 824 uint32_t itextsz; 825 uint32_t idatasz; 826 uint32_t btextsz; 827} __packed; 828 829#define WPI_FW_TEXT_MAXSZ ( 80 * 1024 ) 830#define WPI_FW_DATA_MAXSZ ( 32 * 1024 ) 831#define WPI_FW_BOOT_TEXT_MAXSZ 1024 832 833#define WPI_FW_UPDATED (1U << 31 ) 834 835/* 836 * Offsets into EEPROM. 837 */ 838#define WPI_EEPROM_MAC 0x015 839#define WPI_EEPROM_REVISION 0x035 840#define WPI_EEPROM_SKU_CAP 0x045 841#define WPI_EEPROM_TYPE 0x04a 842#define WPI_EEPROM_DOMAIN 0x060 843#define WPI_EEPROM_BAND1 0x063 844#define WPI_EEPROM_BAND2 0x072 845#define WPI_EEPROM_BAND3 0x080 846#define WPI_EEPROM_BAND4 0x08d 847#define WPI_EEPROM_BAND5 0x099 848#define WPI_EEPROM_POWER_GRP 0x100 849 850struct wpi_eeprom_chan { 851 uint8_t flags; 852#define WPI_EEPROM_CHAN_VALID (1 << 0) 853#define WPI_EEPROM_CHAN_IBSS (1 << 1) 854#define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 855#define WPI_EEPROM_CHAN_RADAR (1 << 4) 856 857 int8_t maxpwr; 858} __packed; 859 860struct wpi_eeprom_sample { 861 uint8_t index; 862 int8_t power; 863 uint16_t volt; 864} __packed; 865 866#define WPI_POWER_GROUPS_COUNT 5 867struct wpi_eeprom_group { 868 struct wpi_eeprom_sample samples[5]; 869 int32_t coef[5]; 870 int32_t corr[5]; 871 int8_t maxpwr; 872 uint8_t chan; 873 int16_t temp; 874} __packed; 875 876#define WPI_CHAN_BANDS_COUNT 5 877#define WPI_MAX_CHAN_PER_BAND 14 878static const struct wpi_chan_band { 879 uint32_t addr; /* offset in EEPROM */ 880 uint8_t nchan; 881 uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 882} wpi_bands[] = { 883 /* 20MHz channels, 2GHz band. */ 884 { WPI_EEPROM_BAND1, 14, 885 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 886 /* 20MHz channels, 5GHz band. */ 887 { WPI_EEPROM_BAND2, 13, 888 { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 889 { WPI_EEPROM_BAND3, 12, 890 { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 891 { WPI_EEPROM_BAND4, 11, 892 { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 893 { WPI_EEPROM_BAND5, 6, 894 { 145, 149, 153, 157, 161, 165 } } 895}; 896 897/* HW rate indices. */ 898#define WPI_RIDX_OFDM6 0 899#define WPI_RIDX_OFDM36 5 900#define WPI_RIDX_OFDM48 6 901#define WPI_RIDX_OFDM54 7 902#define WPI_RIDX_CCK1 8 903#define WPI_RIDX_CCK2 9 904#define WPI_RIDX_CCK11 11 905 906static const uint8_t wpi_ridx_to_plcp[] = { 907 /* OFDM: IEEE Std 802.11a-1999, pp. 14 Table 80 */ 908 /* R1-R4 (ral/ural is R4-R1) */ 909 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 910 /* CCK: device-dependent */ 911 10, 20, 55, 110 912}; 913 914#define WPI_MAX_PWR_INDEX 77 915 916/* 917 * RF Tx gain values from highest to lowest power (values obtained from 918 * the reference driver.) 919 */ 920static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 921 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 922 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 923 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 924 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 925 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 926 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 927 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 928 0x03 929}; 930 931static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 932 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 933 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 934 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 935 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 936 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 937 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 938 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 939 0x03 940}; 941 942/* 943 * DSP pre-DAC gain values from highest to lowest power (values obtained 944 * from the reference driver.) 945 */ 946static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 947 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 948 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 949 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 950 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 951 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 952 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 953 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 954 0x5f 955}; 956 957static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 958 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 959 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 960 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 961 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 962 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 963 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 964 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 965 0x78 966}; 967 968/* 969 * Power saving settings (values obtained from the reference driver.) 970 */ 971#define WPI_NDTIMRANGES 2 972#define WPI_NPOWERLEVELS 6 973static const struct wpi_pmgt { 974 uint32_t rxtimeout; 975 uint32_t txtimeout; 976 uint32_t intval[5]; 977 uint8_t skip_dtim; 978} wpi_pmgt[WPI_NDTIMRANGES][WPI_NPOWERLEVELS] = { 979 /* DTIM <= 10 */ 980 { 981 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 982 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 983 { 200, 300, { 2, 4, 6, 7, 7 }, 0 }, /* PS level 2 */ 984 { 50, 100, { 2, 6, 9, 9, 10 }, 0 }, /* PS level 3 */ 985 { 50, 25, { 2, 7, 9, 9, 10 }, 1 }, /* PS level 4 */ 986 { 25, 25, { 4, 7, 10, 10, 10 }, 1 } /* PS level 5 */ 987 }, 988 /* DTIM >= 11 */ 989 { 990 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 991 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 992 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 993 { 50, 100, { 2, 6, 9, 9, -1 }, 0 }, /* PS level 3 */ 994 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 995 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 996 } 997}; 998 999/* Firmware errors. */ 1000static const char * const wpi_fw_errmsg[] = { 1001 "OK", 1002 "FAIL", 1003 "BAD_PARAM", 1004 "BAD_CHECKSUM", 1005 "NMI_INTERRUPT", 1006 "SYSASSERT", 1007 "FATAL_ERROR" 1008}; 1009 1010#define WPI_READ(sc, reg) \ 1011 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1012 1013#define WPI_WRITE(sc, reg, val) \ 1014 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1015 1016#define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 1017 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 1018 (datap), (count)) 1019 1020#define WPI_SETBITS(sc, reg, mask) \ 1021 WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask)) 1022 1023#define WPI_CLRBITS(sc, reg, mask) \ 1024 WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask)) 1025 1026#define WPI_BARRIER_WRITE(sc) \ 1027 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1028 BUS_SPACE_BARRIER_WRITE) 1029 1030#define WPI_BARRIER_READ_WRITE(sc) \ 1031 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1032 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1033